Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'char-misc-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc and other driver subsystem updates from Greg KH:
"Here is the large set of driver changes for char/misc drivers and
other smaller driver subsystems that flow through this git tree.
Included in here are:
- New IIO drivers and features and improvments in that subsystem
- New hwtracing drivers and additions to that subsystem
- lots of interconnect changes and new drivers as that subsystem
seems under very active development recently. This required also
merging in the icc subsystem changes through this tree.
- FPGA driver updates
- counter subsystem and driver updates
- MHI driver updates
- nvmem driver updates
- documentation updates
- Other smaller driver updates and fixes, full details in the
shortlog
All of these have been in linux-next for a while with no reported
problems"
* tag 'char-misc-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (223 commits)
scripts/tags.sh: fix incompatibility with PCRE2
firmware: coreboot: Remove GOOGLE_COREBOOT_TABLE_ACPI/OF Kconfig entries
mei: lower the log level for non-fatal failed messages
mei: bus: disallow driver match while dismantling device
misc: vmw_balloon: fix memory leak with using debugfs_lookup()
nvmem: stm32: fix OPTEE dependency
dt-bindings: nvmem: qfprom: add IPQ8074 compatible
nvmem: qcom-spmi-sdam: register at device init time
nvmem: rave-sp-eeprm: fix kernel-doc bad line warning
nvmem: stm32: detect bsec pta presence for STM32MP15x
nvmem: stm32: add OP-TEE support for STM32MP13x
nvmem: core: use nvmem_add_one_cell() in nvmem_add_cells_from_of()
nvmem: core: add nvmem_add_one_cell()
nvmem: core: drop the removal of the cells in nvmem_add_cells()
nvmem: core: move struct nvmem_cell_info to nvmem-provider.h
nvmem: core: add an index parameter to the cell
of: property: add #nvmem-cell-cells property
of: property: make #.*-cells optional for simple props
of: base: add of_parse_phandle_with_optional_args()
net: add helper eth_addr_add()
...
+12517
-1945
+1
-1
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
+1
-1
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
···
236
236
Date: November 2014
237
237
KernelVersion: 3.19
238
238
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
239
-
Description: (RW) Holds the trace ID that will appear in the trace stream
239
+
Description: (RO) Holds the trace ID that will appear in the trace stream
240
240
coming from this trace entity.
241
241
242
242
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event
+13
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
+13
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
···
1
+
What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
2
+
Date: January 2023
3
+
KernelVersion 6.2
4
+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
5
+
Description:
6
+
(Write) Run integration test for tpdm. Integration test
7
+
will generate test data for tpdm. It can help to make
8
+
sure that the trace path is enabled and the link configurations
9
+
are fine.
10
+
11
+
Accepts only one of the 2 values - 1 or 2.
12
+
1 : Generate 64 bits data
13
+
2 : Generate 32 bits data
+31
Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb
+31
Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb
···
1
+
What: /sys/bus/coresight/devices/ultra_smb<N>/enable_sink
2
+
Date: January 2023
3
+
KernelVersion: 6.3
4
+
Contact: Junhao He <hejunhao3@huawei.com>
5
+
Description: (RW) Add/remove a SMB device from a trace path. There can be
6
+
multiple sources for a single SMB device.
7
+
8
+
What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_size
9
+
Date: January 2023
10
+
KernelVersion: 6.3
11
+
Contact: Junhao He <hejunhao3@huawei.com>
12
+
Description: (RO) Shows the buffer size of each UltraSoc SMB device.
13
+
14
+
What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_status
15
+
Date: January 2023
16
+
KernelVersion: 6.3
17
+
Contact: Junhao He <hejunhao3@huawei.com>
18
+
Description: (RO) Shows the value of UltraSoc SMB status register.
19
+
BIT(0) is zero means buffer is empty.
20
+
21
+
What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/read_pos
22
+
Date: January 2023
23
+
KernelVersion: 6.3
24
+
Contact: Junhao He <hejunhao3@huawei.com>
25
+
Description: (RO) Shows the value of UltraSoc SMB Read Pointer register.
26
+
27
+
What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/write_pos
28
+
Date: January 2023
29
+
KernelVersion: 6.3
30
+
Contact: Junhao He <hejunhao3@huawei.com>
31
+
Description: (RO) Shows the value of UltraSoc SMB Write Pointer register.
+18
Documentation/ABI/testing/sysfs-driver-uacce
+18
Documentation/ABI/testing/sysfs-driver-uacce
···
19
19
Description: Available instances left of the device
20
20
Return -ENODEV if uacce_ops get_available_instances is not provided
21
21
22
+
What: /sys/class/uacce/<dev_name>/isolate_strategy
23
+
Date: Nov 2022
24
+
KernelVersion: 6.1
25
+
Contact: linux-accelerators@lists.ozlabs.org
26
+
Description: (RW) A sysfs node that configure the error threshold for the hardware
27
+
isolation strategy. This size is a configured integer value, which is the
28
+
number of threshold for hardware errors occurred in one hour. The default is 0.
29
+
0 means never isolate the device. The maximum value is 65535. You can write
30
+
a number of threshold based on your hardware.
31
+
32
+
What: /sys/class/uacce/<dev_name>/isolate
33
+
Date: Nov 2022
34
+
KernelVersion: 6.1
35
+
Contact: linux-accelerators@lists.ozlabs.org
36
+
Description: (R) A sysfs node that read the device isolated state. The value 1
37
+
means the device is unavailable. The 0 means the device is
38
+
available.
39
+
22
40
What: /sys/class/uacce/<dev_name>/algorithms
23
41
Date: Feb 2020
24
42
KernelVersion: 5.7
+16
Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager
+16
Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager
···
1
+
What: /sys/devices/platform/amba_pl/<dev>/errcnt
2
+
Date: Nov 2022
3
+
Contact: appana.durga.kedareswara.rao@amd.com
4
+
Description: This control file provides the fault detection count.
5
+
This file cannot be written.
6
+
Example:
7
+
# cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/errcnt
8
+
1
9
+
10
+
What: /sys/devices/platform/amba_pl/<dev>/dis_block_break
11
+
Date: Nov 2022
12
+
Contact: appana.durga.kedareswara.rao@amd.com
13
+
Description: Write any value to it, This control file enables the break signal.
14
+
This file is write only.
15
+
Example:
16
+
# echo <any value> > /sys/devices/platform/amba_pl/44a10000.tmr_manager/dis_block_break
+129
Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
+129
Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Trace, Profiling and Diagnostics Aggregator - TPDA
9
+
10
+
description: |
11
+
TPDAs are responsible for packetization and timestamping of data sets
12
+
utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or
13
+
more attached TPDM and pushing the resultant (packetized) data out a
14
+
master ATB interface. Performing an arbitrated ATB interleaving (funneling)
15
+
task for free-flowing data from TPDM (i.e. CMB and DSB data set flows).
16
+
17
+
There is no strict binding between TPDM and TPDA. TPDA can have multiple
18
+
TPDMs connect to it. But There must be only one TPDA in the path from the
19
+
TPDM source to TMC sink. TPDM can directly connect to TPDA's inport or
20
+
connect to funnel which will connect to TPDA's inport.
21
+
22
+
We can use the commands are similar to the below to validate TPDMs.
23
+
Enable coresight sink first.
24
+
25
+
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
26
+
echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
27
+
echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
28
+
echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
29
+
30
+
The test data will be collected in the coresight sink which is enabled.
31
+
If rwp register of the sink is keeping updating when do integration_test
32
+
(by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM
33
+
to sink.
34
+
35
+
maintainers:
36
+
- Mao Jinlong <quic_jinlmao@quicinc.com>
37
+
- Tao Zhang <quic_taozha@quicinc.com>
38
+
39
+
# Need a custom select here or 'arm,primecell' will match on lots of nodes
40
+
select:
41
+
properties:
42
+
compatible:
43
+
contains:
44
+
enum:
45
+
- qcom,coresight-tpda
46
+
required:
47
+
- compatible
48
+
49
+
properties:
50
+
$nodename:
51
+
pattern: "^tpda(@[0-9a-f]+)$"
52
+
compatible:
53
+
items:
54
+
- const: qcom,coresight-tpda
55
+
- const: arm,primecell
56
+
57
+
reg:
58
+
minItems: 1
59
+
maxItems: 2
60
+
61
+
clocks:
62
+
maxItems: 1
63
+
64
+
clock-names:
65
+
items:
66
+
- const: apb_pclk
67
+
68
+
in-ports:
69
+
type: object
70
+
description: |
71
+
Input connections from TPDM to TPDA
72
+
$ref: /schemas/graph.yaml#/properties/ports
73
+
74
+
out-ports:
75
+
type: object
76
+
description: |
77
+
Output connections from the TPDA to legacy CoreSight trace bus.
78
+
$ref: /schemas/graph.yaml#/properties/ports
79
+
80
+
properties:
81
+
port:
82
+
description:
83
+
Output connection from the TPDA to legacy CoreSight Trace bus.
84
+
$ref: /schemas/graph.yaml#/properties/port
85
+
86
+
required:
87
+
- compatible
88
+
- reg
89
+
- clocks
90
+
- clock-names
91
+
- in-ports
92
+
- out-ports
93
+
94
+
additionalProperties: false
95
+
96
+
examples:
97
+
# minimum tpda definition.
98
+
- |
99
+
tpda@6004000 {
100
+
compatible = "qcom,coresight-tpda", "arm,primecell";
101
+
reg = <0x6004000 0x1000>;
102
+
103
+
clocks = <&aoss_qmp>;
104
+
clock-names = "apb_pclk";
105
+
106
+
in-ports {
107
+
#address-cells = <1>;
108
+
#size-cells = <0>;
109
+
110
+
port@0 {
111
+
reg = <0>;
112
+
tpda_qdss_0_in_tpdm_dcc: endpoint {
113
+
remote-endpoint =
114
+
<&tpdm_dcc_out_tpda_qdss_0>;
115
+
};
116
+
};
117
+
};
118
+
119
+
out-ports {
120
+
port {
121
+
tpda_qdss_out_funnel_in0: endpoint {
122
+
remote-endpoint =
123
+
<&funnel_in0_in_tpda_qdss>;
124
+
};
125
+
};
126
+
};
127
+
};
128
+
129
+
...
+93
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
+93
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Trace, Profiling and Diagnostics Monitor - TPDM
9
+
10
+
description: |
11
+
The TPDM or Monitor serves as data collection component for various dataset
12
+
types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
13
+
Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
14
+
Single Bit (DSB). It performs data collection in the data producing clock
15
+
domain and transfers it to the data collection time domain, generally ATB
16
+
clock domain.
17
+
18
+
The primary use case of the TPDM is to collect data from different data
19
+
sources and send it to a TPDA for packetization, timestamping, and funneling.
20
+
21
+
maintainers:
22
+
- Mao Jinlong <quic_jinlmao@quicinc.com>
23
+
- Tao Zhang <quic_taozha@quicinc.com>
24
+
25
+
# Need a custom select here or 'arm,primecell' will match on lots of nodes
26
+
select:
27
+
properties:
28
+
compatible:
29
+
contains:
30
+
enum:
31
+
- qcom,coresight-tpdm
32
+
required:
33
+
- compatible
34
+
35
+
properties:
36
+
$nodename:
37
+
pattern: "^tpdm(@[0-9a-f]+)$"
38
+
compatible:
39
+
items:
40
+
- const: qcom,coresight-tpdm
41
+
- const: arm,primecell
42
+
43
+
reg:
44
+
minItems: 1
45
+
maxItems: 2
46
+
47
+
clocks:
48
+
maxItems: 1
49
+
50
+
clock-names:
51
+
items:
52
+
- const: apb_pclk
53
+
54
+
out-ports:
55
+
description: |
56
+
Output connections from the TPDM to coresight funnel/TPDA.
57
+
$ref: /schemas/graph.yaml#/properties/ports
58
+
59
+
properties:
60
+
port:
61
+
description: Output connection from the TPDM to coresight
62
+
funnel/TPDA.
63
+
$ref: /schemas/graph.yaml#/properties/port
64
+
65
+
required:
66
+
- compatible
67
+
- reg
68
+
- clocks
69
+
- clock-names
70
+
71
+
additionalProperties: false
72
+
73
+
examples:
74
+
# minimum TPDM definition. TPDM connect to coresight TPDA.
75
+
- |
76
+
tpdm@684c000 {
77
+
compatible = "qcom,coresight-tpdm", "arm,primecell";
78
+
reg = <0x0684c000 0x1000>;
79
+
80
+
clocks = <&aoss_qmp>;
81
+
clock-names = "apb_pclk";
82
+
83
+
out-ports {
84
+
port {
85
+
tpdm_prng_out_tpda_qdss: endpoint {
86
+
remote-endpoint =
87
+
<&tpda_qdss_in_tpdm_prng>;
88
+
};
89
+
};
90
+
};
91
+
};
92
+
93
+
...
+1
-1
Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml
+2
-2
Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
+2
-2
Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
···
49
49
- |
50
50
#include <dt-bindings/gpio/gpio.h>
51
51
#include <dt-bindings/interrupt-controller/irq.h>
52
-
i2c0 {
52
+
i2c {
53
53
#address-cells = <1>;
54
54
#size-cells = <0>;
55
55
···
64
64
- |
65
65
#include <dt-bindings/gpio/gpio.h>
66
66
#include <dt-bindings/interrupt-controller/irq.h>
67
-
spi0 {
67
+
spi {
68
68
#address-cells = <1>;
69
69
#size-cells = <0>;
70
70
+26
-26
Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml
+26
-26
Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml
···
58
58
59
59
examples:
60
60
- |
61
-
#include <dt-bindings/gpio/gpio.h>
62
-
#include <dt-bindings/interrupt-controller/irq.h>
63
-
i2c {
64
-
#address-cells = <1>;
65
-
#size-cells = <0>;
61
+
#include <dt-bindings/gpio/gpio.h>
62
+
#include <dt-bindings/interrupt-controller/irq.h>
63
+
i2c {
64
+
#address-cells = <1>;
65
+
#size-cells = <0>;
66
66
67
-
/* Example for a I2C device node */
68
-
accelerometer@1d {
69
-
compatible = "adi,adxl355";
70
-
reg = <0x1d>;
71
-
interrupt-parent = <&gpio>;
72
-
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
73
-
interrupt-names = "DRDY";
74
-
};
67
+
/* Example for a I2C device node */
68
+
accelerometer@1d {
69
+
compatible = "adi,adxl355";
70
+
reg = <0x1d>;
71
+
interrupt-parent = <&gpio>;
72
+
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
73
+
interrupt-names = "DRDY";
75
74
};
75
+
};
76
76
- |
77
-
#include <dt-bindings/gpio/gpio.h>
78
-
#include <dt-bindings/interrupt-controller/irq.h>
79
-
spi {
80
-
#address-cells = <1>;
81
-
#size-cells = <0>;
77
+
#include <dt-bindings/gpio/gpio.h>
78
+
#include <dt-bindings/interrupt-controller/irq.h>
79
+
spi {
80
+
#address-cells = <1>;
81
+
#size-cells = <0>;
82
82
83
-
accelerometer@0 {
84
-
compatible = "adi,adxl355";
85
-
reg = <0>;
86
-
spi-max-frequency = <1000000>;
87
-
interrupt-parent = <&gpio>;
88
-
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
89
-
interrupt-names = "DRDY";
90
-
};
83
+
accelerometer@0 {
84
+
compatible = "adi,adxl355";
85
+
reg = <0>;
86
+
spi-max-frequency = <1000000>;
87
+
interrupt-parent = <&gpio>;
88
+
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
89
+
interrupt-names = "DRDY";
91
90
};
91
+
};
+24
-24
Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml
+24
-24
Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml
···
37
37
38
38
examples:
39
39
- |
40
-
#include <dt-bindings/gpio/gpio.h>
41
-
#include <dt-bindings/interrupt-controller/irq.h>
42
-
i2c0 {
43
-
#address-cells = <1>;
44
-
#size-cells = <0>;
40
+
#include <dt-bindings/gpio/gpio.h>
41
+
#include <dt-bindings/interrupt-controller/irq.h>
42
+
i2c {
43
+
#address-cells = <1>;
44
+
#size-cells = <0>;
45
45
46
-
/* Example for a I2C device node */
47
-
accelerometer@53 {
48
-
compatible = "adi,adxl372";
49
-
reg = <0x53>;
50
-
interrupt-parent = <&gpio>;
51
-
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
52
-
};
46
+
/* Example for a I2C device node */
47
+
accelerometer@53 {
48
+
compatible = "adi,adxl372";
49
+
reg = <0x53>;
50
+
interrupt-parent = <&gpio>;
51
+
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
53
52
};
53
+
};
54
54
- |
55
-
#include <dt-bindings/gpio/gpio.h>
56
-
#include <dt-bindings/interrupt-controller/irq.h>
57
-
spi0 {
58
-
#address-cells = <1>;
59
-
#size-cells = <0>;
55
+
#include <dt-bindings/gpio/gpio.h>
56
+
#include <dt-bindings/interrupt-controller/irq.h>
57
+
spi {
58
+
#address-cells = <1>;
59
+
#size-cells = <0>;
60
60
61
-
accelerometer@0 {
62
-
compatible = "adi,adxl372";
63
-
reg = <0>;
64
-
spi-max-frequency = <1000000>;
65
-
interrupt-parent = <&gpio>;
66
-
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
67
-
};
61
+
accelerometer@0 {
62
+
compatible = "adi,adxl372";
63
+
reg = <0>;
64
+
spi-max-frequency = <1000000>;
65
+
interrupt-parent = <&gpio>;
66
+
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
68
67
};
68
+
};
+1
-1
Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml
+1
-1
Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml
+2
-3
Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml
+2
-3
Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml
···
1
1
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
-
3
2
%YAML 1.2
4
3
---
5
-
$id: "http://devicetree.org/schemas/iio/accel/memsensing,msa311.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/iio/accel/memsensing,msa311.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
6
8
7
title: MEMSensing digital 3-Axis accelerometer
9
8
+2
-2
Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml
+2
-2
Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml
···
50
50
examples:
51
51
- |
52
52
#include <dt-bindings/interrupt-controller/irq.h>
53
-
i2c0 {
53
+
i2c {
54
54
#address-cells = <1>;
55
55
#size-cells = <0>;
56
56
···
65
65
};
66
66
- |
67
67
#include <dt-bindings/interrupt-controller/irq.h>
68
-
spi0 {
68
+
spi {
69
69
#address-cells = <1>;
70
70
#size-cells = <0>;
71
71
+4
-4
Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml
+4
-4
Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml
···
44
44
#size-cells = <0>;
45
45
46
46
adc@2f {
47
-
compatible = "adi,ad7091r5";
48
-
reg = <0x2f>;
47
+
compatible = "adi,ad7091r5";
48
+
reg = <0x2f>;
49
49
50
-
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
51
-
interrupt-parent = <&gpio>;
50
+
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
51
+
interrupt-parent = <&gpio>;
52
52
};
53
53
};
54
54
...
+1
-1
Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml
+19
-19
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
+19
-19
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
···
99
99
100
100
examples:
101
101
- |
102
-
spi0 {
103
-
#address-cells = <1>;
104
-
#size-cells = <0>;
102
+
spi {
103
+
#address-cells = <1>;
104
+
#size-cells = <0>;
105
105
106
-
adc@0 {
107
-
compatible = "adi,ad7192";
108
-
reg = <0>;
109
-
spi-max-frequency = <1000000>;
110
-
spi-cpol;
111
-
spi-cpha;
112
-
clocks = <&ad7192_mclk>;
113
-
clock-names = "mclk";
114
-
interrupts = <25 0x2>;
115
-
interrupt-parent = <&gpio>;
116
-
dvdd-supply = <&dvdd>;
117
-
avdd-supply = <&avdd>;
106
+
adc@0 {
107
+
compatible = "adi,ad7192";
108
+
reg = <0>;
109
+
spi-max-frequency = <1000000>;
110
+
spi-cpol;
111
+
spi-cpha;
112
+
clocks = <&ad7192_mclk>;
113
+
clock-names = "mclk";
114
+
interrupts = <25 0x2>;
115
+
interrupt-parent = <&gpio>;
116
+
dvdd-supply = <&dvdd>;
117
+
avdd-supply = <&avdd>;
118
118
119
-
adi,refin2-pins-enable;
120
-
adi,rejection-60-Hz-enable;
121
-
adi,buffer-enable;
122
-
adi,burnout-currents-enable;
119
+
adi,refin2-pins-enable;
120
+
adi,rejection-60-Hz-enable;
121
+
adi,buffer-enable;
122
+
adi,burnout-currents-enable;
123
123
};
124
124
};
+1
-1
Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml
+17
-17
Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml
+17
-17
Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml
···
112
112
- |
113
113
#include <dt-bindings/gpio/gpio.h>
114
114
#include <dt-bindings/interrupt-controller/irq.h>
115
-
spi0 {
115
+
spi {
116
116
#address-cells = <1>;
117
117
#size-cells = <0>;
118
118
119
119
adc@0 {
120
-
compatible = "adi,ad7606-8";
121
-
reg = <0>;
122
-
spi-max-frequency = <1000000>;
123
-
spi-cpol;
124
-
spi-cpha;
120
+
compatible = "adi,ad7606-8";
121
+
reg = <0>;
122
+
spi-max-frequency = <1000000>;
123
+
spi-cpol;
124
+
spi-cpha;
125
125
126
-
avcc-supply = <&adc_vref>;
126
+
avcc-supply = <&adc_vref>;
127
127
128
-
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
129
-
interrupt-parent = <&gpio>;
128
+
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
129
+
interrupt-parent = <&gpio>;
130
130
131
-
adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
132
-
reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
133
-
adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
134
-
adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>,
135
-
<&gpio 23 GPIO_ACTIVE_HIGH>,
136
-
<&gpio 26 GPIO_ACTIVE_HIGH>;
137
-
standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
138
-
adi,sw-mode;
131
+
adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
132
+
reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
133
+
adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
134
+
adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>,
135
+
<&gpio 23 GPIO_ACTIVE_HIGH>,
136
+
<&gpio 26 GPIO_ACTIVE_HIGH>;
137
+
standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
138
+
adi,sw-mode;
139
139
};
140
140
};
141
141
...
+1
-1
Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
+9
-9
Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml
+9
-9
Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml
···
57
57
examples:
58
58
- |
59
59
i2c {
60
-
#address-cells = <1>;
61
-
#size-cells = <0>;
60
+
#address-cells = <1>;
61
+
#size-cells = <0>;
62
62
63
-
adc1: adc@28 {
64
-
reg = <0x28>;
65
-
compatible = "adi,ad7991";
66
-
interrupts = <13 2>;
67
-
interrupt-parent = <&gpio6>;
63
+
adc1: adc@28 {
64
+
reg = <0x28>;
65
+
compatible = "adi,ad7991";
66
+
interrupts = <13 2>;
67
+
interrupt-parent = <&gpio6>;
68
68
69
-
vcc-supply = <&vcc_3v3>;
70
-
vref-supply = <&adc_vref>;
69
+
vcc-supply = <&vcc_3v3>;
70
+
vref-supply = <&adc_vref>;
71
71
};
72
72
};
73
73
...
+4
-4
Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
+4
-4
Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
+5
-5
Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml
+5
-5
Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml
···
51
51
examples:
52
52
- |
53
53
axi-adc@44a00000 {
54
-
compatible = "adi,axi-adc-10.0.a";
55
-
reg = <0x44a00000 0x10000>;
56
-
dmas = <&rx_dma 0>;
57
-
dma-names = "rx";
54
+
compatible = "adi,axi-adc-10.0.a";
55
+
reg = <0x44a00000 0x10000>;
56
+
dmas = <&rx_dma 0>;
57
+
dma-names = "rx";
58
58
59
-
adi,adc-dev = <&spi_adc>;
59
+
adi,adc-dev = <&spi_adc>;
60
60
};
61
61
...
+1
-1
Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml
···
41
41
description: Startup time expressed in ms, it depends on SoC.
42
42
43
43
atmel,trigger-edge-type:
44
-
$ref: '/schemas/types.yaml#/definitions/uint32'
44
+
$ref: /schemas/types.yaml#/definitions/uint32
45
45
description:
46
46
One of possible edge types for the ADTRG hardware trigger pin.
47
47
When the specific edge type is detected, the conversion will
+2
-2
Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
+2
-2
Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/iio/adc/avia-hx711.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/iio/adc/avia-hx711.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: AVIA HX711 ADC chip for weight cells
8
8
+47
Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml
+47
Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/cirrus,ep9301-adc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cirrus Logic EP930x internal ADC
8
+
9
+
description: |
10
+
Cirrus Logic EP9301/EP9302 SoCs' internal ADC block.
11
+
12
+
User's manual:
13
+
https://cdn.embeddedts.com/resource-attachments/ts-7000_ep9301-ug.pdf
14
+
15
+
maintainers:
16
+
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
17
+
18
+
properties:
19
+
compatible:
20
+
const: cirrus,ep9301-adc
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
clocks:
26
+
maxItems: 1
27
+
28
+
interrupts:
29
+
maxItems: 1
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
- clocks
35
+
36
+
additionalProperties: false
37
+
38
+
examples:
39
+
- |
40
+
adc: adc@80900000 {
41
+
compatible = "cirrus,ep9301-adc";
42
+
reg = <0x80900000 0x28>;
43
+
clocks = <&syscon 24>;
44
+
interrupt-parent = <&vic1>;
45
+
interrupts = <30>;
46
+
};
47
+
...
+9
-9
Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml
+9
-9
Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml
···
2
2
# Copyright 2019-2020 Artur Rojek
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Ingenic JZ47xx ADC controller IIO
9
9
···
78
78
#include <dt-bindings/iio/adc/ingenic,adc.h>
79
79
80
80
adc@10070000 {
81
-
compatible = "ingenic,jz4740-adc";
82
-
#io-channel-cells = <1>;
81
+
compatible = "ingenic,jz4740-adc";
82
+
#io-channel-cells = <1>;
83
83
84
-
reg = <0x10070000 0x30>;
84
+
reg = <0x10070000 0x30>;
85
85
86
-
clocks = <&cgu JZ4740_CLK_ADC>;
87
-
clock-names = "adc";
86
+
clocks = <&cgu JZ4740_CLK_ADC>;
87
+
clock-names = "adc";
88
88
89
-
interrupt-parent = <&intc>;
90
-
interrupts = <18>;
89
+
interrupt-parent = <&intc>;
90
+
interrupts = <18>;
91
91
};
+2
-2
Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml
+2
-2
Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml
+2
-2
Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml
+2
-2
Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml
+2
-2
Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml
+2
-2
Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml
···
2
2
# Copyright 2019 Marcus Folkesson <marcus.folkesson@gmail.com>
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Microchip MCP3911 Dual channel analog front end (ADC)
9
9
+81
Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
+81
Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/nxp,imx93-adc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP iMX93 ADC
8
+
9
+
maintainers:
10
+
- Haibo Chen <haibo.chen@nxp.com>
11
+
12
+
description:
13
+
The ADC on iMX93 is a 8-channel 12-bit 1MS/s ADC with 4 channels
14
+
connected to pins. it support normal and inject mode, include
15
+
One-Shot and Scan (continuous) conversions. Programmable DMA
16
+
enables for each channel Also this ADC contain alternate analog
17
+
watchdog thresholds, select threshold through input ports. And
18
+
also has Self-test logic and Software-initiated calibration.
19
+
20
+
properties:
21
+
compatible:
22
+
const: nxp,imx93-adc
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
interrupts:
28
+
items:
29
+
- description: WDGnL, watchdog threshold interrupt requests.
30
+
- description: WDGnH, watchdog threshold interrupt requests.
31
+
- description: normal conversion, include EOC (End of Conversion),
32
+
ECH (End of Chain), JEOC (End of Injected Conversion) and
33
+
JECH (End of injected Chain).
34
+
- description: Self-testing Interrupts.
35
+
36
+
clocks:
37
+
maxItems: 1
38
+
39
+
clock-names:
40
+
const: ipg
41
+
42
+
vref-supply:
43
+
description:
44
+
The reference voltage which used to establish channel scaling.
45
+
46
+
"#io-channel-cells":
47
+
const: 1
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- interrupts
53
+
- clocks
54
+
- clock-names
55
+
- vref-supply
56
+
- "#io-channel-cells"
57
+
58
+
additionalProperties: false
59
+
60
+
examples:
61
+
- |
62
+
#include <dt-bindings/interrupt-controller/irq.h>
63
+
#include <dt-bindings/clock/imx93-clock.h>
64
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
65
+
soc {
66
+
#address-cells = <1>;
67
+
#size-cells = <1>;
68
+
adc@44530000 {
69
+
compatible = "nxp,imx93-adc";
70
+
reg = <0x44530000 0x10000>;
71
+
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
72
+
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
73
+
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
74
+
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
75
+
clocks = <&clk IMX93_CLK_ADC1_GATE>;
76
+
clock-names = "ipg";
77
+
vref-supply = <®_vref_1v8>;
78
+
#io-channel-cells = <1>;
79
+
};
80
+
};
81
+
...
+1
-1
Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml
+2
-1
Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml
+2
-1
Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml
···
20
20
compatible:
21
21
items:
22
22
- enum:
23
+
- qcom,pm8226-iadc
23
24
- qcom,pm8941-iadc
24
25
- const: qcom,spmi-iadc
25
26
···
50
49
examples:
51
50
- |
52
51
#include <dt-bindings/interrupt-controller/irq.h>
53
-
spmi_bus {
52
+
spmi {
54
53
#address-cells = <1>;
55
54
#size-cells = <0>;
56
55
pmic_iadc: adc@3600 {
+7
-7
Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
+7
-7
Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
···
40
40
examples:
41
41
- |
42
42
pmic {
43
-
#address-cells = <1>;
44
-
#size-cells = <0>;
43
+
#address-cells = <1>;
44
+
#size-cells = <0>;
45
45
46
-
pmic_rradc: adc@4500 {
47
-
compatible = "qcom,pmi8998-rradc";
48
-
reg = <0x4500>;
49
-
#io-channel-cells = <1>;
50
-
};
46
+
pmic_rradc: adc@4500 {
47
+
compatible = "qcom,pmi8998-rradc";
48
+
reg = <0x4500>;
49
+
#io-channel-cells = <1>;
50
+
};
51
51
};
+1
-1
Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+3
-3
Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
+3
-3
Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
···
52
52
vdd-supply: true
53
53
54
54
samsung,syscon-phandle:
55
-
$ref: '/schemas/types.yaml#/definitions/phandle'
55
+
$ref: /schemas/types.yaml#/definitions/phandle
56
56
description:
57
57
Phandle to the PMU system controller node (to access the ADC_PHY
58
58
register on Exynos3250/4x12/5250/5420/5800).
···
142
142
pullup-ohm = <47000>;
143
143
pulldown-ohm = <0>;
144
144
io-channels = <&adc 4>;
145
-
};
145
+
};
146
146
};
147
147
148
148
- |
···
150
150
151
151
adc@126c0000 {
152
152
compatible = "samsung,exynos3250-adc";
153
-
reg = <0x126C0000 0x100>;
153
+
reg = <0x126c0000 0x100>;
154
154
interrupts = <0 137 0>;
155
155
#io-channel-cells = <1>;
156
156
+4
-4
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+4
-4
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: STMicroelectronics STM32 ADC
8
8
···
80
80
description:
81
81
Phandle to system configuration controller. It can be used to control the
82
82
analog circuitry on stm32mp1.
83
-
$ref: "/schemas/types.yaml#/definitions/phandle-array"
83
+
$ref: /schemas/types.yaml#/definitions/phandle-array
84
84
85
85
interrupt-controller: true
86
86
···
341
341
patternProperties:
342
342
"^channel@([0-9]|1[0-9])$":
343
343
type: object
344
-
$ref: "adc.yaml"
344
+
$ref: adc.yaml
345
345
description: Represents the external channels which are connected to the ADC.
346
346
347
347
properties:
+3
-5
Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml
+3
-5
Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml
+55
Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml
+55
Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/ti,adc081c.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI Single-channel I2C ADCs
8
+
9
+
maintainers:
10
+
- Jonathan Cameron <jic23@kernel.org>
11
+
- Lars-Peter Clausen <lars@metafoo.de>
12
+
13
+
description: |
14
+
Single-channel ADC supporting 8, 10, or 12-bit samples and high/low alerts.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- ti,adc081c
20
+
- ti,adc101c
21
+
- ti,adc121c
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
vref-supply:
30
+
description:
31
+
Regulator for the combined power supply and voltage reference
32
+
33
+
"#io-channel-cells":
34
+
const: 1
35
+
36
+
required:
37
+
- compatible
38
+
- reg
39
+
- vref-supply
40
+
41
+
additionalProperties: false
42
+
43
+
examples:
44
+
- |
45
+
i2c {
46
+
#address-cells = <1>;
47
+
#size-cells = <0>;
48
+
49
+
adc@52 {
50
+
compatible = "ti,adc081c";
51
+
reg = <0x52>;
52
+
vref-supply = <®_2p5v>;
53
+
};
54
+
};
55
+
...
+4
-4
Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml
+4
-4
Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml
···
104
104
#address-cells = <1>;
105
105
#size-cells = <0>;
106
106
channel@0 {
107
-
reg = <0>;
107
+
reg = <0>;
108
108
};
109
109
channel@4 {
110
-
reg = <4>;
111
-
ti,gain = <3>;
112
-
ti,datarate = <5>;
110
+
reg = <4>;
111
+
ti,gain = <3>;
112
+
ti,datarate = <5>;
113
113
};
114
114
};
115
115
};
+1
-1
Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml
+1
-1
Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml
+110
Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml
+110
Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/ti,ads7924.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI ADS7924 4 channels 12 bits I2C analog to digital converter
8
+
9
+
maintainers:
10
+
- Hugo Villeneuve <hvilleneuve@dimonoff.com>
11
+
12
+
description: |
13
+
Texas Instruments ADS7924 4 channels 12 bits I2C analog to digital converter
14
+
15
+
Specifications:
16
+
https://www.ti.com/lit/gpn/ads7924
17
+
18
+
properties:
19
+
compatible:
20
+
const: ti,ads7924
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
vref-supply:
26
+
description:
27
+
The regulator supply for the ADC reference voltage (AVDD)
28
+
29
+
reset-gpios:
30
+
maxItems: 1
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
"#address-cells":
36
+
const: 1
37
+
38
+
"#size-cells":
39
+
const: 0
40
+
41
+
"#io-channel-cells":
42
+
const: 1
43
+
44
+
patternProperties:
45
+
"^channel@[0-3]+$":
46
+
$ref: adc.yaml
47
+
48
+
description: |
49
+
Represents the external channels which are connected to the ADC.
50
+
51
+
properties:
52
+
reg:
53
+
description: |
54
+
The channel number. It can have up to 4 channels numbered from 0 to 3.
55
+
items:
56
+
- minimum: 0
57
+
maximum: 3
58
+
59
+
label: true
60
+
61
+
required:
62
+
- reg
63
+
64
+
additionalProperties: false
65
+
66
+
additionalProperties: false
67
+
68
+
required:
69
+
- compatible
70
+
- reg
71
+
- vref-supply
72
+
- "#address-cells"
73
+
- "#size-cells"
74
+
75
+
examples:
76
+
- |
77
+
#include <dt-bindings/interrupt-controller/irq.h>
78
+
#include <dt-bindings/gpio/gpio.h>
79
+
i2c {
80
+
#address-cells = <1>;
81
+
#size-cells = <0>;
82
+
83
+
adc@48 {
84
+
compatible = "ti,ads7924";
85
+
reg = <0x48>;
86
+
vref-supply = <&ads7924_reg>;
87
+
reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
88
+
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
89
+
interrupt-parent = <&gpio>;
90
+
#address-cells = <1>;
91
+
#size-cells = <0>;
92
+
channel@0 {
93
+
reg = <0>;
94
+
label = "CH0";
95
+
};
96
+
channel@1 {
97
+
reg = <1>;
98
+
label = "CH1";
99
+
};
100
+
channel@2 {
101
+
reg = <2>;
102
+
label = "CH2";
103
+
};
104
+
channel@3 {
105
+
reg = <3>;
106
+
label = "CH3";
107
+
};
108
+
};
109
+
};
110
+
...
+70
Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml
+70
Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/ti,lmp92064.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments LMP92064 Precision Current and Voltage Sensor.
8
+
9
+
maintainers:
10
+
- Leonard Göhrs <l.goehrs@pengutronix.de>
11
+
12
+
description: |
13
+
The LMP92064 is a two channel ADC intended for combined voltage and current
14
+
measurements.
15
+
16
+
The device contains two ADCs to allow simultaneous sampling of voltage and
17
+
current and thus of instantaneous power consumption.
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- ti,lmp92064
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
vdd-supply:
28
+
description: Regulator that provides power to the main part of the chip
29
+
30
+
vdig-supply:
31
+
description: |
32
+
Regulator that provides power to the digital I/O part of the chip
33
+
34
+
shunt-resistor-micro-ohms:
35
+
description: |
36
+
Value of the shunt resistor (in µΩ) connected between INCP and INCN,
37
+
across which current is measured. Used to provide correct scaling of the
38
+
raw ADC measurement.
39
+
40
+
reset-gpios:
41
+
maxItems: 1
42
+
43
+
required:
44
+
- compatible
45
+
- reg
46
+
- shunt-resistor-micro-ohms
47
+
48
+
allOf:
49
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
50
+
51
+
unevaluatedProperties: false
52
+
53
+
examples:
54
+
- |
55
+
#include <dt-bindings/gpio/gpio.h>
56
+
spi {
57
+
#address-cells = <1>;
58
+
#size-cells = <0>;
59
+
60
+
adc@0 {
61
+
compatible = "ti,lmp92064";
62
+
reg = <0>;
63
+
vdd-supply = <&vdd>;
64
+
vdig-supply = <&vdd>;
65
+
spi-max-frequency = <20000000>;
66
+
shunt-resistor-micro-ohms = <15000>;
67
+
reset-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
68
+
};
69
+
};
70
+
...
+17
-17
Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml
+17
-17
Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml
···
41
41
42
42
patternProperties:
43
43
"^channel@[0-7]$":
44
-
$ref: "adc.yaml"
44
+
$ref: adc.yaml
45
45
type: object
46
46
47
47
properties:
···
83
83
#size-cells = <0>;
84
84
85
85
channel@0 {
86
-
reg = <0>;
86
+
reg = <0>;
87
87
};
88
88
channel@1 {
89
-
reg = <1>;
90
-
settling-time-us = <700>;
91
-
oversampling-ratio = <5>;
89
+
reg = <1>;
90
+
settling-time-us = <700>;
91
+
oversampling-ratio = <5>;
92
92
};
93
93
channel@2 {
94
-
reg = <2>;
94
+
reg = <2>;
95
95
};
96
96
channel@3 {
97
-
reg = <3>;
98
-
settling-time-us = <700>;
99
-
oversampling-ratio = <5>;
97
+
reg = <3>;
98
+
settling-time-us = <700>;
99
+
oversampling-ratio = <5>;
100
100
};
101
101
channel@4 {
102
-
reg = <4>;
103
-
settling-time-us = <700>;
104
-
oversampling-ratio = <5>;
102
+
reg = <4>;
103
+
settling-time-us = <700>;
104
+
oversampling-ratio = <5>;
105
105
};
106
106
channel@5 {
107
-
reg = <5>;
108
-
settling-time-us = <700>;
109
-
oversampling-ratio = <5>;
107
+
reg = <5>;
108
+
settling-time-us = <700>;
109
+
oversampling-ratio = <5>;
110
110
};
111
111
channel@6 {
112
-
reg = <6>;
112
+
reg = <6>;
113
113
};
114
114
channel@7 {
115
-
reg = <7>;
115
+
reg = <7>;
116
116
};
117
117
};
118
118
};
+20
-20
Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
+20
-20
Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
···
192
192
examples:
193
193
- |
194
194
spi {
195
-
#address-cells = <1>;
196
-
#size-cells = <0>;
197
-
ad3552r@0 {
198
-
compatible = "adi,ad3552r";
199
-
reg = <0>;
200
-
spi-max-frequency = <20000000>;
201
-
#address-cells = <1>;
202
-
#size-cells = <0>;
203
-
channel@0 {
204
-
reg = <0>;
205
-
adi,output-range-microvolt = <0 10000000>;
206
-
};
207
-
channel@1 {
208
-
reg = <1>;
209
-
custom-output-range-config {
210
-
adi,gain-offset = <5>;
211
-
adi,gain-scaling-p-inv-log2 = <1>;
212
-
adi,gain-scaling-n-inv-log2 = <2>;
213
-
adi,rfb-ohms = <1>;
214
-
};
195
+
#address-cells = <1>;
196
+
#size-cells = <0>;
197
+
ad3552r@0 {
198
+
compatible = "adi,ad3552r";
199
+
reg = <0>;
200
+
spi-max-frequency = <20000000>;
201
+
#address-cells = <1>;
202
+
#size-cells = <0>;
203
+
channel@0 {
204
+
reg = <0>;
205
+
adi,output-range-microvolt = <0 10000000>;
206
+
};
207
+
channel@1 {
208
+
reg = <1>;
209
+
custom-output-range-config {
210
+
adi,gain-offset = <5>;
211
+
adi,gain-scaling-p-inv-log2 = <1>;
212
+
adi,gain-scaling-n-inv-log2 = <2>;
213
+
adi,rfb-ohms = <1>;
214
+
};
215
215
};
216
216
};
217
217
};
+1
Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml
+1
Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml
+1
Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml
+1
Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml
+11
-11
Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml
+11
-11
Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml
···
51
51
examples:
52
52
- |
53
53
spi {
54
-
#address-cells = <1>;
55
-
#size-cells = <0>;
54
+
#address-cells = <1>;
55
+
#size-cells = <0>;
56
56
57
-
ad5766@0 {
58
-
compatible = "adi,ad5766";
59
-
output-range-microvolts = <(-5000000) 5000000>;
60
-
reg = <0>;
61
-
spi-cpol;
62
-
spi-max-frequency = <1000000>;
63
-
reset-gpios = <&gpio 22 0>;
64
-
};
65
-
};
57
+
ad5766@0 {
58
+
compatible = "adi,ad5766";
59
+
output-range-microvolts = <(-5000000) 5000000>;
60
+
reg = <0>;
61
+
spi-cpol;
62
+
spi-max-frequency = <1000000>;
63
+
reset-gpios = <&gpio 22 0>;
64
+
};
65
+
};
+37
-37
Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml
+37
-37
Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml
···
147
147
148
148
examples:
149
149
- |
150
-
spi {
151
-
#address-cells = <1>;
152
-
#size-cells = <0>;
150
+
spi {
151
+
#address-cells = <1>;
152
+
#size-cells = <0>;
153
153
154
-
ad5770r@0 {
155
-
compatible = "adi,ad5770r";
156
-
reg = <0>;
157
-
spi-max-frequency = <1000000>;
158
-
vref-supply = <&vref>;
159
-
adi,external-resistor;
160
-
reset-gpios = <&gpio 22 0>;
161
-
#address-cells = <1>;
162
-
#size-cells = <0>;
154
+
ad5770r@0 {
155
+
compatible = "adi,ad5770r";
156
+
reg = <0>;
157
+
spi-max-frequency = <1000000>;
158
+
vref-supply = <&vref>;
159
+
adi,external-resistor;
160
+
reset-gpios = <&gpio 22 0>;
161
+
#address-cells = <1>;
162
+
#size-cells = <0>;
163
163
164
-
channel@0 {
165
-
reg = <0>;
166
-
adi,range-microamp = <0 300000>;
167
-
};
164
+
channel@0 {
165
+
reg = <0>;
166
+
adi,range-microamp = <0 300000>;
167
+
};
168
168
169
-
channel@1 {
170
-
reg = <1>;
171
-
adi,range-microamp = <0 140000>;
172
-
};
169
+
channel@1 {
170
+
reg = <1>;
171
+
adi,range-microamp = <0 140000>;
172
+
};
173
173
174
-
channel@2 {
175
-
reg = <2>;
176
-
adi,range-microamp = <0 55000>;
177
-
};
174
+
channel@2 {
175
+
reg = <2>;
176
+
adi,range-microamp = <0 55000>;
177
+
};
178
178
179
-
channel@3 {
180
-
reg = <3>;
181
-
adi,range-microamp = <0 45000>;
182
-
};
179
+
channel@3 {
180
+
reg = <3>;
181
+
adi,range-microamp = <0 45000>;
182
+
};
183
183
184
-
channel@4 {
185
-
reg = <4>;
186
-
adi,range-microamp = <0 45000>;
187
-
};
184
+
channel@4 {
185
+
reg = <4>;
186
+
adi,range-microamp = <0 45000>;
187
+
};
188
188
189
-
channel@5 {
190
-
reg = <5>;
191
-
adi,range-microamp = <0 45000>;
192
-
};
193
-
};
189
+
channel@5 {
190
+
reg = <5>;
191
+
adi,range-microamp = <0 45000>;
192
+
};
194
193
};
194
+
};
195
195
...
+22
-22
Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml
+22
-22
Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml
···
116
116
- |
117
117
118
118
spi {
119
-
#address-cells = <1>;
120
-
#size-cells = <0>;
121
-
ltc2688: ltc2688@0 {
122
-
compatible = "adi,ltc2688";
123
-
reg = <0>;
119
+
#address-cells = <1>;
120
+
#size-cells = <0>;
121
+
ltc2688: ltc2688@0 {
122
+
compatible = "adi,ltc2688";
123
+
reg = <0>;
124
124
125
-
vcc-supply = <&vcc>;
126
-
iovcc-supply = <&vcc>;
127
-
vref-supply = <&vref>;
125
+
vcc-supply = <&vcc>;
126
+
iovcc-supply = <&vcc>;
127
+
vref-supply = <&vref>;
128
128
129
-
#address-cells = <1>;
130
-
#size-cells = <0>;
131
-
channel@0 {
132
-
reg = <0>;
133
-
adi,toggle-mode;
134
-
adi,overrange;
135
-
};
129
+
#address-cells = <1>;
130
+
#size-cells = <0>;
131
+
channel@0 {
132
+
reg = <0>;
133
+
adi,toggle-mode;
134
+
adi,overrange;
135
+
};
136
136
137
-
channel@1 {
138
-
reg = <1>;
139
-
adi,output-range-microvolt = <0 10000000>;
137
+
channel@1 {
138
+
reg = <1>;
139
+
adi,output-range-microvolt = <0 10000000>;
140
140
141
-
clocks = <&clock_tgp3>;
142
-
adi,toggle-dither-input = <2>;
143
-
};
144
-
};
141
+
clocks = <&clock_tgp3>;
142
+
adi,toggle-dither-input = <2>;
143
+
};
144
+
};
145
145
};
146
146
147
147
...
+2
-2
Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml
+2
-2
Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml
···
2
2
# Copyright 2019 Marcus Folkesson <marcus.folkesson@gmail.com>
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc1660.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/iio/dac/lltc,ltc1660.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Linear Technology Micropower octal 8-Bit and 10-Bit DACs
9
9
+10
-10
Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml
+10
-10
Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml
···
1
1
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Linear Technology LTC263x 12-/10-/8-Bit Rail-to-Rail DAC
8
8
···
64
64
};
65
65
66
66
spi {
67
-
#address-cells = <1>;
68
-
#size-cells = <0>;
67
+
#address-cells = <1>;
68
+
#size-cells = <0>;
69
69
70
-
dac@0 {
71
-
compatible = "lltc,ltc2632-l12";
72
-
reg = <0>; /* CS0 */
73
-
spi-max-frequency = <1000000>;
74
-
vref-supply = <&vref>;
75
-
};
70
+
dac@0 {
71
+
compatible = "lltc,ltc2632-l12";
72
+
reg = <0>; /* CS0 */
73
+
spi-max-frequency = <1000000>;
74
+
vref-supply = <&vref>;
75
+
};
76
76
};
77
77
...
+49
Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml
+49
Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/dac/maxim,max5522.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Maxim Integrated MAX5522 Dual 10-bit Voltage-Output SPI DACs
8
+
9
+
maintainers:
10
+
- Angelo Dureghello <angelo.dureghello@timesys.com>
11
+
- Jonathan Cameron <jic23@kernel.org>
12
+
13
+
description: |
14
+
Datasheet available at:
15
+
https://www.analog.com/en/products/max5522.html
16
+
17
+
properties:
18
+
compatible:
19
+
const: maxim,max5522
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
vdd-supply: true
25
+
vrefin-supply: true
26
+
27
+
required:
28
+
- compatible
29
+
- reg
30
+
- vrefin-supply
31
+
32
+
allOf:
33
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
34
+
35
+
unevaluatedProperties: false
36
+
37
+
examples:
38
+
- |
39
+
spi {
40
+
#address-cells = <1>;
41
+
#size-cells = <0>;
42
+
43
+
dac@0 {
44
+
compatible = "maxim,max5522";
45
+
reg = <0>;
46
+
vrefin-supply = <&vref>;
47
+
};
48
+
};
49
+
...
+2
-2
Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
+2
-2
Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: STMicroelectronics STM32 DAC
8
8
+1
-1
Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
+1
-1
Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
+6
-6
Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
+6
-6
Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
···
53
53
54
54
examples:
55
55
- |
56
-
spi0 {
56
+
spi {
57
57
#address-cells = <1>;
58
58
#size-cells = <0>;
59
59
60
60
frequency@0 {
61
-
compatible = "adi,adf4371";
62
-
reg = <0>;
63
-
spi-max-frequency = <1000000>;
64
-
clocks = <&adf4371_clkin>;
65
-
clock-names = "clkin";
61
+
compatible = "adi,adf4371";
62
+
reg = <0>;
63
+
spi-max-frequency = <1000000>;
64
+
clocks = <&adf4371_clkin>;
65
+
clock-names = "clkin";
66
66
};
67
67
};
68
68
...
+7
-7
Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml
+7
-7
Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml
···
50
50
#address-cells = <1>;
51
51
#size-cells = <0>;
52
52
gyro@0 {
53
-
compatible = "adi,adxrs290";
54
-
reg = <0>;
55
-
spi-max-frequency = <5000000>;
56
-
spi-cpol;
57
-
spi-cpha;
58
-
interrupt-parent = <&gpio>;
59
-
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
53
+
compatible = "adi,adxrs290";
54
+
reg = <0>;
55
+
spi-max-frequency = <5000000>;
56
+
spi-cpol;
57
+
spi-cpha;
58
+
interrupt-parent = <&gpio>;
59
+
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
60
60
};
61
61
};
62
62
...
+15
-15
Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml
+15
-15
Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml
···
65
65
- |
66
66
#include <dt-bindings/interrupt-controller/irq.h>
67
67
68
-
i2c0 {
68
+
i2c {
69
69
#address-cells = <1>;
70
70
#size-cells = <0>;
71
71
72
72
gyroscope@20 {
73
-
compatible = "nxp,fxas21002c";
74
-
reg = <0x20>;
73
+
compatible = "nxp,fxas21002c";
74
+
reg = <0x20>;
75
75
76
-
vdd-supply = <®_peri_3p15v>;
77
-
vddio-supply = <®_peri_3p15v>;
76
+
vdd-supply = <®_peri_3p15v>;
77
+
vddio-supply = <®_peri_3p15v>;
78
78
79
-
interrupt-parent = <&gpio1>;
80
-
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
81
-
interrupt-names = "INT1";
79
+
interrupt-parent = <&gpio1>;
80
+
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
81
+
interrupt-names = "INT1";
82
82
};
83
83
};
84
-
spi0 {
84
+
spi {
85
85
#address-cells = <1>;
86
86
#size-cells = <0>;
87
87
88
88
gyroscope@0 {
89
-
compatible = "nxp,fxas21002c";
90
-
reg = <0x0>;
89
+
compatible = "nxp,fxas21002c";
90
+
reg = <0x0>;
91
91
92
-
spi-max-frequency = <2000000>;
92
+
spi-max-frequency = <2000000>;
93
93
94
-
interrupt-parent = <&gpio2>;
95
-
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
96
-
interrupt-names = "INT2";
94
+
interrupt-parent = <&gpio2>;
95
+
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
96
+
interrupt-names = "INT2";
97
97
};
98
98
};
+1
-1
Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml
+1
-1
Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml
+1
-1
Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml
+1
-1
Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml
+1
-1
Documentation/devicetree/bindings/iio/humidity/dht11.yaml
+1
-1
Documentation/devicetree/bindings/iio/humidity/dht11.yaml
+7
-7
Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml
+7
-7
Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml
···
35
35
36
36
examples:
37
37
- |
38
-
i2c0 {
39
-
#address-cells = <1>;
40
-
#size-cells = <0>;
38
+
i2c {
39
+
#address-cells = <1>;
40
+
#size-cells = <0>;
41
41
42
-
humidity@40 {
43
-
compatible = "ti,hdc2010";
44
-
reg = <0x40>;
45
-
};
42
+
humidity@40 {
43
+
compatible = "ti,hdc2010";
44
+
reg = <0x40>;
45
+
};
46
46
};
+1
-1
Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
+1
-1
Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
+11
-11
Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml
+11
-11
Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml
···
114
114
- |
115
115
#include <dt-bindings/interrupt-controller/irq.h>
116
116
spi {
117
-
#address-cells = <1>;
118
-
#size-cells = <0>;
117
+
#address-cells = <1>;
118
+
#size-cells = <0>;
119
119
120
-
adis16475: adis16475-3@0 {
121
-
compatible = "adi,adis16475-3";
122
-
reg = <0>;
123
-
spi-cpha;
124
-
spi-cpol;
125
-
spi-max-frequency = <2000000>;
126
-
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
127
-
interrupt-parent = <&gpio>;
128
-
};
120
+
adis16475: adis16475-3@0 {
121
+
compatible = "adi,adis16475-3";
122
+
reg = <0>;
123
+
spi-cpha;
124
+
spi-cpol;
125
+
spi-max-frequency = <2000000>;
126
+
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
127
+
interrupt-parent = <&gpio>;
128
+
};
129
129
};
130
130
...
+16
-16
Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
+16
-16
Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
···
64
64
#size-cells = <0>;
65
65
66
66
bmi160@68 {
67
-
compatible = "bosch,bmi160";
68
-
reg = <0x68>;
69
-
vdd-supply = <&pm8916_l17>;
70
-
vddio-supply = <&pm8916_l6>;
71
-
interrupt-parent = <&gpio4>;
72
-
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
73
-
interrupt-names = "INT1";
74
-
mount-matrix = "0", "1", "0",
75
-
"-1", "0", "0",
76
-
"0", "0", "1";
67
+
compatible = "bosch,bmi160";
68
+
reg = <0x68>;
69
+
vdd-supply = <&pm8916_l17>;
70
+
vddio-supply = <&pm8916_l6>;
71
+
interrupt-parent = <&gpio4>;
72
+
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
73
+
interrupt-names = "INT1";
74
+
mount-matrix = "0", "1", "0",
75
+
"-1", "0", "0",
76
+
"0", "0", "1";
77
77
};
78
78
};
79
79
- |
···
84
84
#size-cells = <0>;
85
85
86
86
bmi160@0 {
87
-
compatible = "bosch,bmi160";
88
-
reg = <0>;
89
-
spi-max-frequency = <10000000>;
90
-
interrupt-parent = <&gpio2>;
91
-
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
92
-
interrupt-names = "INT2";
87
+
compatible = "bosch,bmi160";
88
+
reg = <0>;
89
+
spi-max-frequency = <10000000>;
90
+
interrupt-parent = <&gpio2>;
91
+
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
92
+
interrupt-names = "INT2";
93
93
};
94
94
};
+17
-17
Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
+17
-17
Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
···
65
65
- |
66
66
#include <dt-bindings/gpio/gpio.h>
67
67
#include <dt-bindings/interrupt-controller/irq.h>
68
-
i2c0 {
68
+
i2c {
69
69
#address-cells = <1>;
70
70
#size-cells = <0>;
71
71
72
72
icm42605@68 {
73
-
compatible = "invensense,icm42605";
74
-
reg = <0x68>;
75
-
interrupt-parent = <&gpio2>;
76
-
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
77
-
vdd-supply = <&vdd>;
78
-
vddio-supply = <&vddio>;
73
+
compatible = "invensense,icm42605";
74
+
reg = <0x68>;
75
+
interrupt-parent = <&gpio2>;
76
+
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
77
+
vdd-supply = <&vdd>;
78
+
vddio-supply = <&vddio>;
79
79
};
80
80
};
81
81
- |
82
82
#include <dt-bindings/gpio/gpio.h>
83
83
#include <dt-bindings/interrupt-controller/irq.h>
84
-
spi0 {
84
+
spi {
85
85
#address-cells = <1>;
86
86
#size-cells = <0>;
87
87
88
88
icm42602@0 {
89
-
compatible = "invensense,icm42602";
90
-
reg = <0>;
91
-
spi-max-frequency = <24000000>;
92
-
spi-cpha;
93
-
spi-cpol;
94
-
interrupt-parent = <&gpio1>;
95
-
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
96
-
vdd-supply = <&vdd>;
97
-
vddio-supply = <&vddio>;
89
+
compatible = "invensense,icm42602";
90
+
reg = <0>;
91
+
spi-max-frequency = <24000000>;
92
+
spi-cpha;
93
+
spi-cpol;
94
+
interrupt-parent = <&gpio1>;
95
+
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
96
+
vdd-supply = <&vdd>;
97
+
vddio-supply = <&vddio>;
98
98
};
99
99
};
+13
-13
Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml
+13
-13
Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml
···
49
49
- |
50
50
#include <dt-bindings/gpio/gpio.h>
51
51
#include <dt-bindings/interrupt-controller/irq.h>
52
-
i2c0 {
52
+
i2c {
53
53
#address-cells = <1>;
54
54
#size-cells = <0>;
55
55
56
56
fxos8700@1e {
57
-
compatible = "nxp,fxos8700";
58
-
reg = <0x1e>;
57
+
compatible = "nxp,fxos8700";
58
+
reg = <0x1e>;
59
59
60
-
interrupt-parent = <&gpio2>;
61
-
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
62
-
interrupt-names = "INT1";
60
+
interrupt-parent = <&gpio2>;
61
+
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
62
+
interrupt-names = "INT1";
63
63
};
64
64
};
65
65
- |
66
66
#include <dt-bindings/gpio/gpio.h>
67
67
#include <dt-bindings/interrupt-controller/irq.h>
68
-
spi0 {
68
+
spi {
69
69
#address-cells = <1>;
70
70
#size-cells = <0>;
71
71
72
72
fxos8700@0 {
73
-
compatible = "nxp,fxos8700";
74
-
reg = <0>;
73
+
compatible = "nxp,fxos8700";
74
+
reg = <0>;
75
75
76
-
spi-max-frequency = <1000000>;
77
-
interrupt-parent = <&gpio1>;
78
-
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
79
-
interrupt-names = "INT2";
76
+
spi-max-frequency = <1000000>;
77
+
interrupt-parent = <&gpio1>;
78
+
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
79
+
interrupt-names = "INT2";
80
80
};
81
81
};
+1
-1
Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml
+1
-1
Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml
···
63
63
description: if defined provides VDD IO power to the sensor.
64
64
65
65
st,drdy-int-pin:
66
-
$ref: '/schemas/types.yaml#/definitions/uint32'
66
+
$ref: /schemas/types.yaml#/definitions/uint32
67
67
description: |
68
68
The pin on the package that will be used to signal data ready
69
69
enum:
+75
Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml
+75
Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/magnetometer/ti,tmag5273.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor
8
+
9
+
maintainers:
10
+
- Gerald Loacker <gerald.loacker@wolfvision.net>
11
+
12
+
description:
13
+
The TI TMAG5273 is a low-power linear 3D Hall-effect sensor. This device
14
+
integrates three independent Hall-effect sensors in the X, Y, and Z axes.
15
+
The device has an integrated temperature sensor available. The TMAG5273
16
+
can be configured through the I2C interface to enable any combination of
17
+
magnetic axes and temperature measurements. An integrated angle calculation
18
+
engine (CORDIC) provides full 360° angular position information for both
19
+
on-axis and off-axis angle measurement topologies. The angle calculation is
20
+
performed using two user-selected magnetic axes.
21
+
22
+
properties:
23
+
compatible:
24
+
const: ti,tmag5273
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
"#io-channel-cells":
30
+
const: 1
31
+
32
+
ti,angle-measurement:
33
+
$ref: /schemas/types.yaml#/definitions/string
34
+
description:
35
+
Enables angle measurement in the selected plane.
36
+
If not specified, "x-y" will be anables as default.
37
+
enum:
38
+
- off
39
+
- x-y
40
+
- y-z
41
+
- x-z
42
+
43
+
vcc-supply:
44
+
description:
45
+
A regulator providing 1.7 V to 3.6 V supply voltage on the VCC pin,
46
+
typically 3.3 V.
47
+
48
+
interrupts:
49
+
description:
50
+
The low active interrupt can be configured to be fixed width or latched.
51
+
Interrupt events can be configured to be generated from magnetic
52
+
thresholds or when a conversion is completed.
53
+
maxItems: 1
54
+
55
+
required:
56
+
- compatible
57
+
- reg
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
i2c {
64
+
#address-cells = <1>;
65
+
#size-cells = <0>;
66
+
67
+
magnetometer@35 {
68
+
compatible = "ti,tmag5273";
69
+
reg = <0x35>;
70
+
#io-channel-cells = <1>;
71
+
ti,angle-measurement = "x-z";
72
+
vcc-supply = <&vcc3v3>;
73
+
};
74
+
};
75
+
...
+9
-9
Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml
+9
-9
Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml
···
91
91
#size-cells = <0>;
92
92
93
93
magnetometer@2e {
94
-
compatible = "yamaha,yas530";
95
-
reg = <0x2e>;
96
-
vdd-supply = <&ldo1_reg>;
97
-
iovdd-supply = <&ldo2_reg>;
98
-
reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
99
-
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
94
+
compatible = "yamaha,yas530";
95
+
reg = <0x2e>;
96
+
vdd-supply = <&ldo1_reg>;
97
+
iovdd-supply = <&ldo2_reg>;
98
+
reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
99
+
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
100
100
};
101
101
};
102
102
···
105
105
#size-cells = <0>;
106
106
107
107
magnetometer@2e {
108
-
compatible = "yamaha,yas539";
109
-
reg = <0x2e>;
110
-
vdd-supply = <&ldo1_reg>;
108
+
compatible = "yamaha,yas539";
109
+
reg = <0x2e>;
110
+
vdd-supply = <&ldo1_reg>;
111
111
};
112
112
};
+1
-1
Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml
+1
-1
Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml
+1
-1
Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml
+1
-1
Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml
+12
-12
Documentation/devicetree/bindings/iio/pressure/bmp085.yaml
+12
-12
Documentation/devicetree/bindings/iio/pressure/bmp085.yaml
···
60
60
- |
61
61
#include <dt-bindings/gpio/gpio.h>
62
62
#include <dt-bindings/interrupt-controller/irq.h>
63
-
i2c0 {
64
-
#address-cells = <1>;
65
-
#size-cells = <0>;
66
-
pressure@77 {
67
-
compatible = "bosch,bmp085";
68
-
reg = <0x77>;
69
-
interrupt-parent = <&gpio0>;
70
-
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
71
-
reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
72
-
vddd-supply = <&foo>;
73
-
vdda-supply = <&bar>;
74
-
};
63
+
i2c {
64
+
#address-cells = <1>;
65
+
#size-cells = <0>;
66
+
pressure@77 {
67
+
compatible = "bosch,bmp085";
68
+
reg = <0x77>;
69
+
interrupt-parent = <&gpio0>;
70
+
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
71
+
reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
72
+
vddd-supply = <&foo>;
73
+
vdda-supply = <&bar>;
74
+
};
75
75
};
+1
-1
Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml
+1
-1
Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml
-1
Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml
-1
Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml
+1
-1
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
+1
-1
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
···
36
36
const: 1
37
37
38
38
semtech,resolution:
39
-
$ref: /schemas/types.yaml#/definitions/uint32-array
39
+
$ref: /schemas/types.yaml#/definitions/uint32
40
40
enum: [8, 16, 32, 64, 128, 256, 512, 1024]
41
41
description:
42
42
Capacitance measurement resolution. For both phases, "reference" and
+2
Documentation/devicetree/bindings/iio/st,st-sensors.yaml
+2
Documentation/devicetree/bindings/iio/st,st-sensors.yaml
···
39
39
- st,lis3lv02dl-accel
40
40
- st,lng2dm-accel
41
41
- st,lsm303agr-accel
42
+
- st,lsm303c-accel
42
43
- st,lsm303dl-accel
43
44
- st,lsm303dlh-accel
44
45
- st,lsm303dlhc-accel
···
67
66
- st,lis2mdl
68
67
- st,lis3mdl-magn
69
68
- st,lsm303agr-magn
69
+
- st,lsm303c-magn
70
70
- st,lsm303dlh-magn
71
71
- st,lsm303dlhc-magn
72
72
- st,lsm303dlm-magn
+59
-60
Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
+59
-60
Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
···
472
472
#size-cells = <0>;
473
473
474
474
temperature-sensor@0 {
475
-
compatible = "adi,ltc2983";
476
-
reg = <0>;
475
+
compatible = "adi,ltc2983";
476
+
reg = <0>;
477
477
478
-
#address-cells = <1>;
479
-
#size-cells = <0>;
478
+
#address-cells = <1>;
479
+
#size-cells = <0>;
480
480
481
-
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
482
-
interrupt-parent = <&gpio>;
481
+
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
482
+
interrupt-parent = <&gpio>;
483
483
484
-
thermocouple@18 {
485
-
reg = <18>;
486
-
adi,sensor-type = <8>; //Type B
487
-
adi,sensor-oc-current-microamp = <10>;
488
-
adi,cold-junction-handle = <&diode5>;
489
-
};
484
+
thermocouple@18 {
485
+
reg = <18>;
486
+
adi,sensor-type = <8>; //Type B
487
+
adi,sensor-oc-current-microamp = <10>;
488
+
adi,cold-junction-handle = <&diode5>;
489
+
};
490
490
491
-
diode5: diode@5 {
492
-
reg = <5>;
493
-
adi,sensor-type = <28>;
494
-
};
491
+
diode5: diode@5 {
492
+
reg = <5>;
493
+
adi,sensor-type = <28>;
494
+
};
495
495
496
-
rsense2: rsense@2 {
497
-
reg = <2>;
498
-
adi,sensor-type = <29>;
499
-
adi,rsense-val-milli-ohms = <1200000>; //1.2Kohms
500
-
};
496
+
rsense2: rsense@2 {
497
+
reg = <2>;
498
+
adi,sensor-type = <29>;
499
+
adi,rsense-val-milli-ohms = <1200000>; //1.2Kohms
500
+
};
501
501
502
-
rtd@14 {
503
-
reg = <14>;
504
-
adi,sensor-type = <15>; //PT1000
505
-
/*2-wire, internal gnd, no current rotation*/
506
-
adi,number-of-wires = <2>;
507
-
adi,rsense-share;
508
-
adi,excitation-current-microamp = <500>;
509
-
adi,rsense-handle = <&rsense2>;
510
-
};
502
+
rtd@14 {
503
+
reg = <14>;
504
+
adi,sensor-type = <15>; //PT1000
505
+
/*2-wire, internal gnd, no current rotation*/
506
+
adi,number-of-wires = <2>;
507
+
adi,rsense-share;
508
+
adi,excitation-current-microamp = <500>;
509
+
adi,rsense-handle = <&rsense2>;
510
+
};
511
511
512
-
adc@10 {
513
-
reg = <10>;
514
-
adi,sensor-type = <30>;
515
-
adi,single-ended;
516
-
};
512
+
adc@10 {
513
+
reg = <10>;
514
+
adi,sensor-type = <30>;
515
+
adi,single-ended;
516
+
};
517
517
518
-
thermistor@12 {
519
-
reg = <12>;
520
-
adi,sensor-type = <26>; //Steinhart
521
-
adi,rsense-handle = <&rsense2>;
522
-
adi,custom-steinhart = <0x00F371EC 0x12345678
523
-
0x2C0F8733 0x10018C66 0xA0FEACCD
524
-
0x90021D99>; //6 entries
525
-
};
518
+
thermistor@12 {
519
+
reg = <12>;
520
+
adi,sensor-type = <26>; //Steinhart
521
+
adi,rsense-handle = <&rsense2>;
522
+
adi,custom-steinhart = <0x00f371ec 0x12345678
523
+
0x2c0f8733 0x10018c66 0xa0feaccd
524
+
0x90021d99>; //6 entries
525
+
};
526
526
527
-
thermocouple@20 {
528
-
reg = <20>;
529
-
adi,sensor-type = <9>; //custom thermocouple
530
-
adi,single-ended;
531
-
adi,custom-thermocouple =
532
-
/bits/ 64 <(-50220000) 0>,
533
-
/bits/ 64 <(-30200000) 99100000>,
534
-
/bits/ 64 <(-5300000) 135400000>,
535
-
/bits/ 64 <0 273150000>,
536
-
/bits/ 64 <40200000 361200000>,
537
-
/bits/ 64 <55300000 522100000>,
538
-
/bits/ 64 <88300000 720300000>,
539
-
/bits/ 64 <132200000 811200000>,
540
-
/bits/ 64 <188700000 922500000>,
541
-
/bits/ 64 <460400000 1000000000>; //10 pairs
542
-
};
543
-
527
+
thermocouple@20 {
528
+
reg = <20>;
529
+
adi,sensor-type = <9>; //custom thermocouple
530
+
adi,single-ended;
531
+
adi,custom-thermocouple =
532
+
/bits/ 64 <(-50220000) 0>,
533
+
/bits/ 64 <(-30200000) 99100000>,
534
+
/bits/ 64 <(-5300000) 135400000>,
535
+
/bits/ 64 <0 273150000>,
536
+
/bits/ 64 <40200000 361200000>,
537
+
/bits/ 64 <55300000 522100000>,
538
+
/bits/ 64 <88300000 720300000>,
539
+
/bits/ 64 <132200000 811200000>,
540
+
/bits/ 64 <188700000 922500000>,
541
+
/bits/ 64 <460400000 1000000000>; //10 pairs
542
+
};
544
543
};
545
544
};
546
545
...
+6
-6
Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml
+6
-6
Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml
···
43
43
#address-cells = <1>;
44
44
#size-cells = <0>;
45
45
46
-
temp_sensor@0 {
47
-
compatible = "maxim,max31865";
48
-
reg = <0>;
49
-
spi-max-frequency = <400000>;
50
-
spi-cpha;
51
-
maxim,3-wire;
46
+
temperature-sensor@0 {
47
+
compatible = "maxim,max31865";
48
+
reg = <0>;
49
+
spi-max-frequency = <400000>;
50
+
spi-cpha;
51
+
maxim,3-wire;
52
52
};
53
53
};
54
54
...
+3
-3
Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml
+3
-3
Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: "http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml#"
5
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
4
+
$id: http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: "TI TMP117 - Digital temperature sensor with integrated NV memory"
7
+
title: TI TMP117 - Digital temperature sensor with integrated NV memory
8
8
9
9
description: |
10
10
TI TMP117 - Digital temperature sensor with integrated NV memory that supports
+2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
···
27
27
- qcom,sc7280-cpu-bwmon
28
28
- qcom,sc8280xp-cpu-bwmon
29
29
- qcom,sdm845-bwmon
30
+
- qcom,sm8550-cpu-bwmon
30
31
- const: qcom,msm8998-bwmon
31
32
- const: qcom,msm8998-bwmon # BWMON v4
32
33
- items:
33
34
- enum:
34
35
- qcom,sc8280xp-llcc-bwmon
36
+
- qcom,sm8550-llcc-bwmon
35
37
- const: qcom,sc7280-llcc-bwmon
36
38
- const: qcom,sc7280-llcc-bwmon # BWMON v5
37
39
- const: qcom,sdm845-llcc-bwmon # BWMON v5
+1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+42
-31
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
+42
-31
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
···
62
62
power-domains:
63
63
maxItems: 1
64
64
65
+
# Child node's properties
66
+
patternProperties:
67
+
'^interconnect-[a-z0-9]+$':
68
+
type: object
69
+
description:
70
+
snoc-mm is a child of snoc, sharing snoc's register address space.
71
+
72
+
properties:
73
+
compatible:
74
+
enum:
75
+
- qcom,msm8939-snoc-mm
76
+
77
+
'#interconnect-cells':
78
+
const: 1
79
+
80
+
clock-names:
81
+
items:
82
+
- const: bus
83
+
- const: bus_a
84
+
85
+
clocks:
86
+
items:
87
+
- description: Bus Clock
88
+
- description: Bus A Clock
89
+
90
+
required:
91
+
- compatible
92
+
- '#interconnect-cells'
93
+
- clock-names
94
+
- clocks
95
+
65
96
required:
66
97
- compatible
67
98
- reg
···
138
107
items:
139
108
- description: Bus Clock
140
109
- description: Bus A Clock
141
-
142
-
# Child node's properties
143
-
patternProperties:
144
-
'^interconnect-[a-z0-9]+$':
145
-
type: object
146
-
description:
147
-
snoc-mm is a child of snoc, sharing snoc's register address space.
148
-
149
-
properties:
150
-
compatible:
151
-
enum:
152
-
- qcom,msm8939-snoc-mm
153
-
154
-
'#interconnect-cells':
155
-
const: 1
156
-
157
-
clock-names:
158
-
items:
159
-
- const: bus
160
-
- const: bus_a
161
-
162
-
clocks:
163
-
items:
164
-
- description: Bus Clock
165
-
- description: Bus A Clock
166
-
167
-
required:
168
-
- compatible
169
-
- '#interconnect-cells'
170
-
- clock-names
171
-
- clocks
172
110
173
111
- if:
174
112
properties:
···
236
236
- description: Aggregate2 UFS AXI Clock.
237
237
- description: Aggregate2 USB3 AXI Clock.
238
238
- description: Config NoC USB2 AXI Clock.
239
+
240
+
- if:
241
+
not:
242
+
properties:
243
+
compatible:
244
+
contains:
245
+
enum:
246
+
- qcom,msm8939-snoc
247
+
then:
248
+
patternProperties:
249
+
'^interconnect-[a-z0-9]+$': false
239
250
240
251
examples:
241
252
- |
+8
-38
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+8
-38
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
···
39
39
- qcom,sc7180-npu-noc
40
40
- qcom,sc7180-qup-virt
41
41
- qcom,sc7180-system-noc
42
-
- qcom,sc7280-aggre1-noc
43
-
- qcom,sc7280-aggre2-noc
44
-
- qcom,sc7280-clk-virt
45
-
- qcom,sc7280-cnoc2
46
-
- qcom,sc7280-cnoc3
47
-
- qcom,sc7280-dc-noc
48
-
- qcom,sc7280-gem-noc
49
-
- qcom,sc7280-lpass-ag-noc
50
-
- qcom,sc7280-mc-virt
51
-
- qcom,sc7280-mmss-noc
52
-
- qcom,sc7280-nsp-noc
53
-
- qcom,sc7280-system-noc
54
42
- qcom,sc8180x-aggre1-noc
55
43
- qcom,sc8180x-aggre2-noc
56
44
- qcom,sc8180x-camnoc-virt
···
46
58
- qcom,sc8180x-config-noc
47
59
- qcom,sc8180x-dc-noc
48
60
- qcom,sc8180x-gem-noc
49
-
- qcom,sc8180x-ipa-virt
50
61
- qcom,sc8180x-mc-virt
51
62
- qcom,sc8180x-mmss-noc
52
63
- qcom,sc8180x-qup-virt
53
64
- qcom,sc8180x-system-noc
54
-
- qcom,sc8280xp-aggre1-noc
55
-
- qcom,sc8280xp-aggre2-noc
56
-
- qcom,sc8280xp-clk-virt
57
-
- qcom,sc8280xp-config-noc
58
-
- qcom,sc8280xp-dc-noc
59
-
- qcom,sc8280xp-gem-noc
60
-
- qcom,sc8280xp-lpass-ag-noc
61
-
- qcom,sc8280xp-mc-virt
62
-
- qcom,sc8280xp-mmss-noc
63
-
- qcom,sc8280xp-nspa-noc
64
-
- qcom,sc8280xp-nspb-noc
65
-
- qcom,sc8280xp-system-noc
65
+
- qcom,sdm670-aggre1-noc
66
+
- qcom,sdm670-aggre2-noc
67
+
- qcom,sdm670-config-noc
68
+
- qcom,sdm670-dc-noc
69
+
- qcom,sdm670-gladiator-noc
70
+
- qcom,sdm670-mem-noc
71
+
- qcom,sdm670-mmss-noc
72
+
- qcom,sdm670-system-noc
66
73
- qcom,sdm845-aggre1-noc
67
74
- qcom,sdm845-aggre2-noc
68
75
- qcom,sdm845-config-noc
···
79
96
- qcom,sm8150-config-noc
80
97
- qcom,sm8150-dc-noc
81
98
- qcom,sm8150-gem-noc
82
-
- qcom,sm8150-ipa-virt
83
99
- qcom,sm8150-mc-virt
84
100
- qcom,sm8150-mmss-noc
85
101
- qcom,sm8150-system-noc
···
88
106
- qcom,sm8250-config-noc
89
107
- qcom,sm8250-dc-noc
90
108
- qcom,sm8250-gem-noc
91
-
- qcom,sm8250-ipa-virt
92
109
- qcom,sm8250-mc-virt
93
110
- qcom,sm8250-mmss-noc
94
111
- qcom,sm8250-npu-noc
···
102
121
- qcom,sm8350-mmss-noc
103
122
- qcom,sm8350-compute-noc
104
123
- qcom,sm8350-system-noc
105
-
- qcom,sm8450-aggre1-noc
106
-
- qcom,sm8450-aggre2-noc
107
-
- qcom,sm8450-clk-virt
108
-
- qcom,sm8450-config-noc
109
-
- qcom,sm8450-gem-noc
110
-
- qcom,sm8450-lpass-ag-noc
111
-
- qcom,sm8450-mc-virt
112
-
- qcom,sm8450-mmss-noc
113
-
- qcom,sm8450-nsp-noc
114
-
- qcom,sm8450-pcie-anoc
115
-
- qcom,sm8450-system-noc
116
124
117
125
'#interconnect-cells': true
118
126
+50
Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
+50
Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sa8775p-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SA8775P
8
+
9
+
maintainers:
10
+
- Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
11
+
12
+
description: |
13
+
RPMh interconnect providers support system bandwidth requirements through
14
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
15
+
16
+
See also:: include/dt-bindings/interconnect/qcom,sa8775p.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sa8775p-aggre1-noc
22
+
- qcom,sa8775p-aggre2-noc
23
+
- qcom,sa8775p-clk-virt
24
+
- qcom,sa8775p-config-noc
25
+
- qcom,sa8775p-dc-noc
26
+
- qcom,sa8775p-gem-noc
27
+
- qcom,sa8775p-gpdsp-anoc
28
+
- qcom,sa8775p-lpass-ag-noc
29
+
- qcom,sa8775p-mc-virt
30
+
- qcom,sa8775p-mmss-noc
31
+
- qcom,sa8775p-nspa-noc
32
+
- qcom,sa8775p-nspb-noc
33
+
- qcom,sa8775p-pcie-anoc
34
+
- qcom,sa8775p-system-noc
35
+
36
+
required:
37
+
- compatible
38
+
39
+
allOf:
40
+
- $ref: qcom,rpmh-common.yaml#
41
+
42
+
unevaluatedProperties: false
43
+
44
+
examples:
45
+
- |
46
+
aggre1_noc: interconnect-aggre1-noc {
47
+
compatible = "qcom,sa8775p-aggre1-noc";
48
+
#interconnect-cells = <2>;
49
+
qcom,bcm-voters = <&apps_bcm_voter>;
50
+
};
+71
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
+71
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
16
+
17
+
See also:: include/dt-bindings/interconnect/qcom,sc7280.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sc7280-aggre1-noc
23
+
- qcom,sc7280-aggre2-noc
24
+
- qcom,sc7280-clk-virt
25
+
- qcom,sc7280-cnoc2
26
+
- qcom,sc7280-cnoc3
27
+
- qcom,sc7280-dc-noc
28
+
- qcom,sc7280-gem-noc
29
+
- qcom,sc7280-lpass-ag-noc
30
+
- qcom,sc7280-mc-virt
31
+
- qcom,sc7280-mmss-noc
32
+
- qcom,sc7280-nsp-noc
33
+
- qcom,sc7280-system-noc
34
+
35
+
reg:
36
+
maxItems: 1
37
+
38
+
required:
39
+
- compatible
40
+
41
+
allOf:
42
+
- $ref: qcom,rpmh-common.yaml#
43
+
- if:
44
+
properties:
45
+
compatible:
46
+
contains:
47
+
enum:
48
+
- qcom,sc7280-clk-virt
49
+
then:
50
+
properties:
51
+
reg: false
52
+
else:
53
+
required:
54
+
- reg
55
+
56
+
unevaluatedProperties: false
57
+
58
+
examples:
59
+
- |
60
+
interconnect {
61
+
compatible = "qcom,sc7280-clk-virt";
62
+
#interconnect-cells = <2>;
63
+
qcom,bcm-voters = <&apps_bcm_voter>;
64
+
};
65
+
66
+
interconnect@9100000 {
67
+
reg = <0x9100000 0xe2200>;
68
+
compatible = "qcom,sc7280-gem-noc";
69
+
#interconnect-cells = <2>;
70
+
qcom,bcm-voters = <&apps_bcm_voter>;
71
+
};
+49
Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml
+49
Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
16
+
17
+
See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sc8280xp-aggre1-noc
23
+
- qcom,sc8280xp-aggre2-noc
24
+
- qcom,sc8280xp-clk-virt
25
+
- qcom,sc8280xp-config-noc
26
+
- qcom,sc8280xp-dc-noc
27
+
- qcom,sc8280xp-gem-noc
28
+
- qcom,sc8280xp-lpass-ag-noc
29
+
- qcom,sc8280xp-mc-virt
30
+
- qcom,sc8280xp-mmss-noc
31
+
- qcom,sc8280xp-nspa-noc
32
+
- qcom,sc8280xp-nspb-noc
33
+
- qcom,sc8280xp-system-noc
34
+
35
+
required:
36
+
- compatible
37
+
38
+
allOf:
39
+
- $ref: qcom,rpmh-common.yaml#
40
+
41
+
unevaluatedProperties: false
42
+
43
+
examples:
44
+
- |
45
+
interconnect-0 {
46
+
compatible = "qcom,sc8280xp-aggre1-noc";
47
+
#interconnect-cells = <2>;
48
+
qcom,bcm-voters = <&apps_bcm_voter>;
49
+
};
+124
Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml
+124
Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
16
+
17
+
See also:: include/dt-bindings/interconnect/qcom,sm8450.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sm8450-aggre1-noc
23
+
- qcom,sm8450-aggre2-noc
24
+
- qcom,sm8450-clk-virt
25
+
- qcom,sm8450-config-noc
26
+
- qcom,sm8450-gem-noc
27
+
- qcom,sm8450-lpass-ag-noc
28
+
- qcom,sm8450-mc-virt
29
+
- qcom,sm8450-mmss-noc
30
+
- qcom,sm8450-nsp-noc
31
+
- qcom,sm8450-pcie-anoc
32
+
- qcom,sm8450-system-noc
33
+
34
+
reg:
35
+
maxItems: 1
36
+
37
+
clocks:
38
+
minItems: 1
39
+
maxItems: 4
40
+
41
+
required:
42
+
- compatible
43
+
44
+
allOf:
45
+
- $ref: qcom,rpmh-common.yaml#
46
+
- if:
47
+
properties:
48
+
compatible:
49
+
contains:
50
+
enum:
51
+
- qcom,sm8450-clk-virt
52
+
- qcom,sm8450-mc-virt
53
+
then:
54
+
properties:
55
+
reg: false
56
+
else:
57
+
required:
58
+
- reg
59
+
60
+
- if:
61
+
properties:
62
+
compatible:
63
+
contains:
64
+
enum:
65
+
- qcom,sm8450-aggre1-noc
66
+
then:
67
+
properties:
68
+
clocks:
69
+
items:
70
+
- description: aggre UFS PHY AXI clock
71
+
- description: aggre USB3 PRIM AXI clock
72
+
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
contains:
77
+
enum:
78
+
- qcom,sm8450-aggre2-noc
79
+
then:
80
+
properties:
81
+
clocks:
82
+
items:
83
+
- description: aggre-NOC PCIe 0 AXI clock
84
+
- description: aggre-NOC PCIe 1 AXI clock
85
+
- description: aggre UFS PHY AXI clock
86
+
- description: RPMH CC IPA clock
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
enum:
93
+
- qcom,sm8450-aggre1-noc
94
+
- qcom,sm8450-aggre2-noc
95
+
then:
96
+
required:
97
+
- clocks
98
+
else:
99
+
properties:
100
+
clocks: false
101
+
102
+
unevaluatedProperties: false
103
+
104
+
examples:
105
+
- |
106
+
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
107
+
#include <dt-bindings/clock/qcom,rpmh.h>
108
+
109
+
interconnect-0 {
110
+
compatible = "qcom,sm8450-clk-virt";
111
+
#interconnect-cells = <2>;
112
+
qcom,bcm-voters = <&apps_bcm_voter>;
113
+
};
114
+
115
+
interconnect@1700000 {
116
+
compatible = "qcom,sm8450-aggre2-noc";
117
+
reg = <0x01700000 0x31080>;
118
+
#interconnect-cells = <2>;
119
+
qcom,bcm-voters = <&apps_bcm_voter>;
120
+
clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
121
+
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
122
+
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
123
+
<&rpmhcc RPMH_IPA_CLK>;
124
+
};
+27
Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml
+27
Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml
···
196
196
maxItems: 2
197
197
198
198
operating-points-v2: true
199
+
opp-table:
200
+
type: object
199
201
200
202
samsung,data-clock-ratio:
201
203
$ref: /schemas/types.yaml#/definitions/uint32
···
229
227
operating-points-v2 = <&bus_dmc_opp_table>;
230
228
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
231
229
vdd-supply = <&buck1_reg>;
230
+
231
+
bus_dmc_opp_table: opp-table {
232
+
compatible = "operating-points-v2";
233
+
234
+
opp-50000000 {
235
+
opp-hz = /bits/ 64 <50000000>;
236
+
opp-microvolt = <800000>;
237
+
};
238
+
opp-100000000 {
239
+
opp-hz = /bits/ 64 <100000000>;
240
+
opp-microvolt = <800000>;
241
+
};
242
+
opp-134000000 {
243
+
opp-hz = /bits/ 64 <134000000>;
244
+
opp-microvolt = <800000>;
245
+
};
246
+
opp-200000000 {
247
+
opp-hz = /bits/ 64 <200000000>;
248
+
opp-microvolt = <825000>;
249
+
};
250
+
opp-400000000 {
251
+
opp-hz = /bits/ 64 <400000000>;
252
+
opp-microvolt = <875000>;
253
+
};
254
+
};
232
255
};
233
256
234
257
ppmu_dmc0: ppmu@106a0000 {
+47
Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
+47
Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Xilinx Triple Modular Redundancy(TMR) Inject IP
8
+
9
+
maintainers:
10
+
- Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
11
+
12
+
description: |
13
+
The Triple Modular Redundancy(TMR) Inject core provides functional fault
14
+
injection by changing selected MicroBlaze instructions, which provides the
15
+
possibility to verify that the TMR subsystem error detection and fault
16
+
recovery logic is working properly.
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- xlnx,tmr-inject-1.0
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
xlnx,magic:
27
+
minimum: 0
28
+
maximum: 255
29
+
description: |
30
+
Magic number, When configured it allows the controller to perform
31
+
recovery.
32
+
$ref: /schemas/types.yaml#/definitions/uint32
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- xlnx,magic
38
+
39
+
additionalProperties: false
40
+
41
+
examples:
42
+
- |
43
+
fault-inject@44a30000 {
44
+
compatible = "xlnx,tmr-inject-1.0";
45
+
reg = <0x44a10000 0x10000>;
46
+
xlnx,magic = <0x46>;
47
+
};
+47
Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
+47
Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Xilinx Triple Modular Redundancy(TMR) Manager IP
8
+
9
+
maintainers:
10
+
- Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
11
+
12
+
description: |
13
+
The Triple Modular Redundancy(TMR) Manager is responsible for handling the
14
+
TMR subsystem state, including fault detection and error recovery. The core
15
+
is triplicated in each of the sub-blocks in the TMR subsystem, and provides
16
+
majority voting of its internal state.
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- xlnx,tmr-manager-1.0
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
xlnx,magic1:
27
+
minimum: 0
28
+
maximum: 255
29
+
description:
30
+
Magic byte 1, When configured it allows the controller to perform
31
+
recovery.
32
+
$ref: /schemas/types.yaml#/definitions/uint32
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- xlnx,magic1
38
+
39
+
additionalProperties: false
40
+
41
+
examples:
42
+
- |
43
+
tmr-manager@44a10000 {
44
+
compatible = "xlnx,tmr-manager-1.0";
45
+
reg = <0x44a10000 0x10000>;
46
+
xlnx,magic1 = <0x46>;
47
+
};
+6
-1
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+6
-1
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
···
19
19
- qcom,apq8064-qfprom
20
20
- qcom,apq8084-qfprom
21
21
- qcom,ipq8064-qfprom
22
-
- qcom,msm8974-qfprom
22
+
- qcom,ipq8074-qfprom
23
23
- qcom,msm8916-qfprom
24
+
- qcom,msm8974-qfprom
25
+
- qcom,msm8976-qfprom
24
26
- qcom,msm8996-qfprom
25
27
- qcom,msm8998-qfprom
26
28
- qcom,qcs404-qfprom
27
29
- qcom,sc7180-qfprom
28
30
- qcom,sc7280-qfprom
29
31
- qcom,sdm630-qfprom
32
+
- qcom,sdm670-qfprom
30
33
- qcom,sdm845-qfprom
31
34
- qcom,sm6115-qfprom
35
+
- qcom,sm8150-qfprom
36
+
- qcom,sm8250-qfprom
32
37
- const: qcom,qfprom
33
38
34
39
reg:
+7
Documentation/kbuild/kbuild.rst
+7
Documentation/kbuild/kbuild.rst
···
278
278
279
279
$ make ALLSOURCE_ARCHS=all tags
280
280
281
+
IGNORE_DIRS
282
+
-----------
283
+
For tags/TAGS/cscope targets, you can choose which directories won't
284
+
be included in the databases, separated by blank space. E.g.::
285
+
286
+
$ make IGNORE_DIRS="drivers/gpu/drm/radeon tools" cscope
287
+
281
288
KBUILD_BUILD_TIMESTAMP
282
289
----------------------
283
290
Setting this to a date string overrides the timestamp used in the
+52
Documentation/trace/coresight/coresight-tpda.rst
+52
Documentation/trace/coresight/coresight-tpda.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
=================================================================
4
+
The trace performance monitoring and diagnostics aggregator(TPDA)
5
+
=================================================================
6
+
7
+
:Author: Jinlong Mao <quic_jinlmao@quicinc.com>
8
+
:Date: January 2023
9
+
10
+
Hardware Description
11
+
--------------------
12
+
13
+
TPDA - The trace performance monitoring and diagnostics aggregator or
14
+
TPDA in short serves as an arbitration and packetization engine for the
15
+
performance monitoring and diagnostics network specification.
16
+
The primary use case of the TPDA is to provide packetization, funneling
17
+
and timestamping of Monitor data.
18
+
19
+
20
+
Sysfs files and directories
21
+
---------------------------
22
+
Root: ``/sys/bus/coresight/devices/tpda<N>``
23
+
24
+
Config details
25
+
---------------------------
26
+
27
+
The tpdm and tpda nodes should be observed at the coresight path
28
+
"/sys/bus/coresight/devices".
29
+
e.g.
30
+
/sys/bus/coresight/devices # ls -l | grep tpd
31
+
tpda0 -> ../../../devices/platform/soc@0/6004000.tpda/tpda0
32
+
tpdm0 -> ../../../devices/platform/soc@0/6c08000.mm.tpdm/tpdm0
33
+
34
+
We can use the commands are similar to the below to validate TPDMs.
35
+
Enable coresight sink first. The port of tpda which is connected to
36
+
the tpdm will be enabled after commands below.
37
+
38
+
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
39
+
echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
40
+
echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
41
+
echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
42
+
43
+
The test data will be collected in the coresight sink which is enabled.
44
+
If rwp register of the sink is keeping updating when do
45
+
integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data
46
+
generated from TPDM to sink.
47
+
48
+
There must be a tpda between tpdm and the sink. When there are some
49
+
other trace event hw components in the same HW block with tpdm, tpdm
50
+
and these hw components will connect to the coresight funnel. When
51
+
there is only tpdm trace hw in the HW block, tpdm will connect to
52
+
tpda directly.
+45
Documentation/trace/coresight/coresight-tpdm.rst
+45
Documentation/trace/coresight/coresight-tpdm.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
==========================================================
4
+
Trace performance monitoring and diagnostics monitor(TPDM)
5
+
==========================================================
6
+
7
+
:Author: Jinlong Mao <quic_jinlmao@quicinc.com>
8
+
:Date: January 2023
9
+
10
+
Hardware Description
11
+
--------------------
12
+
TPDM - The trace performance monitoring and diagnostics monitor or TPDM in
13
+
short serves as data collection component for various dataset types.
14
+
The primary use case of the TPDM is to collect data from different data
15
+
sources and send it to a TPDA for packetization, timestamping and funneling.
16
+
17
+
Sysfs files and directories
18
+
---------------------------
19
+
Root: ``/sys/bus/coresight/devices/tpdm<N>``
20
+
21
+
----
22
+
23
+
:File: ``enable_source`` (RW)
24
+
:Notes:
25
+
- > 0 : enable the datasets of TPDM.
26
+
27
+
- = 0 : disable the datasets of TPDM.
28
+
29
+
:Syntax:
30
+
``echo 1 > enable_source``
31
+
32
+
----
33
+
34
+
:File: ``integration_test`` (wo)
35
+
:Notes:
36
+
Integration test will generate test data for tpdm.
37
+
38
+
:Syntax:
39
+
``echo value > integration_test``
40
+
41
+
value - 1 or 2.
42
+
43
+
----
44
+
45
+
.. This text is intentionally added to make Sphinx happy.
+83
Documentation/trace/coresight/ultrasoc-smb.rst
+83
Documentation/trace/coresight/ultrasoc-smb.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
======================================
4
+
UltraSoc - HW Assisted Tracing on SoC
5
+
======================================
6
+
:Author: Qi Liu <liuqi115@huawei.com>
7
+
:Date: January 2023
8
+
9
+
Introduction
10
+
------------
11
+
12
+
UltraSoc SMB is a per SCCL (Super CPU Cluster) hardware. It provides a
13
+
way to buffer and store CPU trace messages in a region of shared system
14
+
memory. The device acts as a coresight sink device and the
15
+
corresponding trace generators (ETM) are attached as source devices.
16
+
17
+
Sysfs files and directories
18
+
---------------------------
19
+
20
+
The SMB devices appear on the existing coresight bus alongside other
21
+
devices::
22
+
23
+
$# ls /sys/bus/coresight/devices/
24
+
ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3
25
+
26
+
The ``ultra_smb<N>`` names SMB device associated with SCCL.::
27
+
28
+
$# ls /sys/bus/coresight/devices/ultra_smb0
29
+
enable_sink mgmt
30
+
$# ls /sys/bus/coresight/devices/ultra_smb0/mgmt
31
+
buf_size buf_status read_pos write_pos
32
+
33
+
Key file items are:
34
+
35
+
* ``read_pos``: Shows the value on the read pointer register.
36
+
* ``write_pos``: Shows the value on the write pointer register.
37
+
* ``buf_status``: Shows the value on the status register.
38
+
BIT(0) is zero value which means the buffer is empty.
39
+
* ``buf_size``: Shows the buffer size of each device.
40
+
41
+
Firmware Bindings
42
+
-----------------
43
+
44
+
The device is only supported with ACPI. Its binding describes device
45
+
identifier, resource information and graph structure.
46
+
47
+
The device is identified as ACPI HID "HISI03A1". Device resources are allocated
48
+
using the _CRS method. Each device must present two base address; the first one
49
+
is the configuration base address of the device, the second one is the 32-bit
50
+
base address of shared system memory.
51
+
52
+
Example::
53
+
54
+
Device(USMB) { \
55
+
Name(_HID, "HISI03A1") \
56
+
Name(_CRS, ResourceTemplate() { \
57
+
QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, NonCacheable, \
58
+
ReadWrite, 0x0, 0x95100000, 0x951FFFFF, 0x0, 0x100000) \
59
+
QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, Cacheable, \
60
+
ReadWrite, 0x0, 0x50000000, 0x53FFFFFF, 0x0, 0x4000000) \
61
+
}) \
62
+
Name(_DSD, Package() { \
63
+
ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \
64
+
/* Use CoreSight Graph ACPI bindings to describe connections topology */
65
+
Package() { \
66
+
0, \
67
+
1, \
68
+
Package() { \
69
+
1, \
70
+
ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \
71
+
8, \
72
+
Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \
73
+
Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \
74
+
Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \
75
+
Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \
76
+
Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \
77
+
Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \
78
+
Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \
79
+
Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \
80
+
} \
81
+
} \
82
+
}) \
83
+
}
+46
-2
MAINTAINERS
+46
-2
MAINTAINERS
···
2071
2071
M: Alexander Sverdlin <alexander.sverdlin@gmail.com>
2072
2072
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2073
2073
S: Maintained
2074
+
F: Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml
2074
2075
F: arch/arm/boot/compressed/misc-ep93xx.h
2075
2076
F: arch/arm/mach-ep93xx/
2077
+
F: drivers/iio/adc/ep93xx_adc.c
2076
2078
2077
2079
ARM/CLKDEV SUPPORT
2078
2080
M: Russell King <linux@armlinux.org.uk>
···
2101
2099
T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
2102
2100
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
2103
2101
F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml
2102
+
F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml
2104
2103
F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
2105
2104
F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
2106
2105
F: Documentation/trace/coresight/*
···
9257
9254
9258
9255
HISILICON PTT DRIVER
9259
9256
M: Yicong Yang <yangyicong@hisilicon.com>
9257
+
M: Jonathan Cameron <jonathan.cameron@huawei.com>
9260
9258
L: linux-kernel@vger.kernel.org
9261
9259
S: Maintained
9262
9260
F: Documentation/ABI/testing/sysfs-devices-hisi_ptt
9263
9261
F: Documentation/trace/hisi-ptt.rst
9264
9262
F: drivers/hwtracing/ptt/
9263
+
F: tools/perf/arch/arm64/util/hisi-ptt.c
9264
+
F: tools/perf/util/hisi-ptt*
9265
+
F: tools/perf/util/hisi-ptt-decoder/*
9265
9266
9266
9267
HISILICON QM DRIVER
9267
9268
M: Weili Qian <qianweili@huawei.com>
···
10461
10454
F: include/linux/mei_aux.h
10462
10455
F: include/linux/mei_cl_bus.h
10463
10456
F: include/uapi/linux/mei.h
10457
+
F: include/uapi/linux/uuid.h
10464
10458
F: samples/mei/*
10465
10459
10466
10460
INTEL MAX 10 BMC MFD DRIVER
···
13536
13528
T: git git://git.monstr.eu/linux-2.6-microblaze.git
13537
13529
F: arch/microblaze/
13538
13530
13531
+
MICROBLAZE TMR MANAGER
13532
+
M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
13533
+
S: Supported
13534
+
F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager
13535
+
F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml
13536
+
F: drivers/misc/xilinx_tmr_manager.c
13537
+
13538
+
MICROBLAZE TMR INJECT
13539
+
M: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
13540
+
S: Supported
13541
+
F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml
13542
+
F: drivers/misc/xilinx_tmr_inject.c
13543
+
13539
13544
MICROCHIP AT91 DMA DRIVERS
13540
13545
M: Ludovic Desroches <ludovic.desroches@microchip.com>
13541
13546
M: Tudor Ambarus <tudor.ambarus@linaro.org>
···
14974
14953
F: Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml
14975
14954
F: drivers/iio/adc/imx8qxp-adc.c
14976
14955
14977
-
NXP i.MX 7D/6SX/6UL AND VF610 ADC DRIVER
14956
+
NXP i.MX 7D/6SX/6UL/93 AND VF610 ADC DRIVER
14978
14957
M: Haibo Chen <haibo.chen@nxp.com>
14979
14958
L: linux-iio@vger.kernel.org
14980
14959
L: linux-imx@nxp.com
14981
14960
S: Maintained
14982
14961
F: Documentation/devicetree/bindings/iio/adc/fsl,imx7d-adc.yaml
14983
14962
F: Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml
14963
+
F: Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
14984
14964
F: drivers/iio/adc/imx7d_adc.c
14965
+
F: drivers/iio/adc/imx93_adc.c
14985
14966
F: drivers/iio/adc/vf610_adc.c
14986
14967
14987
14968
NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER
···
20779
20756
S: Odd Fixes
20780
20757
F: drivers/gpio/gpio-thunderx.c
20781
20758
20759
+
TI ADS7924 ADC DRIVER
20760
+
M: Hugo Villeneuve <hvilleneuve@dimonoff.com>
20761
+
L: linux-iio@vger.kernel.org
20762
+
S: Supported
20763
+
F: Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml
20764
+
F: drivers/iio/adc/ti-ads7924.c
20765
+
20782
20766
TI AM437X VPFE DRIVER
20783
20767
M: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
20784
20768
L: linux-media@vger.kernel.org
···
20905
20875
F: sound/soc/codecs/isabelle*
20906
20876
F: sound/soc/codecs/lm49453*
20907
20877
20878
+
TI LMP92064 ADC DRIVER
20879
+
M: Leonard Göhrs <l.goehrs@pengutronix.de>
20880
+
R: kernel@pengutronix.de
20881
+
L: linux-iio@vger.kernel.org
20882
+
S: Maintained
20883
+
F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml
20884
+
F: drivers/iio/adc/ti-lmp92064.c
20885
+
20908
20886
TI PCM3060 ASoC CODEC DRIVER
20909
20887
M: Kirill Marinushkin <kmarinushkin@birdec.com>
20910
20888
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
···
20925
20887
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
20926
20888
S: Odd Fixes
20927
20889
F: sound/soc/codecs/tas571x*
20890
+
20891
+
TI TMAG5273 MAGNETOMETER DRIVER
20892
+
M: Gerald Loacker <gerald.loacker@wolfvision.net>
20893
+
L: linux-iio@vger.kernel.org
20894
+
S: Maintained
20895
+
F: Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml
20896
+
F: drivers/iio/magnetometer/tmag5273.c
20928
20897
20929
20898
TI TRF7970A NFC DRIVER
20930
20899
M: Mark Greer <mgreer@animalcreek.com>
···
21834
21789
L: linux-kernel@vger.kernel.org
21835
21790
S: Maintained
21836
21791
F: include/linux/uuid.h
21837
-
F: include/uapi/linux/uuid.h
21838
21792
F: lib/test_uuid.c
21839
21793
F: lib/uuid.c
21840
21794
+1
-1
drivers/accessibility/speakup/main.c
+1
-1
drivers/accessibility/speakup/main.c
···
2490
2490
MODULE_PARM_DESC(reading_punc, "It controls the level of punctuation when reviewing the screen with speakup's screen review commands.");
2491
2491
MODULE_PARM_DESC(cursor_time, "This controls cursor delay when using arrow keys.");
2492
2492
MODULE_PARM_DESC(say_control, "This controls if speakup speaks shift, alt and control when those keys are pressed or not.");
2493
-
MODULE_PARM_DESC(say_word_ctl, "Sets thw say_word_ctl on load.");
2493
+
MODULE_PARM_DESC(say_word_ctl, "Sets the say_word_ctl on load.");
2494
2494
MODULE_PARM_DESC(no_interrupt, "Controls if typing interrupts output from speakup.");
2495
2495
MODULE_PARM_DESC(key_echo, "Controls if speakup speaks keys when they are typed. One = on zero = off or don't echo keys.");
2496
2496
MODULE_PARM_DESC(cur_phonetic, "Controls if speakup speaks letters phonetically during navigation. One = on zero = off or don't speak phonetically.");
+37
-28
drivers/android/binder.c
+37
-28
drivers/android/binder.c
···
277
277
278
278
/**
279
279
* binder_proc_unlock() - Release spinlock for given binder_proc
280
-
* @proc: struct binder_proc to acquire
280
+
* @proc: struct binder_proc to acquire
281
281
*
282
282
* Release lock acquired via binder_proc_lock()
283
283
*/
284
-
#define binder_proc_unlock(_proc) _binder_proc_unlock(_proc, __LINE__)
284
+
#define binder_proc_unlock(proc) _binder_proc_unlock(proc, __LINE__)
285
285
static void
286
286
_binder_proc_unlock(struct binder_proc *proc, int line)
287
287
__releases(&proc->outer_lock)
···
378
378
}
379
379
380
380
/**
381
-
* binder_node_unlock() - Release node and inner locks
381
+
* binder_node_inner_unlock() - Release node and inner locks
382
382
* @node: struct binder_node to acquire
383
383
*
384
384
* Release lock acquired via binder_node_lock()
···
1194
1194
}
1195
1195
1196
1196
/**
1197
-
* binder_dec_ref() - dec the ref for given handle
1197
+
* binder_dec_ref_olocked() - dec the ref for given handle
1198
1198
* @ref: ref to be decremented
1199
1199
* @strong: if true, strong decrement, else weak
1200
1200
*
1201
1201
* Decrement the ref.
1202
1202
*
1203
-
* Return: true if ref is cleaned up and ready to be freed
1203
+
* Return: %true if ref is cleaned up and ready to be freed.
1204
1204
*/
1205
1205
static bool binder_dec_ref_olocked(struct binder_ref *ref, int strong)
1206
1206
{
···
2728
2728
*
2729
2729
* Return: 0 if the transaction was successfully queued
2730
2730
* BR_DEAD_REPLY if the target process or thread is dead
2731
-
* BR_FROZEN_REPLY if the target process or thread is frozen
2731
+
* BR_FROZEN_REPLY if the target process or thread is frozen and
2732
+
* the sync transaction was rejected
2733
+
* BR_TRANSACTION_PENDING_FROZEN if the target process is frozen
2734
+
* and the async transaction was successfully queued
2732
2735
*/
2733
2736
static int binder_proc_transaction(struct binder_transaction *t,
2734
2737
struct binder_proc *proc,
···
2741
2738
bool oneway = !!(t->flags & TF_ONE_WAY);
2742
2739
bool pending_async = false;
2743
2740
struct binder_transaction *t_outdated = NULL;
2741
+
bool frozen = false;
2744
2742
2745
2743
BUG_ON(!node);
2746
2744
binder_node_lock(node);
···
2755
2751
2756
2752
binder_inner_proc_lock(proc);
2757
2753
if (proc->is_frozen) {
2754
+
frozen = true;
2758
2755
proc->sync_recv |= !oneway;
2759
2756
proc->async_recv |= oneway;
2760
2757
}
2761
2758
2762
-
if ((proc->is_frozen && !oneway) || proc->is_dead ||
2759
+
if ((frozen && !oneway) || proc->is_dead ||
2763
2760
(thread && thread->is_dead)) {
2764
2761
binder_inner_proc_unlock(proc);
2765
2762
binder_node_unlock(node);
2766
-
return proc->is_frozen ? BR_FROZEN_REPLY : BR_DEAD_REPLY;
2763
+
return frozen ? BR_FROZEN_REPLY : BR_DEAD_REPLY;
2767
2764
}
2768
2765
2769
2766
if (!thread && !pending_async)
···
2775
2770
} else if (!pending_async) {
2776
2771
binder_enqueue_work_ilocked(&t->work, &proc->todo);
2777
2772
} else {
2778
-
if ((t->flags & TF_UPDATE_TXN) && proc->is_frozen) {
2773
+
if ((t->flags & TF_UPDATE_TXN) && frozen) {
2779
2774
t_outdated = binder_find_outdated_transaction_ilocked(t,
2780
2775
&node->async_todo);
2781
2776
if (t_outdated) {
···
2812
2807
binder_stats_deleted(BINDER_STAT_TRANSACTION);
2813
2808
}
2814
2809
2810
+
if (oneway && frozen)
2811
+
return BR_TRANSACTION_PENDING_FROZEN;
2812
+
2815
2813
return 0;
2816
2814
}
2817
2815
2818
2816
/**
2819
2817
* binder_get_node_refs_for_txn() - Get required refs on node for txn
2820
2818
* @node: struct binder_node for which to get refs
2821
-
* @proc: returns @node->proc if valid
2822
-
* @error: if no @proc then returns BR_DEAD_REPLY
2819
+
* @procp: returns @node->proc if valid
2820
+
* @error: if no @procp then returns BR_DEAD_REPLY
2823
2821
*
2824
2822
* User-space normally keeps the node alive when creating a transaction
2825
2823
* since it has a reference to the target. The local strong ref keeps it
···
2836
2828
* constructing the transaction, so we take that here as well.
2837
2829
*
2838
2830
* Return: The target_node with refs taken or NULL if no @node->proc is NULL.
2839
-
* Also sets @proc if valid. If the @node->proc is NULL indicating that the
2840
-
* target proc has died, @error is set to BR_DEAD_REPLY
2831
+
* Also sets @procp if valid. If the @node->proc is NULL indicating that the
2832
+
* target proc has died, @error is set to BR_DEAD_REPLY.
2841
2833
*/
2842
2834
static struct binder_node *binder_get_node_refs_for_txn(
2843
2835
struct binder_node *node,
···
3615
3607
} else {
3616
3608
BUG_ON(target_node == NULL);
3617
3609
BUG_ON(t->buffer->async_transaction != 1);
3618
-
binder_enqueue_thread_work(thread, tcomplete);
3619
3610
return_error = binder_proc_transaction(t, target_proc, NULL);
3620
-
if (return_error)
3611
+
/*
3612
+
* Let the caller know when async transaction reaches a frozen
3613
+
* process and is put in a pending queue, waiting for the target
3614
+
* process to be unfrozen.
3615
+
*/
3616
+
if (return_error == BR_TRANSACTION_PENDING_FROZEN)
3617
+
tcomplete->type = BINDER_WORK_TRANSACTION_PENDING;
3618
+
binder_enqueue_thread_work(thread, tcomplete);
3619
+
if (return_error &&
3620
+
return_error != BR_TRANSACTION_PENDING_FROZEN)
3621
3621
goto err_dead_proc_or_thread;
3622
3622
}
3623
3623
if (target_thread)
···
4456
4440
binder_stat_br(proc, thread, cmd);
4457
4441
} break;
4458
4442
case BINDER_WORK_TRANSACTION_COMPLETE:
4443
+
case BINDER_WORK_TRANSACTION_PENDING:
4459
4444
case BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT: {
4460
4445
if (proc->oneway_spam_detection_enabled &&
4461
4446
w->type == BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT)
4462
4447
cmd = BR_ONEWAY_SPAM_SUSPECT;
4448
+
else if (w->type == BINDER_WORK_TRANSACTION_PENDING)
4449
+
cmd = BR_TRANSACTION_PENDING_FROZEN;
4463
4450
else
4464
4451
cmd = BR_TRANSACTION_COMPLETE;
4465
4452
binder_inner_proc_unlock(proc);
···
5025
5006
return 0;
5026
5007
}
5027
5008
5028
-
static int binder_ioctl_write_read(struct file *filp,
5029
-
unsigned int cmd, unsigned long arg,
5009
+
static int binder_ioctl_write_read(struct file *filp, unsigned long arg,
5030
5010
struct binder_thread *thread)
5031
5011
{
5032
5012
int ret = 0;
5033
5013
struct binder_proc *proc = filp->private_data;
5034
-
unsigned int size = _IOC_SIZE(cmd);
5035
5014
void __user *ubuf = (void __user *)arg;
5036
5015
struct binder_write_read bwr;
5037
5016
5038
-
if (size != sizeof(struct binder_write_read)) {
5039
-
ret = -EINVAL;
5040
-
goto out;
5041
-
}
5042
5017
if (copy_from_user(&bwr, ubuf, sizeof(bwr))) {
5043
5018
ret = -EFAULT;
5044
5019
goto out;
···
5309
5296
int ret;
5310
5297
struct binder_proc *proc = filp->private_data;
5311
5298
struct binder_thread *thread;
5312
-
unsigned int size = _IOC_SIZE(cmd);
5313
5299
void __user *ubuf = (void __user *)arg;
5314
5300
5315
5301
/*pr_info("binder_ioctl: %d:%d %x %lx\n",
···
5330
5318
5331
5319
switch (cmd) {
5332
5320
case BINDER_WRITE_READ:
5333
-
ret = binder_ioctl_write_read(filp, cmd, arg, thread);
5321
+
ret = binder_ioctl_write_read(filp, arg, thread);
5334
5322
if (ret)
5335
5323
goto err;
5336
5324
break;
···
5373
5361
case BINDER_VERSION: {
5374
5362
struct binder_version __user *ver = ubuf;
5375
5363
5376
-
if (size != sizeof(struct binder_version)) {
5377
-
ret = -EINVAL;
5378
-
goto err;
5379
-
}
5380
5364
if (put_user(BINDER_CURRENT_PROTOCOL_VERSION,
5381
5365
&ver->protocol_version)) {
5382
5366
ret = -EINVAL;
···
6177
6169
"BR_FAILED_REPLY",
6178
6170
"BR_FROZEN_REPLY",
6179
6171
"BR_ONEWAY_SPAM_SUSPECT",
6172
+
"BR_TRANSACTION_PENDING_FROZEN"
6180
6173
};
6181
6174
6182
6175
static const char * const binder_command_strings[] = {
+2
-1
drivers/android/binder_internal.h
+2
-1
drivers/android/binder_internal.h
···
133
133
};
134
134
135
135
struct binder_stats {
136
-
atomic_t br[_IOC_NR(BR_ONEWAY_SPAM_SUSPECT) + 1];
136
+
atomic_t br[_IOC_NR(BR_TRANSACTION_PENDING_FROZEN) + 1];
137
137
atomic_t bc[_IOC_NR(BC_REPLY_SG) + 1];
138
138
atomic_t obj_created[BINDER_STAT_COUNT];
139
139
atomic_t obj_deleted[BINDER_STAT_COUNT];
···
152
152
enum binder_work_type {
153
153
BINDER_WORK_TRANSACTION = 1,
154
154
BINDER_WORK_TRANSACTION_COMPLETE,
155
+
BINDER_WORK_TRANSACTION_PENDING,
155
156
BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT,
156
157
BINDER_WORK_RETURN_ERROR,
157
158
BINDER_WORK_NODE,
+2
-2
drivers/android/binderfs.c
+2
-2
drivers/android/binderfs.c
···
222
222
}
223
223
224
224
/**
225
-
* binderfs_ctl_ioctl - handle binder device node allocation requests
225
+
* binder_ctl_ioctl - handle binder device node allocation requests
226
226
*
227
227
* The request handler for the binder-control device. All requests operate on
228
228
* the binderfs mount the binder-control device resides in:
229
229
* - BINDER_CTL_ADD
230
230
* Allocate a new binder device.
231
231
*
232
-
* Return: 0 on success, negative errno on failure
232
+
* Return: %0 on success, negative errno on failure.
233
233
*/
234
234
static long binder_ctl_ioctl(struct file *file, unsigned int cmd,
235
235
unsigned long arg)
+2
-2
drivers/bus/mhi/Makefile
+2
-2
drivers/bus/mhi/Makefile
+46
-39
drivers/bus/mhi/ep/main.c
+46
-39
drivers/bus/mhi/ep/main.c
···
123
123
int ret;
124
124
125
125
ch_id = MHI_TRE_GET_CMD_CHID(el);
126
+
127
+
/* Check if the channel is supported by the controller */
128
+
if ((ch_id >= mhi_cntrl->max_chan) || !mhi_cntrl->mhi_chan[ch_id].name) {
129
+
dev_err(dev, "Channel (%u) not supported!\n", ch_id);
130
+
return -ENODEV;
131
+
}
132
+
126
133
mhi_chan = &mhi_cntrl->mhi_chan[ch_id];
127
134
ch_ring = &mhi_cntrl->mhi_chan[ch_id].ring;
128
135
···
203
196
mhi_ep_mmio_disable_chdb(mhi_cntrl, ch_id);
204
197
205
198
/* Send channel disconnect status to client drivers */
206
-
result.transaction_status = -ENOTCONN;
207
-
result.bytes_xferd = 0;
208
-
mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
199
+
if (mhi_chan->xfer_cb) {
200
+
result.transaction_status = -ENOTCONN;
201
+
result.bytes_xferd = 0;
202
+
mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
203
+
}
209
204
210
205
/* Set channel state to STOP */
211
206
mhi_chan->state = MHI_CH_STATE_STOP;
···
226
217
mutex_unlock(&mhi_chan->lock);
227
218
break;
228
219
case MHI_PKT_TYPE_RESET_CHAN_CMD:
229
-
dev_dbg(dev, "Received STOP command for channel (%u)\n", ch_id);
220
+
dev_dbg(dev, "Received RESET command for channel (%u)\n", ch_id);
230
221
if (!ch_ring->started) {
231
222
dev_err(dev, "Channel (%u) not opened\n", ch_id);
232
223
return -ENODEV;
···
237
228
mhi_ep_ring_reset(mhi_cntrl, ch_ring);
238
229
239
230
/* Send channel disconnect status to client driver */
240
-
result.transaction_status = -ENOTCONN;
241
-
result.bytes_xferd = 0;
242
-
mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
231
+
if (mhi_chan->xfer_cb) {
232
+
result.transaction_status = -ENOTCONN;
233
+
result.bytes_xferd = 0;
234
+
mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result);
235
+
}
243
236
244
237
/* Set channel state to DISABLED */
245
238
mhi_chan->state = MHI_CH_STATE_DISABLED;
···
730
719
list_del(&itr->node);
731
720
ring = itr->ring;
732
721
722
+
chan = &mhi_cntrl->mhi_chan[ring->ch_id];
723
+
mutex_lock(&chan->lock);
724
+
725
+
/*
726
+
* The ring could've stopped while we waited to grab the (chan->lock), so do
727
+
* a sanity check before going further.
728
+
*/
729
+
if (!ring->started) {
730
+
mutex_unlock(&chan->lock);
731
+
kfree(itr);
732
+
continue;
733
+
}
734
+
733
735
/* Update the write offset for the ring */
734
736
ret = mhi_ep_update_wr_offset(ring);
735
737
if (ret) {
736
738
dev_err(dev, "Error updating write offset for ring\n");
739
+
mutex_unlock(&chan->lock);
737
740
kfree(itr);
738
741
continue;
739
742
}
740
743
741
744
/* Sanity check to make sure there are elements in the ring */
742
745
if (ring->rd_offset == ring->wr_offset) {
746
+
mutex_unlock(&chan->lock);
743
747
kfree(itr);
744
748
continue;
745
749
}
746
750
747
751
el = &ring->ring_cache[ring->rd_offset];
748
-
chan = &mhi_cntrl->mhi_chan[ring->ch_id];
749
752
750
-
mutex_lock(&chan->lock);
751
753
dev_dbg(dev, "Processing the ring for channel (%u)\n", ring->ch_id);
752
754
ret = mhi_ep_process_ch_ring(ring, el);
753
755
if (ret) {
···
997
973
static void mhi_ep_reset_worker(struct work_struct *work)
998
974
{
999
975
struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, reset_work);
1000
-
struct device *dev = &mhi_cntrl->mhi_dev->dev;
1001
976
enum mhi_state cur_state;
1002
-
int ret;
1003
977
1004
-
mhi_ep_abort_transfer(mhi_cntrl);
978
+
mhi_ep_power_down(mhi_cntrl);
1005
979
1006
-
spin_lock_bh(&mhi_cntrl->state_lock);
980
+
mutex_lock(&mhi_cntrl->state_lock);
981
+
1007
982
/* Reset MMIO to signal host that the MHI_RESET is completed in endpoint */
1008
983
mhi_ep_mmio_reset(mhi_cntrl);
1009
984
cur_state = mhi_cntrl->mhi_state;
1010
-
spin_unlock_bh(&mhi_cntrl->state_lock);
1011
985
1012
986
/*
1013
987
* Only proceed further if the reset is due to SYS_ERR. The host will
1014
988
* issue reset during shutdown also and we don't need to do re-init in
1015
989
* that case.
1016
990
*/
1017
-
if (cur_state == MHI_STATE_SYS_ERR) {
1018
-
mhi_ep_mmio_init(mhi_cntrl);
991
+
if (cur_state == MHI_STATE_SYS_ERR)
992
+
mhi_ep_power_up(mhi_cntrl);
1019
993
1020
-
/* Set AMSS EE before signaling ready state */
1021
-
mhi_ep_mmio_set_env(mhi_cntrl, MHI_EE_AMSS);
1022
-
1023
-
/* All set, notify the host that we are ready */
1024
-
ret = mhi_ep_set_ready_state(mhi_cntrl);
1025
-
if (ret)
1026
-
return;
1027
-
1028
-
dev_dbg(dev, "READY state notification sent to the host\n");
1029
-
1030
-
ret = mhi_ep_enable(mhi_cntrl);
1031
-
if (ret) {
1032
-
dev_err(dev, "Failed to enable MHI endpoint: %d\n", ret);
1033
-
return;
1034
-
}
1035
-
1036
-
enable_irq(mhi_cntrl->irq);
1037
-
}
994
+
mutex_unlock(&mhi_cntrl->state_lock);
1038
995
}
1039
996
1040
997
/*
···
1094
1089
1095
1090
void mhi_ep_power_down(struct mhi_ep_cntrl *mhi_cntrl)
1096
1091
{
1097
-
if (mhi_cntrl->enabled)
1092
+
if (mhi_cntrl->enabled) {
1098
1093
mhi_ep_abort_transfer(mhi_cntrl);
1099
-
1100
-
kfree(mhi_cntrl->mhi_event);
1101
-
disable_irq(mhi_cntrl->irq);
1094
+
kfree(mhi_cntrl->mhi_event);
1095
+
disable_irq(mhi_cntrl->irq);
1096
+
}
1102
1097
}
1103
1098
EXPORT_SYMBOL_GPL(mhi_ep_power_down);
1104
1099
···
1124
1119
1125
1120
dev_dbg(&mhi_chan->mhi_dev->dev, "Suspending channel\n");
1126
1121
/* Set channel state to SUSPENDED */
1122
+
mhi_chan->state = MHI_CH_STATE_SUSPENDED;
1127
1123
tmp &= ~CHAN_CTX_CHSTATE_MASK;
1128
1124
tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_SUSPENDED);
1129
1125
mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp);
···
1154
1148
1155
1149
dev_dbg(&mhi_chan->mhi_dev->dev, "Resuming channel\n");
1156
1150
/* Set channel state to RUNNING */
1151
+
mhi_chan->state = MHI_CH_STATE_RUNNING;
1157
1152
tmp &= ~CHAN_CTX_CHSTATE_MASK;
1158
1153
tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_RUNNING);
1159
1154
mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp);
···
1388
1381
1389
1382
INIT_LIST_HEAD(&mhi_cntrl->st_transition_list);
1390
1383
INIT_LIST_HEAD(&mhi_cntrl->ch_db_list);
1391
-
spin_lock_init(&mhi_cntrl->state_lock);
1392
1384
spin_lock_init(&mhi_cntrl->list_lock);
1385
+
mutex_init(&mhi_cntrl->state_lock);
1393
1386
mutex_init(&mhi_cntrl->event_lock);
1394
1387
1395
1388
/* Set MHI version and AMSS EE before enumeration */
+24
-18
drivers/bus/mhi/ep/sm.c
+24
-18
drivers/bus/mhi/ep/sm.c
···
63
63
int ret;
64
64
65
65
/* If MHI is in M3, resume suspended channels */
66
-
spin_lock_bh(&mhi_cntrl->state_lock);
66
+
mutex_lock(&mhi_cntrl->state_lock);
67
+
67
68
old_state = mhi_cntrl->mhi_state;
68
69
if (old_state == MHI_STATE_M3)
69
70
mhi_ep_resume_channels(mhi_cntrl);
70
71
71
72
ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
72
-
spin_unlock_bh(&mhi_cntrl->state_lock);
73
-
74
73
if (ret) {
75
74
mhi_ep_handle_syserr(mhi_cntrl);
76
-
return ret;
75
+
goto err_unlock;
77
76
}
78
77
79
78
/* Signal host that the device moved to M0 */
80
79
ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M0);
81
80
if (ret) {
82
81
dev_err(dev, "Failed sending M0 state change event\n");
83
-
return ret;
82
+
goto err_unlock;
84
83
}
85
84
86
85
if (old_state == MHI_STATE_READY) {
···
87
88
ret = mhi_ep_send_ee_event(mhi_cntrl, MHI_EE_AMSS);
88
89
if (ret) {
89
90
dev_err(dev, "Failed sending AMSS EE event\n");
90
-
return ret;
91
+
goto err_unlock;
91
92
}
92
93
}
93
94
94
-
return 0;
95
+
err_unlock:
96
+
mutex_unlock(&mhi_cntrl->state_lock);
97
+
98
+
return ret;
95
99
}
96
100
97
101
int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl)
···
102
100
struct device *dev = &mhi_cntrl->mhi_dev->dev;
103
101
int ret;
104
102
105
-
spin_lock_bh(&mhi_cntrl->state_lock);
106
-
ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
107
-
spin_unlock_bh(&mhi_cntrl->state_lock);
103
+
mutex_lock(&mhi_cntrl->state_lock);
108
104
105
+
ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
109
106
if (ret) {
110
107
mhi_ep_handle_syserr(mhi_cntrl);
111
-
return ret;
108
+
goto err_unlock;
112
109
}
113
110
114
111
mhi_ep_suspend_channels(mhi_cntrl);
···
116
115
ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M3);
117
116
if (ret) {
118
117
dev_err(dev, "Failed sending M3 state change event\n");
119
-
return ret;
118
+
goto err_unlock;
120
119
}
121
120
122
-
return 0;
121
+
err_unlock:
122
+
mutex_unlock(&mhi_cntrl->state_lock);
123
+
124
+
return ret;
123
125
}
124
126
125
127
int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl)
···
131
127
enum mhi_state mhi_state;
132
128
int ret, is_ready;
133
129
134
-
spin_lock_bh(&mhi_cntrl->state_lock);
130
+
mutex_lock(&mhi_cntrl->state_lock);
131
+
135
132
/* Ensure that the MHISTATUS is set to RESET by host */
136
133
mhi_state = mhi_ep_mmio_masked_read(mhi_cntrl, EP_MHISTATUS, MHISTATUS_MHISTATE_MASK);
137
134
is_ready = mhi_ep_mmio_masked_read(mhi_cntrl, EP_MHISTATUS, MHISTATUS_READY_MASK);
138
135
139
136
if (mhi_state != MHI_STATE_RESET || is_ready) {
140
137
dev_err(dev, "READY state transition failed. MHI host not in RESET state\n");
141
-
spin_unlock_bh(&mhi_cntrl->state_lock);
142
-
return -EIO;
138
+
ret = -EIO;
139
+
goto err_unlock;
143
140
}
144
141
145
142
ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_READY);
146
-
spin_unlock_bh(&mhi_cntrl->state_lock);
147
-
148
143
if (ret)
149
144
mhi_ep_handle_syserr(mhi_cntrl);
145
+
146
+
err_unlock:
147
+
mutex_unlock(&mhi_cntrl->state_lock);
150
148
151
149
return ret;
152
150
}
+1
-1
drivers/bus/mhi/host/init.c
+1
-1
drivers/bus/mhi/host/init.c
+46
drivers/bus/simple-pm-bus.c
+46
drivers/bus/simple-pm-bus.c
···
8
8
* for more details.
9
9
*/
10
10
11
+
#include <linux/clk.h>
11
12
#include <linux/module.h>
12
13
#include <linux/of_platform.h>
13
14
#include <linux/platform_device.h>
14
15
#include <linux/pm_runtime.h>
16
+
17
+
struct simple_pm_bus {
18
+
struct clk_bulk_data *clks;
19
+
int num_clks;
20
+
};
15
21
16
22
static int simple_pm_bus_probe(struct platform_device *pdev)
17
23
{
···
25
19
const struct of_dev_auxdata *lookup = dev_get_platdata(dev);
26
20
struct device_node *np = dev->of_node;
27
21
const struct of_device_id *match;
22
+
struct simple_pm_bus *bus;
28
23
29
24
/*
30
25
* Allow user to use driver_override to bind this driver to a
···
51
44
return -ENODEV;
52
45
}
53
46
47
+
bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
48
+
if (!bus)
49
+
return -ENOMEM;
50
+
51
+
bus->num_clks = devm_clk_bulk_get_all(&pdev->dev, &bus->clks);
52
+
if (bus->num_clks < 0)
53
+
return dev_err_probe(&pdev->dev, bus->num_clks, "failed to get clocks\n");
54
+
55
+
dev_set_drvdata(&pdev->dev, bus);
56
+
54
57
dev_dbg(&pdev->dev, "%s\n", __func__);
55
58
56
59
pm_runtime_enable(&pdev->dev);
···
84
67
return 0;
85
68
}
86
69
70
+
static int simple_pm_bus_runtime_suspend(struct device *dev)
71
+
{
72
+
struct simple_pm_bus *bus = dev_get_drvdata(dev);
73
+
74
+
clk_bulk_disable_unprepare(bus->num_clks, bus->clks);
75
+
76
+
return 0;
77
+
}
78
+
79
+
static int simple_pm_bus_runtime_resume(struct device *dev)
80
+
{
81
+
struct simple_pm_bus *bus = dev_get_drvdata(dev);
82
+
int ret;
83
+
84
+
ret = clk_bulk_prepare_enable(bus->num_clks, bus->clks);
85
+
if (ret) {
86
+
dev_err(dev, "failed to enable clocks: %d\n", ret);
87
+
return ret;
88
+
}
89
+
90
+
return 0;
91
+
}
92
+
93
+
static const struct dev_pm_ops simple_pm_bus_pm_ops = {
94
+
RUNTIME_PM_OPS(simple_pm_bus_runtime_suspend, simple_pm_bus_runtime_resume, NULL)
95
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
96
+
};
97
+
87
98
#define ONLY_BUS ((void *) 1) /* Match if the device is only a bus. */
88
99
89
100
static const struct of_device_id simple_pm_bus_of_match[] = {
···
130
85
.driver = {
131
86
.name = "simple-pm-bus",
132
87
.of_match_table = simple_pm_bus_of_match,
88
+
.pm = pm_ptr(&simple_pm_bus_pm_ops),
133
89
},
134
90
};
135
91
+4
-1
drivers/char/applicom.c
+4
-1
drivers/char/applicom.c
···
197
197
if (!pci_match_id(applicom_pci_tbl, dev))
198
198
continue;
199
199
200
-
if (pci_enable_device(dev))
200
+
if (pci_enable_device(dev)) {
201
+
pci_dev_put(dev);
201
202
return -EIO;
203
+
}
202
204
203
205
RamIO = ioremap(pci_resource_start(dev, 0), LEN_RAM_IO);
204
206
···
209
207
"space at 0x%llx\n",
210
208
(unsigned long long)pci_resource_start(dev, 0));
211
209
pci_disable_device(dev);
210
+
pci_dev_put(dev);
212
211
return -EIO;
213
212
}
214
213
+4
-2
drivers/char/pcmcia/cm4000_cs.c
+4
-2
drivers/char/pcmcia/cm4000_cs.c
···
529
529
DEBUGP(5, dev, "NumRecBytes is valid\n");
530
530
break;
531
531
}
532
-
usleep_range(10000, 11000);
532
+
/* can not sleep as this is in atomic context */
533
+
mdelay(10);
533
534
}
534
535
if (i == 100) {
535
536
DEBUGP(5, dev, "Timeout waiting for NumRecBytes getting "
···
550
549
}
551
550
break;
552
551
}
553
-
usleep_range(10000, 11000);
552
+
/* can not sleep as this is in atomic context */
553
+
mdelay(10);
554
554
}
555
555
556
556
/* check whether it is a short PTS reply? */
+11
-11
drivers/char/pcmcia/synclink_cs.c
+11
-11
drivers/char/pcmcia/synclink_cs.c
···
483
483
return mgslpc_get_text_ptr;
484
484
}
485
485
486
-
/**
486
+
/*
487
487
* line discipline callback wrappers
488
488
*
489
489
* The wrappers maintain line discipline references
···
3855
3855
3856
3856
#if SYNCLINK_GENERIC_HDLC
3857
3857
3858
-
/**
3858
+
/*
3859
3859
* called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3860
3860
* set encoding and frame check sequence (FCS) options
3861
3861
*
···
3908
3908
return 0;
3909
3909
}
3910
3910
3911
-
/**
3911
+
/*
3912
3912
* called by generic HDLC layer to send frame
3913
3913
*
3914
3914
* skb socket buffer containing HDLC frame
···
3953
3953
return NETDEV_TX_OK;
3954
3954
}
3955
3955
3956
-
/**
3956
+
/*
3957
3957
* called by network layer when interface enabled
3958
3958
* claim resources and initialize hardware
3959
3959
*
···
4016
4016
return 0;
4017
4017
}
4018
4018
4019
-
/**
4019
+
/*
4020
4020
* called by network layer when interface is disabled
4021
4021
* shutdown hardware and release resources
4022
4022
*
···
4047
4047
return 0;
4048
4048
}
4049
4049
4050
-
/**
4050
+
/*
4051
4051
* called by network layer to process IOCTL call to network device
4052
4052
*
4053
4053
* dev pointer to network device structure
···
4150
4150
}
4151
4151
}
4152
4152
4153
-
/**
4153
+
/*
4154
4154
* called by network layer when transmit timeout is detected
4155
4155
*
4156
4156
* dev pointer to network device structure
···
4173
4173
netif_wake_queue(dev);
4174
4174
}
4175
4175
4176
-
/**
4176
+
/*
4177
4177
* called by device driver when transmit completes
4178
4178
* reenable network layer transmit if stopped
4179
4179
*
···
4185
4185
netif_wake_queue(info->netdev);
4186
4186
}
4187
4187
4188
-
/**
4188
+
/*
4189
4189
* called by device driver when frame received
4190
4190
* pass frame to network layer
4191
4191
*
···
4225
4225
.ndo_tx_timeout = hdlcdev_tx_timeout,
4226
4226
};
4227
4227
4228
-
/**
4228
+
/*
4229
4229
* called by device driver when adding device instance
4230
4230
* do generic HDLC initialization
4231
4231
*
···
4273
4273
return 0;
4274
4274
}
4275
4275
4276
-
/**
4276
+
/*
4277
4277
* called by device driver when removing device instance
4278
4278
* do generic HDLC cleanup
4279
4279
*
+2
-3
drivers/char/virtio_console.c
+2
-3
drivers/char/virtio_console.c
···
1666
1666
"Not enough space to store port name\n");
1667
1667
break;
1668
1668
}
1669
-
strncpy(port->name, buf->buf + buf->offset + sizeof(*cpkt),
1670
-
name_size - 1);
1671
-
port->name[name_size - 1] = 0;
1669
+
strscpy(port->name, buf->buf + buf->offset + sizeof(*cpkt),
1670
+
name_size);
1672
1671
1673
1672
/*
1674
1673
* Since we only have one sysfs attribute, 'name',
+1
-1
drivers/comedi/Kconfig
+1
-1
drivers/comedi/Kconfig
+1
drivers/comedi/comedi_fops.c
+1
drivers/comedi/comedi_fops.c
···
1215
1215
case INSN_CONFIG_GET_CLOCK_SRC:
1216
1216
case INSN_CONFIG_SET_OTHER_SRC:
1217
1217
case INSN_CONFIG_GET_COUNTER_STATUS:
1218
+
case INSN_CONFIG_GET_PWM_OUTPUT:
1218
1219
case INSN_CONFIG_PWM_SET_H_BRIDGE:
1219
1220
case INSN_CONFIG_PWM_GET_H_BRIDGE:
1220
1221
case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
+47
-44
drivers/counter/Kconfig
+47
-44
drivers/counter/Kconfig
···
29
29
array module parameter. The interrupt line numbers for the devices may
30
30
be configured via the irq array module parameter.
31
31
32
+
config FTM_QUADDEC
33
+
tristate "Flex Timer Module Quadrature decoder driver"
34
+
depends on SOC_LS1021A || COMPILE_TEST
35
+
depends on HAS_IOMEM && OF
36
+
help
37
+
Select this option to enable the Flex Timer Quadrature decoder
38
+
driver.
39
+
40
+
To compile this driver as a module, choose M here: the
41
+
module will be called ftm-quaddec.
42
+
43
+
config INTEL_QEP
44
+
tristate "Intel Quadrature Encoder Peripheral driver"
45
+
depends on X86
46
+
depends on PCI
47
+
help
48
+
Select this option to enable the Intel Quadrature Encoder Peripheral
49
+
driver.
50
+
51
+
To compile this driver as a module, choose M here: the module
52
+
will be called intel-qep.
53
+
32
54
config INTERRUPT_CNT
33
55
tristate "Interrupt counter driver"
34
56
depends on GPIOLIB
···
61
39
To compile this driver as a module, choose M here: the
62
40
module will be called interrupt-cnt.
63
41
64
-
config STM32_TIMER_CNT
65
-
tristate "STM32 Timer encoder counter driver"
66
-
depends on MFD_STM32_TIMERS || COMPILE_TEST
42
+
config MICROCHIP_TCB_CAPTURE
43
+
tristate "Microchip Timer Counter Capture driver"
44
+
depends on SOC_AT91SAM9 || SOC_SAM_V7 || COMPILE_TEST
45
+
depends on HAS_IOMEM && OF
46
+
select REGMAP_MMIO
67
47
help
68
-
Select this option to enable STM32 Timer quadrature encoder
69
-
and counter driver.
48
+
Select this option to enable the Microchip Timer Counter Block
49
+
capture driver.
70
50
71
51
To compile this driver as a module, choose M here: the
72
-
module will be called stm32-timer-cnt.
52
+
module will be called microchip-tcb-capture.
73
53
74
54
config STM32_LPTIMER_CNT
75
55
tristate "STM32 LP Timer encoder counter driver"
···
83
59
To compile this driver as a module, choose M here: the
84
60
module will be called stm32-lptimer-cnt.
85
61
86
-
config TI_EQEP
87
-
tristate "TI eQEP counter driver"
88
-
depends on (SOC_AM33XX || COMPILE_TEST)
89
-
select REGMAP_MMIO
62
+
config STM32_TIMER_CNT
63
+
tristate "STM32 Timer encoder counter driver"
64
+
depends on MFD_STM32_TIMERS || COMPILE_TEST
90
65
help
91
-
Select this option to enable the Texas Instruments Enhanced Quadrature
92
-
Encoder Pulse (eQEP) counter driver.
93
-
94
-
To compile this driver as a module, choose M here: the module will be
95
-
called ti-eqep.
96
-
97
-
config FTM_QUADDEC
98
-
tristate "Flex Timer Module Quadrature decoder driver"
99
-
depends on HAS_IOMEM && OF
100
-
help
101
-
Select this option to enable the Flex Timer Quadrature decoder
102
-
driver.
66
+
Select this option to enable STM32 Timer quadrature encoder
67
+
and counter driver.
103
68
104
69
To compile this driver as a module, choose M here: the
105
-
module will be called ftm-quaddec.
106
-
107
-
config MICROCHIP_TCB_CAPTURE
108
-
tristate "Microchip Timer Counter Capture driver"
109
-
depends on HAS_IOMEM && OF
110
-
select REGMAP_MMIO
111
-
help
112
-
Select this option to enable the Microchip Timer Counter Block
113
-
capture driver.
114
-
115
-
To compile this driver as a module, choose M here: the
116
-
module will be called microchip-tcb-capture.
117
-
118
-
config INTEL_QEP
119
-
tristate "Intel Quadrature Encoder Peripheral driver"
120
-
depends on PCI
121
-
help
122
-
Select this option to enable the Intel Quadrature Encoder Peripheral
123
-
driver.
124
-
125
-
To compile this driver as a module, choose M here: the module
126
-
will be called intel-qep.
70
+
module will be called stm32-timer-cnt.
127
71
128
72
config TI_ECAP_CAPTURE
129
73
tristate "TI eCAP capture driver"
···
107
115
108
116
To compile this driver as a module, choose M here: the module
109
117
will be called ti-ecap-capture.
118
+
119
+
config TI_EQEP
120
+
tristate "TI eQEP counter driver"
121
+
depends on (SOC_AM33XX || COMPILE_TEST)
122
+
select REGMAP_MMIO
123
+
help
124
+
Select this option to enable the Texas Instruments Enhanced Quadrature
125
+
Encoder Pulse (eQEP) counter driver.
126
+
127
+
To compile this driver as a module, choose M here: the module will be
128
+
called ti-eqep.
110
129
111
130
endif # COUNTER
+154
-15
drivers/crypto/hisilicon/qm.c
+154
-15
drivers/crypto/hisilicon/qm.c
···
357
357
struct list_head list;
358
358
};
359
359
360
+
/**
361
+
* struct qm_hw_err - Structure describing the device errors
362
+
* @list: hardware error list
363
+
* @timestamp: timestamp when the error occurred
364
+
*/
365
+
struct qm_hw_err {
366
+
struct list_head list;
367
+
unsigned long long timestamp;
368
+
};
369
+
360
370
struct hisi_qm_hw_ops {
361
371
int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
362
372
void (*qm_db)(struct hisi_qm *qm, u16 qn,
···
2468
2458
return -EINVAL;
2469
2459
}
2470
2460
2461
+
/**
2462
+
* qm_hw_err_isolate() - Try to set the isolation status of the uacce device
2463
+
* according to user's configuration of error threshold.
2464
+
* @qm: the uacce device
2465
+
*/
2466
+
static int qm_hw_err_isolate(struct hisi_qm *qm)
2467
+
{
2468
+
struct qm_hw_err *err, *tmp, *hw_err;
2469
+
struct qm_err_isolate *isolate;
2470
+
u32 count = 0;
2471
+
2472
+
isolate = &qm->isolate_data;
2473
+
2474
+
#define SECONDS_PER_HOUR 3600
2475
+
2476
+
/* All the hw errs are processed by PF driver */
2477
+
if (qm->uacce->is_vf || isolate->is_isolate || !isolate->err_threshold)
2478
+
return 0;
2479
+
2480
+
hw_err = kzalloc(sizeof(*hw_err), GFP_KERNEL);
2481
+
if (!hw_err)
2482
+
return -ENOMEM;
2483
+
2484
+
/*
2485
+
* Time-stamp every slot AER error. Then check the AER error log when the
2486
+
* next device AER error occurred. if the device slot AER error count exceeds
2487
+
* the setting error threshold in one hour, the isolated state will be set
2488
+
* to true. And the AER error logs that exceed one hour will be cleared.
2489
+
*/
2490
+
mutex_lock(&isolate->isolate_lock);
2491
+
hw_err->timestamp = jiffies;
2492
+
list_for_each_entry_safe(err, tmp, &isolate->qm_hw_errs, list) {
2493
+
if ((hw_err->timestamp - err->timestamp) / HZ >
2494
+
SECONDS_PER_HOUR) {
2495
+
list_del(&err->list);
2496
+
kfree(err);
2497
+
} else {
2498
+
count++;
2499
+
}
2500
+
}
2501
+
list_add(&hw_err->list, &isolate->qm_hw_errs);
2502
+
mutex_unlock(&isolate->isolate_lock);
2503
+
2504
+
if (count >= isolate->err_threshold)
2505
+
isolate->is_isolate = true;
2506
+
2507
+
return 0;
2508
+
}
2509
+
2510
+
static void qm_hw_err_destroy(struct hisi_qm *qm)
2511
+
{
2512
+
struct qm_hw_err *err, *tmp;
2513
+
2514
+
mutex_lock(&qm->isolate_data.isolate_lock);
2515
+
list_for_each_entry_safe(err, tmp, &qm->isolate_data.qm_hw_errs, list) {
2516
+
list_del(&err->list);
2517
+
kfree(err);
2518
+
}
2519
+
mutex_unlock(&qm->isolate_data.isolate_lock);
2520
+
}
2521
+
2522
+
static enum uacce_dev_state hisi_qm_get_isolate_state(struct uacce_device *uacce)
2523
+
{
2524
+
struct hisi_qm *qm = uacce->priv;
2525
+
struct hisi_qm *pf_qm;
2526
+
2527
+
if (uacce->is_vf)
2528
+
pf_qm = pci_get_drvdata(pci_physfn(qm->pdev));
2529
+
else
2530
+
pf_qm = qm;
2531
+
2532
+
return pf_qm->isolate_data.is_isolate ?
2533
+
UACCE_DEV_ISOLATE : UACCE_DEV_NORMAL;
2534
+
}
2535
+
2536
+
static int hisi_qm_isolate_threshold_write(struct uacce_device *uacce, u32 num)
2537
+
{
2538
+
struct hisi_qm *qm = uacce->priv;
2539
+
2540
+
/* Must be set by PF */
2541
+
if (uacce->is_vf)
2542
+
return -EPERM;
2543
+
2544
+
if (qm->isolate_data.is_isolate)
2545
+
return -EPERM;
2546
+
2547
+
qm->isolate_data.err_threshold = num;
2548
+
2549
+
/* After the policy is updated, need to reset the hardware err list */
2550
+
qm_hw_err_destroy(qm);
2551
+
2552
+
return 0;
2553
+
}
2554
+
2555
+
static u32 hisi_qm_isolate_threshold_read(struct uacce_device *uacce)
2556
+
{
2557
+
struct hisi_qm *qm = uacce->priv;
2558
+
struct hisi_qm *pf_qm;
2559
+
2560
+
if (uacce->is_vf) {
2561
+
pf_qm = pci_get_drvdata(pci_physfn(qm->pdev));
2562
+
return pf_qm->isolate_data.err_threshold;
2563
+
}
2564
+
2565
+
return qm->isolate_data.err_threshold;
2566
+
}
2567
+
2471
2568
static const struct uacce_ops uacce_qm_ops = {
2472
2569
.get_available_instances = hisi_qm_get_available_instances,
2473
2570
.get_queue = hisi_qm_uacce_get_queue,
···
2584
2467
.mmap = hisi_qm_uacce_mmap,
2585
2468
.ioctl = hisi_qm_uacce_ioctl,
2586
2469
.is_q_updated = hisi_qm_is_q_updated,
2470
+
.get_isolate_state = hisi_qm_get_isolate_state,
2471
+
.isolate_err_threshold_write = hisi_qm_isolate_threshold_write,
2472
+
.isolate_err_threshold_read = hisi_qm_isolate_threshold_read,
2587
2473
};
2474
+
2475
+
static void qm_remove_uacce(struct hisi_qm *qm)
2476
+
{
2477
+
struct uacce_device *uacce = qm->uacce;
2478
+
2479
+
if (qm->use_sva) {
2480
+
qm_hw_err_destroy(qm);
2481
+
uacce_remove(uacce);
2482
+
qm->uacce = NULL;
2483
+
}
2484
+
}
2588
2485
2589
2486
static int qm_alloc_uacce(struct hisi_qm *qm)
2590
2487
{
···
2626
2495
qm->use_sva = true;
2627
2496
} else {
2628
2497
/* only consider sva case */
2629
-
uacce_remove(uacce);
2630
-
qm->uacce = NULL;
2498
+
qm_remove_uacce(qm);
2631
2499
return -EINVAL;
2632
2500
}
2633
2501
···
2659
2529
uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr;
2660
2530
2661
2531
qm->uacce = uacce;
2532
+
INIT_LIST_HEAD(&qm->isolate_data.qm_hw_errs);
2533
+
mutex_init(&qm->isolate_data.isolate_lock);
2662
2534
2663
2535
return 0;
2664
2536
}
···
4149
4017
return ret;
4150
4018
}
4151
4019
4020
+
if (qm->use_sva) {
4021
+
ret = qm_hw_err_isolate(qm);
4022
+
if (ret)
4023
+
pci_err(pdev, "failed to isolate hw err!\n");
4024
+
}
4025
+
4152
4026
ret = qm_wait_vf_prepare_finish(qm);
4153
4027
if (ret)
4154
4028
pci_err(pdev, "failed to stop by vfs in soft reset!\n");
···
4459
4321
qm->err_ini->show_last_dfx_regs(qm);
4460
4322
4461
4323
ret = qm_soft_reset(qm);
4462
-
if (ret) {
4463
-
pci_err(pdev, "Controller reset failed (%d)\n", ret);
4464
-
qm_reset_bit_clear(qm);
4465
-
return ret;
4466
-
}
4324
+
if (ret)
4325
+
goto err_reset;
4467
4326
4468
4327
ret = qm_controller_reset_done(qm);
4469
-
if (ret) {
4470
-
qm_reset_bit_clear(qm);
4471
-
return ret;
4472
-
}
4328
+
if (ret)
4329
+
goto err_reset;
4473
4330
4474
4331
pci_info(pdev, "Controller reset complete\n");
4475
4332
4476
4333
return 0;
4334
+
4335
+
err_reset:
4336
+
pci_err(pdev, "Controller reset failed (%d)\n", ret);
4337
+
qm_reset_bit_clear(qm);
4338
+
4339
+
/* if resetting fails, isolate the device */
4340
+
if (qm->use_sva)
4341
+
qm->isolate_data.is_isolate = true;
4342
+
return ret;
4477
4343
}
4478
4344
4479
4345
/**
···
5397
5255
err_free_qm_memory:
5398
5256
hisi_qm_memory_uninit(qm);
5399
5257
err_alloc_uacce:
5400
-
if (qm->use_sva) {
5401
-
uacce_remove(qm->uacce);
5402
-
qm->uacce = NULL;
5403
-
}
5258
+
qm_remove_uacce(qm);
5404
5259
err_irq_register:
5405
5260
qm_irqs_unregister(qm);
5406
5261
err_pci_init:
+7
-7
drivers/firmware/dmi-sysfs.c
+7
-7
drivers/firmware/dmi-sysfs.c
···
418
418
return dmi_sel_raw_read_phys32(entry, &sel, state->buf,
419
419
state->pos, state->count);
420
420
case DMI_SEL_ACCESS_METHOD_GPNV:
421
-
pr_info("dmi-sysfs: GPNV support missing.\n");
421
+
pr_info_ratelimited("dmi-sysfs: GPNV support missing.\n");
422
422
return -EIO;
423
423
default:
424
-
pr_info("dmi-sysfs: Unknown access method %02x\n",
424
+
pr_info_ratelimited("dmi-sysfs: Unknown access method %02x\n",
425
425
sel.access_method);
426
426
return -EIO;
427
427
}
···
603
603
*ret = kobject_init_and_add(&entry->kobj, &dmi_sysfs_entry_ktype, NULL,
604
604
"%d-%d", dh->type, entry->instance);
605
605
606
-
if (*ret) {
607
-
kobject_put(&entry->kobj);
608
-
return;
609
-
}
610
-
611
606
/* Thread on the global list for cleanup */
612
607
spin_lock(&entry_list_lock);
613
608
list_add_tail(&entry->list, &entry_list);
614
609
spin_unlock(&entry_list_lock);
610
+
611
+
if (*ret) {
612
+
kobject_put(&entry->kobj);
613
+
return;
614
+
}
615
615
616
616
/* Handle specializations by type */
617
617
switch (dh->type) {
-8
drivers/firmware/google/Kconfig
-8
drivers/firmware/google/Kconfig
···
44
44
device tree node /firmware/coreboot.
45
45
If unsure say N.
46
46
47
-
config GOOGLE_COREBOOT_TABLE_ACPI
48
-
tristate
49
-
select GOOGLE_COREBOOT_TABLE
50
-
51
-
config GOOGLE_COREBOOT_TABLE_OF
52
-
tristate
53
-
select GOOGLE_COREBOOT_TABLE
54
-
55
47
config GOOGLE_MEMCONSOLE
56
48
tristate
57
49
depends on GOOGLE_MEMCONSOLE_X86_LEGACY || GOOGLE_MEMCONSOLE_COREBOOT
+1
-3
drivers/firmware/google/framebuffer-coreboot.c
+1
-3
drivers/firmware/google/framebuffer-coreboot.c
···
43
43
fb->green_mask_pos == formats[i].green.offset &&
44
44
fb->green_mask_size == formats[i].green.length &&
45
45
fb->blue_mask_pos == formats[i].blue.offset &&
46
-
fb->blue_mask_size == formats[i].blue.length &&
47
-
fb->reserved_mask_pos == formats[i].transp.offset &&
48
-
fb->reserved_mask_size == formats[i].transp.length)
46
+
fb->blue_mask_size == formats[i].blue.length)
49
47
pdata.format = formats[i].name;
50
48
}
51
49
if (!pdata.format)
+17
-8
drivers/firmware/stratix10-svc.c
+17
-8
drivers/firmware/stratix10-svc.c
···
1138
1138
1139
1139
/* allocate service controller and supporting channel */
1140
1140
controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
1141
-
if (!controller)
1142
-
return -ENOMEM;
1141
+
if (!controller) {
1142
+
ret = -ENOMEM;
1143
+
goto err_destroy_pool;
1144
+
}
1143
1145
1144
1146
chans = devm_kmalloc_array(dev, SVC_NUM_CHANNEL,
1145
1147
sizeof(*chans), GFP_KERNEL | __GFP_ZERO);
1146
-
if (!chans)
1147
-
return -ENOMEM;
1148
+
if (!chans) {
1149
+
ret = -ENOMEM;
1150
+
goto err_destroy_pool;
1151
+
}
1148
1152
1149
1153
controller->dev = dev;
1150
1154
controller->num_chans = SVC_NUM_CHANNEL;
···
1163
1159
ret = kfifo_alloc(&controller->svc_fifo, fifo_size, GFP_KERNEL);
1164
1160
if (ret) {
1165
1161
dev_err(dev, "failed to allocate FIFO\n");
1166
-
return ret;
1162
+
goto err_destroy_pool;
1167
1163
}
1168
1164
spin_lock_init(&controller->svc_fifo_lock);
1169
1165
···
1202
1198
ret = platform_device_add(svc->stratix10_svc_rsu);
1203
1199
if (ret) {
1204
1200
platform_device_put(svc->stratix10_svc_rsu);
1205
-
return ret;
1201
+
goto err_free_kfifo;
1206
1202
}
1207
1203
1208
1204
svc->intel_svc_fcs = platform_device_alloc(INTEL_FCS, 1);
1209
1205
if (!svc->intel_svc_fcs) {
1210
1206
dev_err(dev, "failed to allocate %s device\n", INTEL_FCS);
1211
-
return -ENOMEM;
1207
+
ret = -ENOMEM;
1208
+
goto err_unregister_dev;
1212
1209
}
1213
1210
1214
1211
ret = platform_device_add(svc->intel_svc_fcs);
1215
1212
if (ret) {
1216
1213
platform_device_put(svc->intel_svc_fcs);
1217
-
return ret;
1214
+
goto err_unregister_dev;
1218
1215
}
1219
1216
1220
1217
dev_set_drvdata(dev, svc);
···
1224
1219
1225
1220
return 0;
1226
1221
1222
+
err_unregister_dev:
1223
+
platform_device_unregister(svc->stratix10_svc_rsu);
1227
1224
err_free_kfifo:
1228
1225
kfifo_free(&controller->svc_fifo);
1226
+
err_destroy_pool:
1227
+
gen_pool_destroy(genpool);
1229
1228
return ret;
1230
1229
}
1231
1230
+1
drivers/fpga/dfl-afu-region.c
+1
drivers/fpga/dfl-afu-region.c
+1
-1
drivers/fpga/dfl-afu.h
+1
-1
drivers/fpga/dfl-afu.h
+1
-1
drivers/fpga/dfl-fme-perf.c
+1
-1
drivers/fpga/dfl-fme-perf.c
···
141
141
* @fab_port_id: used to indicate current working mode of fabric counters.
142
142
* @fab_lock: lock to protect fabric counters working mode.
143
143
* @cpu: active CPU to which the PMU is bound for accesses.
144
-
* @cpuhp_node: node for CPU hotplug notifier link.
144
+
* @node: node for CPU hotplug notifier link.
145
145
* @cpuhp_state: state for CPU hotplug notification;
146
146
*/
147
147
struct fme_perf_priv {
+2
-2
drivers/fpga/dfl-fme-pr.c
+2
-2
drivers/fpga/dfl-fme-pr.c
···
164
164
165
165
/**
166
166
* dfl_fme_create_mgr - create fpga mgr platform device as child device
167
-
*
167
+
* @feature: sub feature info
168
168
* @pdata: fme platform_device's pdata
169
169
*
170
170
* Return: mgr platform device if successful, and error code otherwise.
···
273
273
}
274
274
275
275
/**
276
-
* dfl_fme_destroy_bridge - destroy all fpga bridge platform device
276
+
* dfl_fme_destroy_bridges - destroy all fpga bridge platform device
277
277
* @pdata: fme platform device's pdata
278
278
*/
279
279
static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata)
+1
-1
drivers/fpga/dfl-fme-pr.h
+1
-1
drivers/fpga/dfl-fme-pr.h
+2
-2
drivers/fpga/dfl.c
+2
-2
drivers/fpga/dfl.c
···
46
46
};
47
47
48
48
/**
49
-
* dfl_dev_info - dfl feature device information.
49
+
* struct dfl_dev_info - dfl feature device information.
50
50
* @name: name string of the feature platform device.
51
51
* @dfh_id: id value in Device Feature Header (DFH) register by DFL spec.
52
52
* @id: idr id of the feature dev.
···
68
68
};
69
69
70
70
/**
71
-
* dfl_chardev_info - chardev information of dfl feature device
71
+
* struct dfl_chardev_info - chardev information of dfl feature device
72
72
* @name: nmae string of the char device.
73
73
* @devt: devt of the char device.
74
74
*/
+1
-1
drivers/fpga/dfl.h
+1
-1
drivers/fpga/dfl.h
···
267
267
*
268
268
* @dev: ptr to pdev of the feature device which has the sub feature.
269
269
* @id: sub feature id.
270
-
* @revision: revisition of the instance of a feature.
270
+
* @revision: revision of this sub feature.
271
271
* @resource_index: each sub feature has one mmio resource for its registers.
272
272
* this index is used to find its mmio resource from the
273
273
* feature dev (platform device)'s resources.
+7
-4
drivers/fpga/fpga-bridge.c
+7
-4
drivers/fpga/fpga-bridge.c
···
293
293
struct device_attribute *attr, char *buf)
294
294
{
295
295
struct fpga_bridge *bridge = to_fpga_bridge(dev);
296
-
int enable = 1;
296
+
int state = 1;
297
297
298
-
if (bridge->br_ops && bridge->br_ops->enable_show)
299
-
enable = bridge->br_ops->enable_show(bridge);
298
+
if (bridge->br_ops && bridge->br_ops->enable_show) {
299
+
state = bridge->br_ops->enable_show(bridge);
300
+
if (state < 0)
301
+
return state;
302
+
}
300
303
301
-
return sprintf(buf, "%s\n", enable ? "enabled" : "disabled");
304
+
return sysfs_emit(buf, "%s\n", state ? "enabled" : "disabled");
302
305
}
303
306
304
307
static DEVICE_ATTR_RO(name);
+79
-66
drivers/fpga/microchip-spi.c
+79
-66
drivers/fpga/microchip-spi.c
···
6
6
#include <asm/unaligned.h>
7
7
#include <linux/delay.h>
8
8
#include <linux/fpga/fpga-mgr.h>
9
+
#include <linux/iopoll.h>
9
10
#include <linux/module.h>
10
11
#include <linux/of_device.h>
11
12
#include <linux/spi/spi.h>
···
34
33
35
34
#define MPF_BITS_PER_COMPONENT_SIZE 22
36
35
37
-
#define MPF_STATUS_POLL_RETRIES 10000
36
+
#define MPF_STATUS_POLL_TIMEOUT (2 * USEC_PER_SEC)
38
37
#define MPF_STATUS_BUSY BIT(0)
39
38
#define MPF_STATUS_READY BIT(1)
40
39
#define MPF_STATUS_SPI_VIOLATION BIT(2)
···
43
42
struct mpf_priv {
44
43
struct spi_device *spi;
45
44
bool program_mode;
45
+
u8 tx __aligned(ARCH_KMALLOC_MINALIGN);
46
+
u8 rx;
46
47
};
47
48
48
-
static int mpf_read_status(struct spi_device *spi)
49
+
static int mpf_read_status(struct mpf_priv *priv)
49
50
{
50
-
u8 status = 0, status_command = MPF_SPI_READ_STATUS;
51
-
struct spi_transfer xfers[2] = { 0 };
52
-
int ret;
53
-
54
51
/*
55
52
* HW status is returned on MISO in the first byte after CS went
56
53
* active. However, first reading can be inadequate, so we submit
57
54
* two identical SPI transfers and use result of the later one.
58
55
*/
59
-
xfers[0].tx_buf = &status_command;
60
-
xfers[1].tx_buf = &status_command;
61
-
xfers[0].rx_buf = &status;
62
-
xfers[1].rx_buf = &status;
63
-
xfers[0].len = 1;
64
-
xfers[1].len = 1;
65
-
xfers[0].cs_change = 1;
56
+
struct spi_transfer xfers[2] = {
57
+
{
58
+
.tx_buf = &priv->tx,
59
+
.rx_buf = &priv->rx,
60
+
.len = 1,
61
+
.cs_change = 1,
62
+
}, {
63
+
.tx_buf = &priv->tx,
64
+
.rx_buf = &priv->rx,
65
+
.len = 1,
66
+
},
67
+
};
68
+
u8 status;
69
+
int ret;
66
70
67
-
ret = spi_sync_transfer(spi, xfers, 2);
71
+
priv->tx = MPF_SPI_READ_STATUS;
72
+
73
+
ret = spi_sync_transfer(priv->spi, xfers, 2);
74
+
if (ret)
75
+
return ret;
76
+
77
+
status = priv->rx;
68
78
69
79
if ((status & MPF_STATUS_SPI_VIOLATION) ||
70
80
(status & MPF_STATUS_SPI_ERROR))
71
-
ret = -EIO;
81
+
return -EIO;
72
82
73
-
return ret ? : status;
83
+
return status;
74
84
}
75
85
76
86
static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)
77
87
{
78
88
struct mpf_priv *priv = mgr->priv;
79
-
struct spi_device *spi;
80
89
bool program_mode;
81
90
int status;
82
91
83
-
spi = priv->spi;
84
92
program_mode = priv->program_mode;
85
-
status = mpf_read_status(spi);
93
+
status = mpf_read_status(priv);
86
94
87
95
if (!program_mode && !status)
88
96
return FPGA_MGR_STATE_OPERATING;
···
195
185
return 0;
196
186
}
197
187
198
-
/* Poll HW status until busy bit is cleared and mask bits are set. */
199
-
static int mpf_poll_status(struct spi_device *spi, u8 mask)
188
+
static int mpf_poll_status(struct mpf_priv *priv, u8 mask)
200
189
{
201
-
int status, retries = MPF_STATUS_POLL_RETRIES;
190
+
int ret, status;
202
191
203
-
while (retries--) {
204
-
status = mpf_read_status(spi);
205
-
if (status < 0)
206
-
return status;
192
+
/*
193
+
* Busy poll HW status. Polling stops if any of the following
194
+
* conditions are met:
195
+
* - timeout is reached
196
+
* - mpf_read_status() returns an error
197
+
* - busy bit is cleared AND mask bits are set
198
+
*/
199
+
ret = read_poll_timeout(mpf_read_status, status,
200
+
(status < 0) ||
201
+
((status & (MPF_STATUS_BUSY | mask)) == mask),
202
+
0, MPF_STATUS_POLL_TIMEOUT, false, priv);
203
+
if (ret < 0)
204
+
return ret;
207
205
208
-
if (status & MPF_STATUS_BUSY)
209
-
continue;
210
-
211
-
if (!mask || (status & mask))
212
-
return status;
213
-
}
214
-
215
-
return -EBUSY;
206
+
return status;
216
207
}
217
208
218
-
static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size)
209
+
static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size)
219
210
{
220
-
int status = mpf_poll_status(spi, 0);
211
+
int status = mpf_poll_status(priv, 0);
221
212
222
213
if (status < 0)
223
214
return status;
224
215
225
-
return spi_write(spi, buf, buf_size);
216
+
return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0);
226
217
}
227
218
228
-
static int mpf_spi_write_then_read(struct spi_device *spi,
219
+
static int mpf_spi_write_then_read(struct mpf_priv *priv,
229
220
const void *txbuf, size_t txbuf_size,
230
221
void *rxbuf, size_t rxbuf_size)
231
222
{
232
223
const u8 read_command[] = { MPF_SPI_READ_DATA };
233
224
int ret;
234
225
235
-
ret = mpf_spi_write(spi, txbuf, txbuf_size);
226
+
ret = mpf_spi_write(priv, txbuf, txbuf_size);
236
227
if (ret)
237
228
return ret;
238
229
239
-
ret = mpf_poll_status(spi, MPF_STATUS_READY);
230
+
ret = mpf_poll_status(priv, MPF_STATUS_READY);
240
231
if (ret < 0)
241
232
return ret;
242
233
243
-
return spi_write_then_read(spi, read_command, sizeof(read_command),
234
+
return spi_write_then_read(priv->spi, read_command, sizeof(read_command),
244
235
rxbuf, rxbuf_size);
245
236
}
246
237
···
253
242
const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE };
254
243
struct mpf_priv *priv = mgr->priv;
255
244
struct device *dev = &mgr->dev;
256
-
struct spi_device *spi;
257
245
u32 isc_ret = 0;
258
246
int ret;
259
247
···
261
251
return -EOPNOTSUPP;
262
252
}
263
253
264
-
spi = priv->spi;
265
-
266
-
ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command),
254
+
ret = mpf_spi_write_then_read(priv, isc_en_command, sizeof(isc_en_command),
267
255
&isc_ret, sizeof(isc_ret));
268
256
if (ret || isc_ret) {
269
257
dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n",
···
269
261
return -EFAULT;
270
262
}
271
263
272
-
ret = mpf_spi_write(spi, program_mode, sizeof(program_mode));
264
+
ret = mpf_spi_write(priv, program_mode, sizeof(program_mode));
273
265
if (ret) {
274
266
dev_err(dev, "Failed to enter program mode: %d\n", ret);
275
267
return ret;
···
280
272
return 0;
281
273
}
282
274
275
+
static int mpf_spi_frame_write(struct mpf_priv *priv, const char *buf)
276
+
{
277
+
struct spi_transfer xfers[2] = {
278
+
{
279
+
.tx_buf = &priv->tx,
280
+
.len = 1,
281
+
}, {
282
+
.tx_buf = buf,
283
+
.len = MPF_SPI_FRAME_SIZE,
284
+
},
285
+
};
286
+
int ret;
287
+
288
+
ret = mpf_poll_status(priv, 0);
289
+
if (ret < 0)
290
+
return ret;
291
+
292
+
priv->tx = MPF_SPI_FRAME;
293
+
294
+
return spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers));
295
+
}
296
+
283
297
static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
284
298
{
285
-
u8 spi_frame_command[] = { MPF_SPI_FRAME };
286
-
struct spi_transfer xfers[2] = { 0 };
287
299
struct mpf_priv *priv = mgr->priv;
288
300
struct device *dev = &mgr->dev;
289
-
struct spi_device *spi;
290
301
int ret, i;
291
302
292
303
if (count % MPF_SPI_FRAME_SIZE) {
···
314
287
return -EINVAL;
315
288
}
316
289
317
-
spi = priv->spi;
318
-
319
-
xfers[0].tx_buf = spi_frame_command;
320
-
xfers[0].len = sizeof(spi_frame_command);
321
-
322
290
for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
323
-
xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE;
324
-
xfers[1].len = MPF_SPI_FRAME_SIZE;
325
-
326
-
ret = mpf_poll_status(spi, 0);
327
-
if (ret >= 0)
328
-
ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers));
329
-
291
+
ret = mpf_spi_frame_write(priv, buf + i * MPF_SPI_FRAME_SIZE);
330
292
if (ret) {
331
293
dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
332
294
i, count / MPF_SPI_FRAME_SIZE);
···
333
317
const u8 release_command[] = { MPF_SPI_RELEASE };
334
318
struct mpf_priv *priv = mgr->priv;
335
319
struct device *dev = &mgr->dev;
336
-
struct spi_device *spi;
337
320
int ret;
338
321
339
-
spi = priv->spi;
340
-
341
-
ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command));
322
+
ret = mpf_spi_write(priv, isc_dis_command, sizeof(isc_dis_command));
342
323
if (ret) {
343
324
dev_err(dev, "Failed to disable ISC: %d\n", ret);
344
325
return ret;
···
343
330
344
331
usleep_range(1000, 2000);
345
332
346
-
ret = mpf_spi_write(spi, release_command, sizeof(release_command));
333
+
ret = mpf_spi_write(priv, release_command, sizeof(release_command));
347
334
if (ret) {
348
335
dev_err(dev, "Failed to exit program mode: %d\n", ret);
349
336
return ret;
+35
drivers/hwtracing/coresight/Kconfig
+35
drivers/hwtracing/coresight/Kconfig
···
201
201
202
202
To compile this driver as a module, choose M here: the module will be
203
203
called coresight-trbe.
204
+
205
+
config ULTRASOC_SMB
206
+
tristate "Ultrasoc system memory buffer drivers"
207
+
depends on ACPI || COMPILE_TEST
208
+
depends on ARM64 && CORESIGHT_LINKS_AND_SINKS
209
+
help
210
+
This driver provides support for the Ultrasoc system memory buffer (SMB).
211
+
SMB is responsible for receiving the trace data from Coresight ETM devices
212
+
and storing them to a system buffer.
213
+
214
+
To compile this driver as a module, choose M here: the module will be
215
+
called ultrasoc-smb.
216
+
217
+
config CORESIGHT_TPDM
218
+
tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver"
219
+
select CORESIGHT_LINKS_AND_SINKS
220
+
select CORESIGHT_TPDA
221
+
help
222
+
This driver provides support for configuring monitor. Monitors are
223
+
primarily responsible for data set collection and support the
224
+
ability to collect any permutation of data set types.
225
+
226
+
To compile this driver as a module, choose M here: the module will be
227
+
called coresight-tpdm.
228
+
229
+
config CORESIGHT_TPDA
230
+
tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver"
231
+
help
232
+
This driver provides support for configuring aggregator. This is
233
+
primarily useful for pulling the data sets from one or more
234
+
attached monitors and pushing the resultant data out. Multiple
235
+
monitors are connected on different input ports of TPDA.
236
+
237
+
To compile this driver as a module, choose M here: the module will be
238
+
called coresight-tpda.
204
239
endif
+4
-1
drivers/hwtracing/coresight/Makefile
+4
-1
drivers/hwtracing/coresight/Makefile
···
6
6
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7
7
coresight-sysfs.o coresight-syscfg.o coresight-config.o \
8
8
coresight-cfg-preload.o coresight-cfg-afdo.o \
9
-
coresight-syscfg-configfs.o
9
+
coresight-syscfg-configfs.o coresight-trace-id.o
10
10
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
11
11
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
12
12
coresight-tmc-etr.o
···
25
25
obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
26
26
obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
27
27
obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
28
+
obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
29
+
obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o
28
30
coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
29
31
coresight-cti-sysfs.o
32
+
obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
+30
-57
drivers/hwtracing/coresight/coresight-core.c
+30
-57
drivers/hwtracing/coresight/coresight-core.c
···
8
8
#include <linux/types.h>
9
9
#include <linux/device.h>
10
10
#include <linux/io.h>
11
+
#include <linux/idr.h>
11
12
#include <linux/err.h>
12
13
#include <linux/export.h>
13
14
#include <linux/slab.h>
···
27
26
static DEFINE_MUTEX(coresight_mutex);
28
27
static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
29
28
29
+
/*
30
+
* Use IDR to map the hash of the source's device name
31
+
* to the pointer of path for the source. The idr is for
32
+
* the sources which aren't associated with CPU.
33
+
*/
34
+
static DEFINE_IDR(path_idr);
35
+
30
36
/**
31
37
* struct coresight_node - elements of a path, from source to sink
32
38
* @csdev: Address of an element.
···
49
41
* path can exist from a tracer (associated to a CPU) to a sink.
50
42
*/
51
43
static DEFINE_PER_CPU(struct list_head *, tracer_path);
52
-
53
-
/*
54
-
* As of this writing only a single STM can be found in CS topologies. Since
55
-
* there is no way to know if we'll ever see more and what kind of
56
-
* configuration they will enact, for the time being only define a single path
57
-
* for STM.
58
-
*/
59
-
static struct list_head *stm_path;
60
44
61
45
/*
62
46
* When losing synchronisation a new barrier packet needs to be inserted at the
···
111
111
return per_cpu(csdev_sink, cpu);
112
112
}
113
113
EXPORT_SYMBOL_GPL(coresight_get_percpu_sink);
114
-
115
-
static int coresight_id_match(struct device *dev, void *data)
116
-
{
117
-
int trace_id, i_trace_id;
118
-
struct coresight_device *csdev, *i_csdev;
119
-
120
-
csdev = data;
121
-
i_csdev = to_coresight_device(dev);
122
-
123
-
/*
124
-
* No need to care about oneself and components that are not
125
-
* sources or not enabled
126
-
*/
127
-
if (i_csdev == csdev || !i_csdev->enable ||
128
-
i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE)
129
-
return 0;
130
-
131
-
/* Get the source ID for both components */
132
-
trace_id = source_ops(csdev)->trace_id(csdev);
133
-
i_trace_id = source_ops(i_csdev)->trace_id(i_csdev);
134
-
135
-
/* All you need is one */
136
-
if (trace_id == i_trace_id)
137
-
return 1;
138
-
139
-
return 0;
140
-
}
141
-
142
-
static int coresight_source_is_unique(struct coresight_device *csdev)
143
-
{
144
-
int trace_id = source_ops(csdev)->trace_id(csdev);
145
-
146
-
/* this shouldn't happen */
147
-
if (trace_id < 0)
148
-
return 0;
149
-
150
-
return !bus_for_each_dev(&coresight_bustype, NULL,
151
-
csdev, coresight_id_match);
152
-
}
153
114
154
115
static int coresight_find_link_inport(struct coresight_device *csdev,
155
116
struct coresight_device *parent)
···
419
458
static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
420
459
{
421
460
int ret;
422
-
423
-
if (!coresight_source_is_unique(csdev)) {
424
-
dev_warn(&csdev->dev, "traceID %d not unique\n",
425
-
source_ops(csdev)->trace_id(csdev));
426
-
return -EINVAL;
427
-
}
428
461
429
462
if (!csdev->enable) {
430
463
if (source_ops(csdev)->enable) {
···
1061
1106
}
1062
1107
1063
1108
if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
1064
-
subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) {
1109
+
subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE &&
1110
+
subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) {
1065
1111
dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
1066
1112
return -EINVAL;
1067
1113
}
···
1076
1120
struct coresight_device *sink;
1077
1121
struct list_head *path;
1078
1122
enum coresight_dev_subtype_source subtype;
1123
+
u32 hash;
1079
1124
1080
1125
subtype = csdev->subtype.source_subtype;
1081
1126
···
1131
1174
per_cpu(tracer_path, cpu) = path;
1132
1175
break;
1133
1176
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
1134
-
stm_path = path;
1177
+
case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS:
1178
+
/*
1179
+
* Use the hash of source's device name as ID
1180
+
* and map the ID to the pointer of the path.
1181
+
*/
1182
+
hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
1183
+
ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL);
1184
+
if (ret)
1185
+
goto err_source;
1135
1186
break;
1136
1187
default:
1137
1188
/* We can't be here */
···
1163
1198
{
1164
1199
int cpu, ret;
1165
1200
struct list_head *path = NULL;
1201
+
u32 hash;
1166
1202
1167
1203
mutex_lock(&coresight_mutex);
1168
1204
···
1181
1215
per_cpu(tracer_path, cpu) = NULL;
1182
1216
break;
1183
1217
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
1184
-
path = stm_path;
1185
-
stm_path = NULL;
1218
+
case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS:
1219
+
hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
1220
+
/* Find the path by the hash. */
1221
+
path = idr_find(&path_idr, hash);
1222
+
if (path == NULL) {
1223
+
pr_err("Path is not found for %s\n", dev_name(&csdev->dev));
1224
+
goto out;
1225
+
}
1226
+
idr_remove(&path_idr, hash);
1186
1227
break;
1187
1228
default:
1188
1229
/* We can't be here */
+15
-8
drivers/hwtracing/coresight/coresight-cti-core.c
+15
-8
drivers/hwtracing/coresight/coresight-cti-core.c
···
107
107
cti_write_all_hw_regs(drvdata);
108
108
109
109
config->hw_enabled = true;
110
-
atomic_inc(&drvdata->config.enable_req_count);
110
+
drvdata->config.enable_req_count++;
111
111
spin_unlock_irqrestore(&drvdata->spinlock, flags);
112
112
return rc;
113
113
114
114
cti_state_unchanged:
115
-
atomic_inc(&drvdata->config.enable_req_count);
115
+
drvdata->config.enable_req_count++;
116
116
117
117
/* cannot enable due to error */
118
118
cti_err_not_enabled:
···
129
129
config->hw_powered = true;
130
130
131
131
/* no need to do anything if no enable request */
132
-
if (!atomic_read(&drvdata->config.enable_req_count))
132
+
if (!drvdata->config.enable_req_count)
133
133
goto cti_hp_not_enabled;
134
134
135
135
/* try to claim the device */
···
151
151
{
152
152
struct cti_config *config = &drvdata->config;
153
153
struct coresight_device *csdev = drvdata->csdev;
154
+
int ret = 0;
154
155
155
156
spin_lock(&drvdata->spinlock);
156
157
158
+
/* don't allow negative refcounts, return an error */
159
+
if (!drvdata->config.enable_req_count) {
160
+
ret = -EINVAL;
161
+
goto cti_not_disabled;
162
+
}
163
+
157
164
/* check refcount - disable on 0 */
158
-
if (atomic_dec_return(&drvdata->config.enable_req_count) > 0)
165
+
if (--drvdata->config.enable_req_count > 0)
159
166
goto cti_not_disabled;
160
167
161
168
/* no need to do anything if disabled or cpu unpowered */
···
178
171
coresight_disclaim_device_unlocked(csdev);
179
172
CS_LOCK(drvdata->base);
180
173
spin_unlock(&drvdata->spinlock);
181
-
return 0;
174
+
return ret;
182
175
183
176
/* not disabled this call */
184
177
cti_not_disabled:
185
178
spin_unlock(&drvdata->spinlock);
186
-
return 0;
179
+
return ret;
187
180
}
188
181
189
182
void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value)
···
239
232
/* Most regs default to 0 as zalloc'ed except...*/
240
233
config->trig_filter_enable = true;
241
234
config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0);
242
-
atomic_set(&config->enable_req_count, 0);
235
+
config->enable_req_count = 0;
243
236
}
244
237
245
238
/*
···
696
689
drvdata->config.hw_enabled = false;
697
690
698
691
/* check enable reference count to enable HW */
699
-
if (atomic_read(&drvdata->config.enable_req_count)) {
692
+
if (drvdata->config.enable_req_count) {
700
693
/* check we can claim the device as we re-power */
701
694
if (coresight_claim_device(csdev))
702
695
goto cti_notify_exit;
+12
-3
drivers/hwtracing/coresight/coresight-cti-sysfs.c
+12
-3
drivers/hwtracing/coresight/coresight-cti-sysfs.c
···
84
84
bool enabled, powered;
85
85
struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
86
86
87
-
enable_req = atomic_read(&drvdata->config.enable_req_count);
88
87
spin_lock(&drvdata->spinlock);
88
+
enable_req = drvdata->config.enable_req_count;
89
89
powered = drvdata->config.hw_powered;
90
90
enabled = drvdata->config.hw_enabled;
91
91
spin_unlock(&drvdata->spinlock);
···
108
108
if (ret)
109
109
return ret;
110
110
111
-
if (val)
111
+
if (val) {
112
+
ret = pm_runtime_resume_and_get(dev->parent);
113
+
if (ret)
114
+
return ret;
112
115
ret = cti_enable(drvdata->csdev);
113
-
else
116
+
if (ret)
117
+
pm_runtime_put(dev->parent);
118
+
} else {
114
119
ret = cti_disable(drvdata->csdev);
120
+
if (!ret)
121
+
pm_runtime_put(dev->parent);
122
+
}
123
+
115
124
if (ret)
116
125
return ret;
117
126
return size;
+1
-1
drivers/hwtracing/coresight/coresight-cti.h
+1
-1
drivers/hwtracing/coresight/coresight-cti.h
+31
drivers/hwtracing/coresight/coresight-etm-perf.c
+31
drivers/hwtracing/coresight/coresight-etm-perf.c
···
4
4
* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5
5
*/
6
6
7
+
#include <linux/bitfield.h>
7
8
#include <linux/coresight.h>
8
9
#include <linux/coresight-pmu.h>
9
10
#include <linux/cpumask.h>
···
23
22
#include "coresight-etm-perf.h"
24
23
#include "coresight-priv.h"
25
24
#include "coresight-syscfg.h"
25
+
#include "coresight-trace-id.h"
26
26
27
27
static struct pmu etm_pmu;
28
28
static bool etm_perf_up;
···
230
228
if (!(IS_ERR_OR_NULL(*ppath)))
231
229
coresight_release_path(*ppath);
232
230
*ppath = NULL;
231
+
coresight_trace_id_put_cpu_id(cpu);
233
232
}
233
+
234
+
/* mark perf event as done for trace id allocator */
235
+
coresight_trace_id_perf_stop();
234
236
235
237
free_percpu(event_data->path);
236
238
kfree(event_data);
···
306
300
{
307
301
u32 id, cfg_hash;
308
302
int cpu = event->cpu;
303
+
int trace_id;
309
304
cpumask_t *mask;
310
305
struct coresight_device *sink = NULL;
311
306
struct coresight_device *user_sink = NULL, *last_sink = NULL;
···
322
315
id = (u32)event->attr.config2;
323
316
sink = user_sink = coresight_get_sink_by_id(id);
324
317
}
318
+
319
+
/* tell the trace ID allocator that a perf event is starting up */
320
+
coresight_trace_id_perf_start();
325
321
326
322
/* check if user wants a coresight configuration selected */
327
323
cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32);
···
398
388
continue;
399
389
}
400
390
391
+
/* ensure we can allocate a trace ID for this CPU */
392
+
trace_id = coresight_trace_id_get_cpu_id(cpu);
393
+
if (!IS_VALID_CS_TRACE_ID(trace_id)) {
394
+
cpumask_clear_cpu(cpu, mask);
395
+
continue;
396
+
}
397
+
401
398
*etm_event_cpu_path_ptr(event_data, cpu) = path;
402
399
}
403
400
···
449
432
struct perf_output_handle *handle = &ctxt->handle;
450
433
struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
451
434
struct list_head *path;
435
+
u64 hw_id;
452
436
453
437
if (!csdev)
454
438
goto fail;
···
494
476
/* Finally enable the tracer */
495
477
if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
496
478
goto fail_disable_path;
479
+
480
+
/*
481
+
* output cpu / trace ID in perf record, once for the lifetime
482
+
* of the event.
483
+
*/
484
+
if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) {
485
+
cpumask_set_cpu(cpu, &event_data->aux_hwid_done);
486
+
hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK,
487
+
CS_AUX_HW_ID_CURR_VERSION);
488
+
hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK,
489
+
coresight_trace_id_read_cpu_id(cpu));
490
+
perf_report_aux_output_id(event, hw_id);
491
+
}
497
492
498
493
out:
499
494
/* Tell the perf core the event is alive */
+2
drivers/hwtracing/coresight/coresight-etm-perf.h
+2
drivers/hwtracing/coresight/coresight-etm-perf.h
···
48
48
* struct etm_event_data - Coresight specifics associated to an event
49
49
* @work: Handle to free allocated memory outside IRQ context.
50
50
* @mask: Hold the CPU(s) this event was set for.
51
+
* @aux_hwid_done: Whether a CPU has emitted the TraceID packet or not.
51
52
* @snk_config: The sink configuration.
52
53
* @cfg_hash: The hash id of any coresight config selected.
53
54
* @path: An array of path, each slot for one CPU.
···
56
55
struct etm_event_data {
57
56
struct work_struct work;
58
57
cpumask_t mask;
58
+
cpumask_t aux_hwid_done;
59
59
void *snk_config;
60
60
u32 cfg_hash;
61
61
struct list_head * __percpu *path;
+2
-1
drivers/hwtracing/coresight/coresight-etm.h
+2
-1
drivers/hwtracing/coresight/coresight-etm.h
···
283
283
}
284
284
285
285
extern const struct attribute_group *coresight_etm_groups[];
286
-
int etm_get_trace_id(struct etm_drvdata *drvdata);
287
286
void etm_set_default(struct etm_config *config);
288
287
void etm_config_trace_mode(struct etm_config *config);
289
288
struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
289
+
int etm_read_alloc_trace_id(struct etm_drvdata *drvdata);
290
+
void etm_release_trace_id(struct etm_drvdata *drvdata);
290
291
#endif
+58
-35
drivers/hwtracing/coresight/coresight-etm3x-core.c
+58
-35
drivers/hwtracing/coresight/coresight-etm3x-core.c
···
32
32
33
33
#include "coresight-etm.h"
34
34
#include "coresight-etm-perf.h"
35
+
#include "coresight-trace-id.h"
35
36
36
37
/*
37
38
* Not really modular but using module_param is the easiest way to
···
455
454
return drvdata->cpu;
456
455
}
457
456
458
-
int etm_get_trace_id(struct etm_drvdata *drvdata)
457
+
int etm_read_alloc_trace_id(struct etm_drvdata *drvdata)
459
458
{
460
-
unsigned long flags;
461
-
int trace_id = -1;
462
-
struct device *etm_dev;
459
+
int trace_id;
463
460
464
-
if (!drvdata)
465
-
goto out;
466
-
467
-
etm_dev = drvdata->csdev->dev.parent;
468
-
if (!local_read(&drvdata->mode))
469
-
return drvdata->traceid;
470
-
471
-
pm_runtime_get_sync(etm_dev);
472
-
473
-
spin_lock_irqsave(&drvdata->spinlock, flags);
474
-
475
-
CS_UNLOCK(drvdata->base);
476
-
trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
477
-
CS_LOCK(drvdata->base);
478
-
479
-
spin_unlock_irqrestore(&drvdata->spinlock, flags);
480
-
pm_runtime_put(etm_dev);
481
-
482
-
out:
461
+
/*
462
+
* This will allocate a trace ID to the cpu,
463
+
* or return the one currently allocated.
464
+
*
465
+
* trace id function has its own lock
466
+
*/
467
+
trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
468
+
if (IS_VALID_CS_TRACE_ID(trace_id))
469
+
drvdata->traceid = (u8)trace_id;
470
+
else
471
+
dev_err(&drvdata->csdev->dev,
472
+
"Failed to allocate trace ID for %s on CPU%d\n",
473
+
dev_name(&drvdata->csdev->dev), drvdata->cpu);
483
474
return trace_id;
484
-
485
475
}
486
476
487
-
static int etm_trace_id(struct coresight_device *csdev)
477
+
void etm_release_trace_id(struct etm_drvdata *drvdata)
488
478
{
489
-
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
490
-
491
-
return etm_get_trace_id(drvdata);
479
+
coresight_trace_id_put_cpu_id(drvdata->cpu);
492
480
}
493
481
494
482
static int etm_enable_perf(struct coresight_device *csdev,
495
483
struct perf_event *event)
496
484
{
497
485
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
486
+
int trace_id;
498
487
499
488
if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
500
489
return -EINVAL;
501
490
502
491
/* Configure the tracer based on the session's specifics */
503
492
etm_parse_event_config(drvdata, event);
493
+
494
+
/*
495
+
* perf allocates cpu ids as part of _setup_aux() - device needs to use
496
+
* the allocated ID. This reads the current version without allocation.
497
+
*
498
+
* This does not use the trace id lock to prevent lock_dep issues
499
+
* with perf locks - we know the ID cannot change until perf shuts down
500
+
* the session
501
+
*/
502
+
trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu);
503
+
if (!IS_VALID_CS_TRACE_ID(trace_id)) {
504
+
dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
505
+
dev_name(&drvdata->csdev->dev), drvdata->cpu);
506
+
return -EINVAL;
507
+
}
508
+
drvdata->traceid = (u8)trace_id;
509
+
504
510
/* And enable it */
505
511
return etm_enable_hw(drvdata);
506
512
}
···
519
511
int ret;
520
512
521
513
spin_lock(&drvdata->spinlock);
514
+
515
+
/* sysfs needs to allocate and set a trace ID */
516
+
ret = etm_read_alloc_trace_id(drvdata);
517
+
if (ret < 0)
518
+
goto unlock_enable_sysfs;
522
519
523
520
/*
524
521
* Configure the ETM only if the CPU is online. If it isn't online
···
541
528
ret = -ENODEV;
542
529
}
543
530
531
+
if (ret)
532
+
etm_release_trace_id(drvdata);
533
+
534
+
unlock_enable_sysfs:
544
535
spin_unlock(&drvdata->spinlock);
545
536
546
537
if (!ret)
···
628
611
coresight_disclaim_device_unlocked(csdev);
629
612
630
613
CS_LOCK(drvdata->base);
614
+
615
+
/*
616
+
* perf will release trace ids when _free_aux()
617
+
* is called at the end of the session
618
+
*/
619
+
631
620
}
632
621
633
622
static void etm_disable_sysfs(struct coresight_device *csdev)
···
657
634
658
635
spin_unlock(&drvdata->spinlock);
659
636
cpus_read_unlock();
637
+
638
+
/*
639
+
* we only release trace IDs when resetting sysfs.
640
+
* This permits sysfs users to read the trace ID after the trace
641
+
* session has completed. This maintains operational behaviour with
642
+
* prior trace id allocation method
643
+
*/
660
644
661
645
dev_dbg(&csdev->dev, "ETM tracing disabled\n");
662
646
}
···
701
671
702
672
static const struct coresight_ops_source etm_source_ops = {
703
673
.cpu_id = etm_cpu_id,
704
-
.trace_id = etm_trace_id,
705
674
.enable = etm_enable,
706
675
.disable = etm_disable,
707
676
};
···
810
781
CS_LOCK(drvdata->base);
811
782
}
812
783
813
-
static void etm_init_trace_id(struct etm_drvdata *drvdata)
814
-
{
815
-
drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
816
-
}
817
-
818
784
static int __init etm_hp_setup(void)
819
785
{
820
786
int ret;
···
895
871
if (etm_arch_supported(drvdata->arch) == false)
896
872
return -EINVAL;
897
873
898
-
etm_init_trace_id(drvdata);
899
874
etm_set_default(&drvdata->config);
900
875
901
876
pdata = coresight_get_platform_data(dev);
+7
-20
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+7
-20
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
···
85
85
}
86
86
87
87
etm_set_default(config);
88
+
etm_release_trace_id(drvdata);
88
89
spin_unlock(&drvdata->spinlock);
89
90
}
90
91
···
1190
1189
static ssize_t traceid_show(struct device *dev,
1191
1190
struct device_attribute *attr, char *buf)
1192
1191
{
1193
-
unsigned long val;
1192
+
int trace_id;
1194
1193
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1195
1194
1196
-
val = etm_get_trace_id(drvdata);
1195
+
trace_id = etm_read_alloc_trace_id(drvdata);
1196
+
if (trace_id < 0)
1197
+
return trace_id;
1197
1198
1198
-
return sprintf(buf, "%#lx\n", val);
1199
+
return sysfs_emit(buf, "%#x\n", trace_id);
1199
1200
}
1200
-
1201
-
static ssize_t traceid_store(struct device *dev,
1202
-
struct device_attribute *attr,
1203
-
const char *buf, size_t size)
1204
-
{
1205
-
int ret;
1206
-
unsigned long val;
1207
-
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1208
-
1209
-
ret = kstrtoul(buf, 16, &val);
1210
-
if (ret)
1211
-
return ret;
1212
-
1213
-
drvdata->traceid = val & ETM_TRACEID_MASK;
1214
-
return size;
1215
-
}
1216
-
static DEVICE_ATTR_RW(traceid);
1201
+
static DEVICE_ATTR_RO(traceid);
1217
1202
1218
1203
static struct attribute *coresight_etm_attrs[] = {
1219
1204
&dev_attr_nr_addr_cmp.attr,
+74
-17
drivers/hwtracing/coresight/coresight-etm4x-core.c
+74
-17
drivers/hwtracing/coresight/coresight-etm4x-core.c
···
42
42
#include "coresight-etm4x-cfg.h"
43
43
#include "coresight-self-hosted-trace.h"
44
44
#include "coresight-syscfg.h"
45
+
#include "coresight-trace-id.h"
45
46
46
47
static int boot_enable;
47
48
module_param(boot_enable, int, 0444);
···
231
230
return drvdata->cpu;
232
231
}
233
232
234
-
static int etm4_trace_id(struct coresight_device *csdev)
233
+
int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
235
234
{
236
-
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
235
+
int trace_id;
237
236
238
-
return drvdata->trcid;
237
+
/*
238
+
* This will allocate a trace ID to the cpu,
239
+
* or return the one currently allocated.
240
+
* The trace id function has its own lock
241
+
*/
242
+
trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
243
+
if (IS_VALID_CS_TRACE_ID(trace_id))
244
+
drvdata->trcid = (u8)trace_id;
245
+
else
246
+
dev_err(&drvdata->csdev->dev,
247
+
"Failed to allocate trace ID for %s on CPU%d\n",
248
+
dev_name(&drvdata->csdev->dev), drvdata->cpu);
249
+
return trace_id;
250
+
}
251
+
252
+
void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
253
+
{
254
+
coresight_trace_id_put_cpu_id(drvdata->cpu);
239
255
}
240
256
241
257
struct etm4_enable_arg {
···
445
427
etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
446
428
for (i = 0; i < drvdata->nrseqstate - 1; i++)
447
429
etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
448
-
etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
449
-
etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
430
+
if (drvdata->nrseqstate) {
431
+
etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
432
+
etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
433
+
}
450
434
etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
451
435
for (i = 0; i < drvdata->nr_cntr; i++) {
452
436
etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
···
740
720
static int etm4_enable_perf(struct coresight_device *csdev,
741
721
struct perf_event *event)
742
722
{
743
-
int ret = 0;
723
+
int ret = 0, trace_id;
744
724
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
745
725
746
726
if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
···
752
732
ret = etm4_parse_event_config(csdev, event);
753
733
if (ret)
754
734
goto out;
735
+
736
+
/*
737
+
* perf allocates cpu ids as part of _setup_aux() - device needs to use
738
+
* the allocated ID. This reads the current version without allocation.
739
+
*
740
+
* This does not use the trace id lock to prevent lock_dep issues
741
+
* with perf locks - we know the ID cannot change until perf shuts down
742
+
* the session
743
+
*/
744
+
trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu);
745
+
if (!IS_VALID_CS_TRACE_ID(trace_id)) {
746
+
dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
747
+
dev_name(&drvdata->csdev->dev), drvdata->cpu);
748
+
ret = -EINVAL;
749
+
goto out;
750
+
}
751
+
drvdata->trcid = (u8)trace_id;
752
+
755
753
/* And enable it */
756
754
ret = etm4_enable_hw(drvdata);
757
755
···
794
756
795
757
spin_lock(&drvdata->spinlock);
796
758
759
+
/* sysfs needs to read and allocate a trace ID */
760
+
ret = etm4_read_alloc_trace_id(drvdata);
761
+
if (ret < 0)
762
+
goto unlock_sysfs_enable;
763
+
797
764
/*
798
765
* Executing etm4_enable_hw on the cpu whose ETM is being enabled
799
766
* ensures that register writes occur when cpu is powered.
···
810
767
ret = arg.rc;
811
768
if (!ret)
812
769
drvdata->sticky_enable = true;
770
+
771
+
if (ret)
772
+
etm4_release_trace_id(drvdata);
773
+
774
+
unlock_sysfs_enable:
813
775
spin_unlock(&drvdata->spinlock);
814
776
815
777
if (!ret)
···
946
898
/* TRCVICTLR::SSSTATUS, bit[9] */
947
899
filters->ssstatus = (control & BIT(9));
948
900
901
+
/*
902
+
* perf will release trace ids when _free_aux() is
903
+
* called at the end of the session.
904
+
*/
905
+
949
906
return 0;
950
907
}
951
908
···
975
922
976
923
spin_unlock(&drvdata->spinlock);
977
924
cpus_read_unlock();
925
+
926
+
/*
927
+
* we only release trace IDs when resetting sysfs.
928
+
* This permits sysfs users to read the trace ID after the trace
929
+
* session has completed. This maintains operational behaviour with
930
+
* prior trace id allocation method
931
+
*/
978
932
979
933
dev_dbg(&csdev->dev, "ETM tracing disabled\n");
980
934
}
···
1016
956
1017
957
static const struct coresight_ops_source etm4_source_ops = {
1018
958
.cpu_id = etm4_cpu_id,
1019
-
.trace_id = etm4_trace_id,
1020
959
.enable = etm4_enable,
1021
960
.disable = etm4_disable,
1022
961
};
···
1624
1565
return 0;
1625
1566
}
1626
1567
1627
-
static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1628
-
{
1629
-
drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1630
-
}
1631
-
1632
1568
static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1633
1569
{
1634
1570
int i, ret = 0;
···
1688
1634
for (i = 0; i < drvdata->nrseqstate - 1; i++)
1689
1635
state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1690
1636
1691
-
state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1692
-
state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1637
+
if (drvdata->nrseqstate) {
1638
+
state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1639
+
state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1640
+
}
1693
1641
state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1694
1642
1695
1643
for (i = 0; i < drvdata->nr_cntr; i++) {
···
1819
1763
for (i = 0; i < drvdata->nrseqstate - 1; i++)
1820
1764
etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1821
1765
1822
-
etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1823
-
etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1766
+
if (drvdata->nrseqstate) {
1767
+
etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1768
+
etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1769
+
}
1824
1770
etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1825
1771
1826
1772
for (i = 0; i < drvdata->nr_cntr; i++) {
···
2004
1946
if (!desc.name)
2005
1947
return -ENOMEM;
2006
1948
2007
-
etm4_init_trace_id(drvdata);
2008
1949
etm4_set_default(&drvdata->config);
2009
1950
2010
1951
pdata = coresight_get_platform_data(dev);
+24
-3
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+24
-3
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
···
266
266
config->vmid_mask0 = 0x0;
267
267
config->vmid_mask1 = 0x0;
268
268
269
-
drvdata->trcid = drvdata->cpu + 1;
270
-
271
269
spin_unlock(&drvdata->spinlock);
270
+
271
+
/* for sysfs - only release trace id when resetting */
272
+
etm4_release_trace_id(drvdata);
272
273
273
274
cscfg_csdev_reset_feats(to_coresight_device(dev));
274
275
···
2393
2392
NULL,
2394
2393
};
2395
2394
2395
+
/*
2396
+
* Trace ID allocated dynamically on enable - but also allocate on read
2397
+
* in case sysfs or perf read before enable to ensure consistent metadata
2398
+
* information for trace decode
2399
+
*/
2400
+
static ssize_t trctraceid_show(struct device *dev,
2401
+
struct device_attribute *attr,
2402
+
char *buf)
2403
+
{
2404
+
int trace_id;
2405
+
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
2406
+
2407
+
trace_id = etm4_read_alloc_trace_id(drvdata);
2408
+
if (trace_id < 0)
2409
+
return trace_id;
2410
+
2411
+
return sysfs_emit(buf, "0x%x\n", trace_id);
2412
+
}
2413
+
static DEVICE_ATTR_RO(trctraceid);
2414
+
2396
2415
struct etmv4_reg {
2397
2416
struct coresight_device *csdev;
2398
2417
u32 offset;
···
2549
2528
coresight_etm4x_reg(trcpidr3, TRCPIDR3),
2550
2529
coresight_etm4x_reg(trcoslsr, TRCOSLSR),
2551
2530
coresight_etm4x_reg(trcconfig, TRCCONFIGR),
2552
-
coresight_etm4x_reg(trctraceid, TRCTRACEIDR),
2531
+
&dev_attr_trctraceid.attr,
2553
2532
coresight_etm4x_reg(trcdevarch, TRCDEVARCH),
2554
2533
NULL,
2555
2534
};
+3
drivers/hwtracing/coresight/coresight-etm4x.h
+3
drivers/hwtracing/coresight/coresight-etm4x.h
+14
-35
drivers/hwtracing/coresight/coresight-stm.c
+14
-35
drivers/hwtracing/coresight/coresight-stm.c
···
31
31
#include <linux/stm.h>
32
32
33
33
#include "coresight-priv.h"
34
+
#include "coresight-trace-id.h"
34
35
35
36
#define STMDMASTARTR 0xc04
36
37
#define STMDMASTOPR 0xc08
···
281
280
}
282
281
}
283
282
284
-
static int stm_trace_id(struct coresight_device *csdev)
285
-
{
286
-
struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
287
-
288
-
return drvdata->traceid;
289
-
}
290
-
291
283
static const struct coresight_ops_source stm_source_ops = {
292
-
.trace_id = stm_trace_id,
293
284
.enable = stm_enable,
294
285
.disable = stm_disable,
295
286
};
···
608
615
val = drvdata->traceid;
609
616
return sprintf(buf, "%#lx\n", val);
610
617
}
611
-
612
-
static ssize_t traceid_store(struct device *dev,
613
-
struct device_attribute *attr,
614
-
const char *buf, size_t size)
615
-
{
616
-
int ret;
617
-
unsigned long val;
618
-
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
619
-
620
-
ret = kstrtoul(buf, 16, &val);
621
-
if (ret)
622
-
return ret;
623
-
624
-
/* traceid field is 7bit wide on STM32 */
625
-
drvdata->traceid = val & 0x7f;
626
-
return size;
627
-
}
628
-
static DEVICE_ATTR_RW(traceid);
618
+
static DEVICE_ATTR_RO(traceid);
629
619
630
620
static struct attribute *coresight_stm_attrs[] = {
631
621
&dev_attr_hwevent_enable.attr,
···
779
803
*/
780
804
drvdata->stmsper = ~0x0;
781
805
782
-
/*
783
-
* The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
784
-
* anything equal to or higher than 0x70 is reserved. Since 0x00 is
785
-
* also reserved the STM trace ID needs to be higher than 0x00 and
786
-
* lowner than 0x10.
787
-
*/
788
-
drvdata->traceid = 0x1;
789
-
790
806
/* Set invariant transaction timing on all channels */
791
807
bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
792
808
}
···
806
838
807
839
static int stm_probe(struct amba_device *adev, const struct amba_id *id)
808
840
{
809
-
int ret;
841
+
int ret, trace_id;
810
842
void __iomem *base;
811
843
struct device *dev = &adev->dev;
812
844
struct coresight_platform_data *pdata = NULL;
···
890
922
goto stm_unregister;
891
923
}
892
924
925
+
trace_id = coresight_trace_id_get_system_id();
926
+
if (trace_id < 0) {
927
+
ret = trace_id;
928
+
goto cs_unregister;
929
+
}
930
+
drvdata->traceid = (u8)trace_id;
931
+
893
932
pm_runtime_put(&adev->dev);
894
933
895
934
dev_info(&drvdata->csdev->dev, "%s initialized\n",
896
935
(char *)coresight_get_uci_data(id));
897
936
return 0;
937
+
938
+
cs_unregister:
939
+
coresight_unregister(drvdata->csdev);
898
940
899
941
stm_unregister:
900
942
stm_unregister_device(&drvdata->stm);
···
915
937
{
916
938
struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
917
939
940
+
coresight_trace_id_put_system_id(drvdata->traceid);
918
941
coresight_unregister(drvdata->csdev);
919
942
920
943
stm_unregister_device(&drvdata->stm);
+3
-1
drivers/hwtracing/coresight/coresight-tmc-core.c
+3
-1
drivers/hwtracing/coresight/coresight-tmc-core.c
···
31
31
DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf");
32
32
DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
33
33
34
-
void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
34
+
int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
35
35
{
36
36
struct coresight_device *csdev = drvdata->csdev;
37
37
struct csdev_access *csa = &csdev->access;
···
40
40
if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
41
41
dev_err(&csdev->dev,
42
42
"timeout while waiting for TMC to be Ready\n");
43
+
return -EBUSY;
43
44
}
45
+
return 0;
44
46
}
45
47
46
48
void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
+36
-9
drivers/hwtracing/coresight/coresight-tmc-etf.c
+36
-9
drivers/hwtracing/coresight/coresight-tmc-etf.c
···
16
16
static int tmc_set_etf_buffer(struct coresight_device *csdev,
17
17
struct perf_output_handle *handle);
18
18
19
-
static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
19
+
static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
20
20
{
21
+
int rc = 0;
22
+
21
23
CS_UNLOCK(drvdata->base);
22
24
23
25
/* Wait for TMCSReady bit to be set */
24
-
tmc_wait_for_tmcready(drvdata);
26
+
rc = tmc_wait_for_tmcready(drvdata);
27
+
if (rc) {
28
+
dev_err(&drvdata->csdev->dev,
29
+
"Failed to enable: TMC not ready\n");
30
+
CS_LOCK(drvdata->base);
31
+
return rc;
32
+
}
25
33
26
34
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
27
35
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
···
41
33
tmc_enable_hw(drvdata);
42
34
43
35
CS_LOCK(drvdata->base);
36
+
return rc;
44
37
}
45
38
46
39
static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
···
51
42
if (rc)
52
43
return rc;
53
44
54
-
__tmc_etb_enable_hw(drvdata);
55
-
return 0;
45
+
rc = __tmc_etb_enable_hw(drvdata);
46
+
if (rc)
47
+
coresight_disclaim_device(drvdata->csdev);
48
+
return rc;
56
49
}
57
50
58
51
static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
···
102
91
coresight_disclaim_device(drvdata->csdev);
103
92
}
104
93
105
-
static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
94
+
static int __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
106
95
{
96
+
int rc = 0;
97
+
107
98
CS_UNLOCK(drvdata->base);
108
99
109
100
/* Wait for TMCSReady bit to be set */
110
-
tmc_wait_for_tmcready(drvdata);
101
+
rc = tmc_wait_for_tmcready(drvdata);
102
+
if (rc) {
103
+
dev_err(&drvdata->csdev->dev,
104
+
"Failed to enable : TMC is not ready\n");
105
+
CS_LOCK(drvdata->base);
106
+
return rc;
107
+
}
111
108
112
109
writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
113
110
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
···
124
105
tmc_enable_hw(drvdata);
125
106
126
107
CS_LOCK(drvdata->base);
108
+
return rc;
127
109
}
128
110
129
111
static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
···
134
114
if (rc)
135
115
return rc;
136
116
137
-
__tmc_etf_enable_hw(drvdata);
138
-
return 0;
117
+
rc = __tmc_etf_enable_hw(drvdata);
118
+
if (rc)
119
+
coresight_disclaim_device(drvdata->csdev);
120
+
return rc;
139
121
}
140
122
141
123
static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
···
661
639
char *buf = NULL;
662
640
enum tmc_mode mode;
663
641
unsigned long flags;
642
+
int rc = 0;
664
643
665
644
/* config types are set a boot time and never change */
666
645
if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB &&
···
687
664
* can't be NULL.
688
665
*/
689
666
memset(drvdata->buf, 0, drvdata->size);
690
-
__tmc_etb_enable_hw(drvdata);
667
+
rc = __tmc_etb_enable_hw(drvdata);
668
+
if (rc) {
669
+
spin_unlock_irqrestore(&drvdata->spinlock, flags);
670
+
return rc;
671
+
}
691
672
} else {
692
673
/*
693
674
* The ETB/ETF is not tracing and the buffer was just read.
+16
-3
drivers/hwtracing/coresight/coresight-tmc-etr.c
+16
-3
drivers/hwtracing/coresight/coresight-tmc-etr.c
···
983
983
etr_buf->ops->sync(etr_buf, rrp, rwp);
984
984
}
985
985
986
-
static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
986
+
static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
987
987
{
988
988
u32 axictl, sts;
989
989
struct etr_buf *etr_buf = drvdata->etr_buf;
990
+
int rc = 0;
990
991
991
992
CS_UNLOCK(drvdata->base);
992
993
993
994
/* Wait for TMCSReady bit to be set */
994
-
tmc_wait_for_tmcready(drvdata);
995
+
rc = tmc_wait_for_tmcready(drvdata);
996
+
if (rc) {
997
+
dev_err(&drvdata->csdev->dev,
998
+
"Failed to enable : TMC not ready\n");
999
+
CS_LOCK(drvdata->base);
1000
+
return rc;
1001
+
}
995
1002
996
1003
writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ);
997
1004
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
···
1039
1032
tmc_enable_hw(drvdata);
1040
1033
1041
1034
CS_LOCK(drvdata->base);
1035
+
return rc;
1042
1036
}
1043
1037
1044
1038
static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
···
1068
1060
rc = coresight_claim_device(drvdata->csdev);
1069
1061
if (!rc) {
1070
1062
drvdata->etr_buf = etr_buf;
1071
-
__tmc_etr_enable_hw(drvdata);
1063
+
rc = __tmc_etr_enable_hw(drvdata);
1064
+
if (rc) {
1065
+
drvdata->etr_buf = NULL;
1066
+
coresight_disclaim_device(drvdata->csdev);
1067
+
tmc_etr_disable_catu(drvdata);
1068
+
}
1072
1069
}
1073
1070
1074
1071
return rc;
+1
-1
drivers/hwtracing/coresight/coresight-tmc.h
+1
-1
drivers/hwtracing/coresight/coresight-tmc.h
···
255
255
};
256
256
257
257
/* Generic functions */
258
-
void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
258
+
int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
259
259
void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
260
260
void tmc_enable_hw(struct tmc_drvdata *drvdata);
261
261
void tmc_disable_hw(struct tmc_drvdata *drvdata);
+211
drivers/hwtracing/coresight/coresight-tpda.c
+211
drivers/hwtracing/coresight/coresight-tpda.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/amba/bus.h>
7
+
#include <linux/bitfield.h>
8
+
#include <linux/coresight.h>
9
+
#include <linux/device.h>
10
+
#include <linux/err.h>
11
+
#include <linux/fs.h>
12
+
#include <linux/io.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of.h>
16
+
#include <linux/platform_device.h>
17
+
18
+
#include "coresight-priv.h"
19
+
#include "coresight-tpda.h"
20
+
#include "coresight-trace-id.h"
21
+
22
+
DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");
23
+
24
+
/* Settings pre enabling port control register */
25
+
static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
26
+
{
27
+
u32 val;
28
+
29
+
val = readl_relaxed(drvdata->base + TPDA_CR);
30
+
val &= ~TPDA_CR_ATID;
31
+
val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid);
32
+
writel_relaxed(val, drvdata->base + TPDA_CR);
33
+
}
34
+
35
+
static void tpda_enable_port(struct tpda_drvdata *drvdata, int port)
36
+
{
37
+
u32 val;
38
+
39
+
val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
40
+
/* Enable the port */
41
+
val |= TPDA_Pn_CR_ENA;
42
+
writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
43
+
}
44
+
45
+
static void __tpda_enable(struct tpda_drvdata *drvdata, int port)
46
+
{
47
+
CS_UNLOCK(drvdata->base);
48
+
49
+
if (!drvdata->csdev->enable)
50
+
tpda_enable_pre_port(drvdata);
51
+
52
+
tpda_enable_port(drvdata, port);
53
+
54
+
CS_LOCK(drvdata->base);
55
+
}
56
+
57
+
static int tpda_enable(struct coresight_device *csdev, int inport, int outport)
58
+
{
59
+
struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
60
+
61
+
spin_lock(&drvdata->spinlock);
62
+
if (atomic_read(&csdev->refcnt[inport]) == 0)
63
+
__tpda_enable(drvdata, inport);
64
+
65
+
atomic_inc(&csdev->refcnt[inport]);
66
+
spin_unlock(&drvdata->spinlock);
67
+
68
+
dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", inport);
69
+
return 0;
70
+
}
71
+
72
+
static void __tpda_disable(struct tpda_drvdata *drvdata, int port)
73
+
{
74
+
u32 val;
75
+
76
+
CS_UNLOCK(drvdata->base);
77
+
78
+
val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
79
+
val &= ~TPDA_Pn_CR_ENA;
80
+
writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
81
+
82
+
CS_LOCK(drvdata->base);
83
+
}
84
+
85
+
static void tpda_disable(struct coresight_device *csdev, int inport,
86
+
int outport)
87
+
{
88
+
struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
89
+
90
+
spin_lock(&drvdata->spinlock);
91
+
if (atomic_dec_return(&csdev->refcnt[inport]) == 0)
92
+
__tpda_disable(drvdata, inport);
93
+
94
+
spin_unlock(&drvdata->spinlock);
95
+
96
+
dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", inport);
97
+
}
98
+
99
+
static const struct coresight_ops_link tpda_link_ops = {
100
+
.enable = tpda_enable,
101
+
.disable = tpda_disable,
102
+
};
103
+
104
+
static const struct coresight_ops tpda_cs_ops = {
105
+
.link_ops = &tpda_link_ops,
106
+
};
107
+
108
+
static int tpda_init_default_data(struct tpda_drvdata *drvdata)
109
+
{
110
+
int atid;
111
+
/*
112
+
* TPDA must has a unique atid. This atid can uniquely
113
+
* identify the TPDM trace source connected to the TPDA.
114
+
* The TPDMs which are connected to same TPDA share the
115
+
* same trace-id. When TPDA does packetization, different
116
+
* port will have unique channel number for decoding.
117
+
*/
118
+
atid = coresight_trace_id_get_system_id();
119
+
if (atid < 0)
120
+
return atid;
121
+
122
+
drvdata->atid = atid;
123
+
return 0;
124
+
}
125
+
126
+
static int tpda_probe(struct amba_device *adev, const struct amba_id *id)
127
+
{
128
+
int ret;
129
+
struct device *dev = &adev->dev;
130
+
struct coresight_platform_data *pdata;
131
+
struct tpda_drvdata *drvdata;
132
+
struct coresight_desc desc = { 0 };
133
+
void __iomem *base;
134
+
135
+
pdata = coresight_get_platform_data(dev);
136
+
if (IS_ERR(pdata))
137
+
return PTR_ERR(pdata);
138
+
adev->dev.platform_data = pdata;
139
+
140
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
141
+
if (!drvdata)
142
+
return -ENOMEM;
143
+
144
+
drvdata->dev = &adev->dev;
145
+
dev_set_drvdata(dev, drvdata);
146
+
147
+
base = devm_ioremap_resource(dev, &adev->res);
148
+
if (IS_ERR(base))
149
+
return PTR_ERR(base);
150
+
drvdata->base = base;
151
+
152
+
spin_lock_init(&drvdata->spinlock);
153
+
154
+
ret = tpda_init_default_data(drvdata);
155
+
if (ret)
156
+
return ret;
157
+
158
+
desc.name = coresight_alloc_device_name(&tpda_devs, dev);
159
+
if (!desc.name)
160
+
return -ENOMEM;
161
+
desc.type = CORESIGHT_DEV_TYPE_LINK;
162
+
desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG;
163
+
desc.ops = &tpda_cs_ops;
164
+
desc.pdata = adev->dev.platform_data;
165
+
desc.dev = &adev->dev;
166
+
desc.access = CSDEV_ACCESS_IOMEM(base);
167
+
drvdata->csdev = coresight_register(&desc);
168
+
if (IS_ERR(drvdata->csdev))
169
+
return PTR_ERR(drvdata->csdev);
170
+
171
+
pm_runtime_put(&adev->dev);
172
+
173
+
dev_dbg(drvdata->dev, "TPDA initialized\n");
174
+
return 0;
175
+
}
176
+
177
+
static void tpda_remove(struct amba_device *adev)
178
+
{
179
+
struct tpda_drvdata *drvdata = dev_get_drvdata(&adev->dev);
180
+
181
+
coresight_trace_id_put_system_id(drvdata->atid);
182
+
coresight_unregister(drvdata->csdev);
183
+
}
184
+
185
+
/*
186
+
* Different TPDA has different periph id.
187
+
* The difference is 0-7 bits' value. So ignore 0-7 bits.
188
+
*/
189
+
static struct amba_id tpda_ids[] = {
190
+
{
191
+
.id = 0x000f0f00,
192
+
.mask = 0x000fff00,
193
+
},
194
+
{ 0, 0},
195
+
};
196
+
197
+
static struct amba_driver tpda_driver = {
198
+
.drv = {
199
+
.name = "coresight-tpda",
200
+
.owner = THIS_MODULE,
201
+
.suppress_bind_attrs = true,
202
+
},
203
+
.probe = tpda_probe,
204
+
.remove = tpda_remove,
205
+
.id_table = tpda_ids,
206
+
};
207
+
208
+
module_amba_driver(tpda_driver);
209
+
210
+
MODULE_LICENSE("GPL");
211
+
MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver");
+35
drivers/hwtracing/coresight/coresight-tpda.h
+35
drivers/hwtracing/coresight/coresight-tpda.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _CORESIGHT_CORESIGHT_TPDA_H
7
+
#define _CORESIGHT_CORESIGHT_TPDA_H
8
+
9
+
#define TPDA_CR (0x000)
10
+
#define TPDA_Pn_CR(n) (0x004 + (n * 4))
11
+
/* Aggregator port enable bit */
12
+
#define TPDA_Pn_CR_ENA BIT(0)
13
+
14
+
#define TPDA_MAX_INPORTS 32
15
+
16
+
/* Bits 6 ~ 12 is for atid value */
17
+
#define TPDA_CR_ATID GENMASK(12, 6)
18
+
19
+
/**
20
+
* struct tpda_drvdata - specifics associated to an TPDA component
21
+
* @base: memory mapped base address for this component.
22
+
* @dev: The device entity associated to this component.
23
+
* @csdev: component vitals needed by the framework.
24
+
* @spinlock: lock for the drvdata value.
25
+
* @enable: enable status of the component.
26
+
*/
27
+
struct tpda_drvdata {
28
+
void __iomem *base;
29
+
struct device *dev;
30
+
struct coresight_device *csdev;
31
+
spinlock_t spinlock;
32
+
u8 atid;
33
+
};
34
+
35
+
#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
+259
drivers/hwtracing/coresight/coresight-tpdm.c
+259
drivers/hwtracing/coresight/coresight-tpdm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/amba/bus.h>
7
+
#include <linux/bitmap.h>
8
+
#include <linux/coresight.h>
9
+
#include <linux/coresight-pmu.h>
10
+
#include <linux/device.h>
11
+
#include <linux/err.h>
12
+
#include <linux/fs.h>
13
+
#include <linux/io.h>
14
+
#include <linux/kernel.h>
15
+
#include <linux/module.h>
16
+
#include <linux/of.h>
17
+
18
+
#include "coresight-priv.h"
19
+
#include "coresight-tpdm.h"
20
+
21
+
DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
22
+
23
+
static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
24
+
{
25
+
u32 val;
26
+
27
+
/* Set the enable bit of DSB control register to 1 */
28
+
val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
29
+
val |= TPDM_DSB_CR_ENA;
30
+
writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
31
+
}
32
+
33
+
/* TPDM enable operations */
34
+
static void __tpdm_enable(struct tpdm_drvdata *drvdata)
35
+
{
36
+
CS_UNLOCK(drvdata->base);
37
+
38
+
/* Check if DSB datasets is present for TPDM. */
39
+
if (drvdata->datasets & TPDM_PIDR0_DS_DSB)
40
+
tpdm_enable_dsb(drvdata);
41
+
42
+
CS_LOCK(drvdata->base);
43
+
}
44
+
45
+
static int tpdm_enable(struct coresight_device *csdev,
46
+
struct perf_event *event, u32 mode)
47
+
{
48
+
struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
49
+
50
+
spin_lock(&drvdata->spinlock);
51
+
if (drvdata->enable) {
52
+
spin_unlock(&drvdata->spinlock);
53
+
return -EBUSY;
54
+
}
55
+
56
+
__tpdm_enable(drvdata);
57
+
drvdata->enable = true;
58
+
spin_unlock(&drvdata->spinlock);
59
+
60
+
dev_dbg(drvdata->dev, "TPDM tracing enabled\n");
61
+
return 0;
62
+
}
63
+
64
+
static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
65
+
{
66
+
u32 val;
67
+
68
+
/* Set the enable bit of DSB control register to 0 */
69
+
val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
70
+
val &= ~TPDM_DSB_CR_ENA;
71
+
writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
72
+
}
73
+
74
+
/* TPDM disable operations */
75
+
static void __tpdm_disable(struct tpdm_drvdata *drvdata)
76
+
{
77
+
CS_UNLOCK(drvdata->base);
78
+
79
+
/* Check if DSB datasets is present for TPDM. */
80
+
if (drvdata->datasets & TPDM_PIDR0_DS_DSB)
81
+
tpdm_disable_dsb(drvdata);
82
+
83
+
CS_LOCK(drvdata->base);
84
+
}
85
+
86
+
static void tpdm_disable(struct coresight_device *csdev,
87
+
struct perf_event *event)
88
+
{
89
+
struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
90
+
91
+
spin_lock(&drvdata->spinlock);
92
+
if (!drvdata->enable) {
93
+
spin_unlock(&drvdata->spinlock);
94
+
return;
95
+
}
96
+
97
+
__tpdm_disable(drvdata);
98
+
drvdata->enable = false;
99
+
spin_unlock(&drvdata->spinlock);
100
+
101
+
dev_dbg(drvdata->dev, "TPDM tracing disabled\n");
102
+
}
103
+
104
+
static const struct coresight_ops_source tpdm_source_ops = {
105
+
.enable = tpdm_enable,
106
+
.disable = tpdm_disable,
107
+
};
108
+
109
+
static const struct coresight_ops tpdm_cs_ops = {
110
+
.source_ops = &tpdm_source_ops,
111
+
};
112
+
113
+
static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
114
+
{
115
+
u32 pidr;
116
+
117
+
CS_UNLOCK(drvdata->base);
118
+
/* Get the datasets present on the TPDM. */
119
+
pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
120
+
drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0);
121
+
CS_LOCK(drvdata->base);
122
+
}
123
+
124
+
/*
125
+
* value 1: 64 bits test data
126
+
* value 2: 32 bits test data
127
+
*/
128
+
static ssize_t integration_test_store(struct device *dev,
129
+
struct device_attribute *attr,
130
+
const char *buf,
131
+
size_t size)
132
+
{
133
+
int i, ret = 0;
134
+
unsigned long val;
135
+
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
136
+
137
+
ret = kstrtoul(buf, 10, &val);
138
+
if (ret)
139
+
return ret;
140
+
141
+
if (val != 1 && val != 2)
142
+
return -EINVAL;
143
+
144
+
if (!drvdata->enable)
145
+
return -EINVAL;
146
+
147
+
if (val == 1)
148
+
val = ATBCNTRL_VAL_64;
149
+
else
150
+
val = ATBCNTRL_VAL_32;
151
+
CS_UNLOCK(drvdata->base);
152
+
writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
153
+
154
+
for (i = 0; i < INTEGRATION_TEST_CYCLE; i++)
155
+
writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
156
+
157
+
writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
158
+
CS_LOCK(drvdata->base);
159
+
return size;
160
+
}
161
+
static DEVICE_ATTR_WO(integration_test);
162
+
163
+
static struct attribute *tpdm_attrs[] = {
164
+
&dev_attr_integration_test.attr,
165
+
NULL,
166
+
};
167
+
168
+
static struct attribute_group tpdm_attr_grp = {
169
+
.attrs = tpdm_attrs,
170
+
};
171
+
172
+
static const struct attribute_group *tpdm_attr_grps[] = {
173
+
&tpdm_attr_grp,
174
+
NULL,
175
+
};
176
+
177
+
static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
178
+
{
179
+
void __iomem *base;
180
+
struct device *dev = &adev->dev;
181
+
struct coresight_platform_data *pdata;
182
+
struct tpdm_drvdata *drvdata;
183
+
struct coresight_desc desc = { 0 };
184
+
185
+
pdata = coresight_get_platform_data(dev);
186
+
if (IS_ERR(pdata))
187
+
return PTR_ERR(pdata);
188
+
adev->dev.platform_data = pdata;
189
+
190
+
/* driver data*/
191
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
192
+
if (!drvdata)
193
+
return -ENOMEM;
194
+
drvdata->dev = &adev->dev;
195
+
dev_set_drvdata(dev, drvdata);
196
+
197
+
base = devm_ioremap_resource(dev, &adev->res);
198
+
if (IS_ERR(base))
199
+
return PTR_ERR(base);
200
+
201
+
drvdata->base = base;
202
+
203
+
/* Set up coresight component description */
204
+
desc.name = coresight_alloc_device_name(&tpdm_devs, dev);
205
+
if (!desc.name)
206
+
return -ENOMEM;
207
+
desc.type = CORESIGHT_DEV_TYPE_SOURCE;
208
+
desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS;
209
+
desc.ops = &tpdm_cs_ops;
210
+
desc.pdata = adev->dev.platform_data;
211
+
desc.dev = &adev->dev;
212
+
desc.access = CSDEV_ACCESS_IOMEM(base);
213
+
desc.groups = tpdm_attr_grps;
214
+
drvdata->csdev = coresight_register(&desc);
215
+
if (IS_ERR(drvdata->csdev))
216
+
return PTR_ERR(drvdata->csdev);
217
+
218
+
spin_lock_init(&drvdata->spinlock);
219
+
tpdm_init_default_data(drvdata);
220
+
/* Decrease pm refcount when probe is done.*/
221
+
pm_runtime_put(&adev->dev);
222
+
223
+
return 0;
224
+
}
225
+
226
+
static void tpdm_remove(struct amba_device *adev)
227
+
{
228
+
struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
229
+
230
+
coresight_unregister(drvdata->csdev);
231
+
}
232
+
233
+
/*
234
+
* Different TPDM has different periph id.
235
+
* The difference is 0-7 bits' value. So ignore 0-7 bits.
236
+
*/
237
+
static struct amba_id tpdm_ids[] = {
238
+
{
239
+
.id = 0x000f0e00,
240
+
.mask = 0x000fff00,
241
+
},
242
+
{ 0, 0},
243
+
};
244
+
245
+
static struct amba_driver tpdm_driver = {
246
+
.drv = {
247
+
.name = "coresight-tpdm",
248
+
.owner = THIS_MODULE,
249
+
.suppress_bind_attrs = true,
250
+
},
251
+
.probe = tpdm_probe,
252
+
.id_table = tpdm_ids,
253
+
.remove = tpdm_remove,
254
+
};
255
+
256
+
module_amba_driver(tpdm_driver);
257
+
258
+
MODULE_LICENSE("GPL");
259
+
MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver");
+62
drivers/hwtracing/coresight/coresight-tpdm.h
+62
drivers/hwtracing/coresight/coresight-tpdm.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _CORESIGHT_CORESIGHT_TPDM_H
7
+
#define _CORESIGHT_CORESIGHT_TPDM_H
8
+
9
+
/* The max number of the datasets that TPDM supports */
10
+
#define TPDM_DATASETS 7
11
+
12
+
/* DSB Subunit Registers */
13
+
#define TPDM_DSB_CR (0x780)
14
+
/* Enable bit for DSB subunit */
15
+
#define TPDM_DSB_CR_ENA BIT(0)
16
+
17
+
/* TPDM integration test registers */
18
+
#define TPDM_ITATBCNTRL (0xEF0)
19
+
#define TPDM_ITCNTRL (0xF00)
20
+
21
+
/* Register value for integration test */
22
+
#define ATBCNTRL_VAL_32 0xC00F1409
23
+
#define ATBCNTRL_VAL_64 0xC01F1409
24
+
25
+
/*
26
+
* Number of cycles to write value when
27
+
* integration test.
28
+
*/
29
+
#define INTEGRATION_TEST_CYCLE 10
30
+
31
+
/**
32
+
* The bits of PERIPHIDR0 register.
33
+
* The fields [6:0] of PERIPHIDR0 are used to determine what
34
+
* interfaces and subunits are present on a given TPDM.
35
+
*
36
+
* PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
37
+
* PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
38
+
*/
39
+
40
+
#define TPDM_PIDR0_DS_IMPDEF BIT(0)
41
+
#define TPDM_PIDR0_DS_DSB BIT(1)
42
+
43
+
/**
44
+
* struct tpdm_drvdata - specifics associated to an TPDM component
45
+
* @base: memory mapped base address for this component.
46
+
* @dev: The device entity associated to this component.
47
+
* @csdev: component vitals needed by the framework.
48
+
* @spinlock: lock for the drvdata value.
49
+
* @enable: enable status of the component.
50
+
* @datasets: The datasets types present of the TPDM.
51
+
*/
52
+
53
+
struct tpdm_drvdata {
54
+
void __iomem *base;
55
+
struct device *dev;
56
+
struct coresight_device *csdev;
57
+
spinlock_t spinlock;
58
+
bool enable;
59
+
unsigned long datasets;
60
+
};
61
+
62
+
#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
+297
drivers/hwtracing/coresight/coresight-trace-id.c
+297
drivers/hwtracing/coresight/coresight-trace-id.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2022, Linaro Limited, All rights reserved.
4
+
* Author: Mike Leach <mike.leach@linaro.org>
5
+
*/
6
+
#include <linux/coresight-pmu.h>
7
+
#include <linux/cpumask.h>
8
+
#include <linux/kernel.h>
9
+
#include <linux/spinlock.h>
10
+
#include <linux/types.h>
11
+
12
+
#include "coresight-trace-id.h"
13
+
14
+
/* Default trace ID map. Used on systems that don't require per sink mappings */
15
+
static struct coresight_trace_id_map id_map_default;
16
+
17
+
/* maintain a record of the mapping of IDs and pending releases per cpu */
18
+
static DEFINE_PER_CPU(atomic_t, cpu_id) = ATOMIC_INIT(0);
19
+
static cpumask_t cpu_id_release_pending;
20
+
21
+
/* perf session active counter */
22
+
static atomic_t perf_cs_etm_session_active = ATOMIC_INIT(0);
23
+
24
+
/* lock to protect id_map and cpu data */
25
+
static DEFINE_SPINLOCK(id_map_lock);
26
+
27
+
/* #define TRACE_ID_DEBUG 1 */
28
+
#if defined(TRACE_ID_DEBUG) || defined(CONFIG_COMPILE_TEST)
29
+
30
+
static void coresight_trace_id_dump_table(struct coresight_trace_id_map *id_map,
31
+
const char *func_name)
32
+
{
33
+
pr_debug("%s id_map::\n", func_name);
34
+
pr_debug("Used = %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->used_ids);
35
+
pr_debug("Pend = %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->pend_rel_ids);
36
+
}
37
+
#define DUMP_ID_MAP(map) coresight_trace_id_dump_table(map, __func__)
38
+
#define DUMP_ID_CPU(cpu, id) pr_debug("%s called; cpu=%d, id=%d\n", __func__, cpu, id)
39
+
#define DUMP_ID(id) pr_debug("%s called; id=%d\n", __func__, id)
40
+
#define PERF_SESSION(n) pr_debug("%s perf count %d\n", __func__, n)
41
+
#else
42
+
#define DUMP_ID_MAP(map)
43
+
#define DUMP_ID(id)
44
+
#define DUMP_ID_CPU(cpu, id)
45
+
#define PERF_SESSION(n)
46
+
#endif
47
+
48
+
/* unlocked read of current trace ID value for given CPU */
49
+
static int _coresight_trace_id_read_cpu_id(int cpu)
50
+
{
51
+
return atomic_read(&per_cpu(cpu_id, cpu));
52
+
}
53
+
54
+
/* look for next available odd ID, return 0 if none found */
55
+
static int coresight_trace_id_find_odd_id(struct coresight_trace_id_map *id_map)
56
+
{
57
+
int found_id = 0, bit = 1, next_id;
58
+
59
+
while ((bit < CORESIGHT_TRACE_ID_RES_TOP) && !found_id) {
60
+
/*
61
+
* bitmap length of CORESIGHT_TRACE_ID_RES_TOP,
62
+
* search from offset `bit`.
63
+
*/
64
+
next_id = find_next_zero_bit(id_map->used_ids,
65
+
CORESIGHT_TRACE_ID_RES_TOP, bit);
66
+
if ((next_id < CORESIGHT_TRACE_ID_RES_TOP) && (next_id & 0x1))
67
+
found_id = next_id;
68
+
else
69
+
bit = next_id + 1;
70
+
}
71
+
return found_id;
72
+
}
73
+
74
+
/*
75
+
* Allocate new ID and set in use
76
+
*
77
+
* if @preferred_id is a valid id then try to use that value if available.
78
+
* if @preferred_id is not valid and @prefer_odd_id is true, try for odd id.
79
+
*
80
+
* Otherwise allocate next available ID.
81
+
*/
82
+
static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *id_map,
83
+
int preferred_id, bool prefer_odd_id)
84
+
{
85
+
int id = 0;
86
+
87
+
/* for backwards compatibility, cpu IDs may use preferred value */
88
+
if (IS_VALID_CS_TRACE_ID(preferred_id) &&
89
+
!test_bit(preferred_id, id_map->used_ids)) {
90
+
id = preferred_id;
91
+
goto trace_id_allocated;
92
+
} else if (prefer_odd_id) {
93
+
/* may use odd ids to avoid preferred legacy cpu IDs */
94
+
id = coresight_trace_id_find_odd_id(id_map);
95
+
if (id)
96
+
goto trace_id_allocated;
97
+
}
98
+
99
+
/*
100
+
* skip reserved bit 0, look at bitmap length of
101
+
* CORESIGHT_TRACE_ID_RES_TOP from offset of bit 1.
102
+
*/
103
+
id = find_next_zero_bit(id_map->used_ids, CORESIGHT_TRACE_ID_RES_TOP, 1);
104
+
if (id >= CORESIGHT_TRACE_ID_RES_TOP)
105
+
return -EINVAL;
106
+
107
+
/* mark as used */
108
+
trace_id_allocated:
109
+
set_bit(id, id_map->used_ids);
110
+
return id;
111
+
}
112
+
113
+
static void coresight_trace_id_free(int id, struct coresight_trace_id_map *id_map)
114
+
{
115
+
if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id))
116
+
return;
117
+
if (WARN(!test_bit(id, id_map->used_ids), "Freeing unused ID %d\n", id))
118
+
return;
119
+
clear_bit(id, id_map->used_ids);
120
+
}
121
+
122
+
static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_map *id_map)
123
+
{
124
+
if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id))
125
+
return;
126
+
set_bit(id, id_map->pend_rel_ids);
127
+
}
128
+
129
+
/*
130
+
* release all pending IDs for all current maps & clear CPU associations
131
+
*
132
+
* This currently operates on the default id map, but may be extended to
133
+
* operate on all registered id maps if per sink id maps are used.
134
+
*/
135
+
static void coresight_trace_id_release_all_pending(void)
136
+
{
137
+
struct coresight_trace_id_map *id_map = &id_map_default;
138
+
unsigned long flags;
139
+
int cpu, bit;
140
+
141
+
spin_lock_irqsave(&id_map_lock, flags);
142
+
for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_ID_RES_TOP) {
143
+
clear_bit(bit, id_map->used_ids);
144
+
clear_bit(bit, id_map->pend_rel_ids);
145
+
}
146
+
for_each_cpu(cpu, &cpu_id_release_pending) {
147
+
atomic_set(&per_cpu(cpu_id, cpu), 0);
148
+
cpumask_clear_cpu(cpu, &cpu_id_release_pending);
149
+
}
150
+
spin_unlock_irqrestore(&id_map_lock, flags);
151
+
DUMP_ID_MAP(id_map);
152
+
}
153
+
154
+
static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map)
155
+
{
156
+
unsigned long flags;
157
+
int id;
158
+
159
+
spin_lock_irqsave(&id_map_lock, flags);
160
+
161
+
/* check for existing allocation for this CPU */
162
+
id = _coresight_trace_id_read_cpu_id(cpu);
163
+
if (id)
164
+
goto get_cpu_id_clr_pend;
165
+
166
+
/*
167
+
* Find a new ID.
168
+
*
169
+
* Use legacy values where possible in the dynamic trace ID allocator to
170
+
* allow older tools to continue working if they are not upgraded at the
171
+
* same time as the kernel drivers.
172
+
*
173
+
* If the generated legacy ID is invalid, or not available then the next
174
+
* available dynamic ID will be used.
175
+
*/
176
+
id = coresight_trace_id_alloc_new_id(id_map,
177
+
CORESIGHT_LEGACY_CPU_TRACE_ID(cpu),
178
+
false);
179
+
if (!IS_VALID_CS_TRACE_ID(id))
180
+
goto get_cpu_id_out_unlock;
181
+
182
+
/* allocate the new id to the cpu */
183
+
atomic_set(&per_cpu(cpu_id, cpu), id);
184
+
185
+
get_cpu_id_clr_pend:
186
+
/* we are (re)using this ID - so ensure it is not marked for release */
187
+
cpumask_clear_cpu(cpu, &cpu_id_release_pending);
188
+
clear_bit(id, id_map->pend_rel_ids);
189
+
190
+
get_cpu_id_out_unlock:
191
+
spin_unlock_irqrestore(&id_map_lock, flags);
192
+
193
+
DUMP_ID_CPU(cpu, id);
194
+
DUMP_ID_MAP(id_map);
195
+
return id;
196
+
}
197
+
198
+
static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map)
199
+
{
200
+
unsigned long flags;
201
+
int id;
202
+
203
+
/* check for existing allocation for this CPU */
204
+
id = _coresight_trace_id_read_cpu_id(cpu);
205
+
if (!id)
206
+
return;
207
+
208
+
spin_lock_irqsave(&id_map_lock, flags);
209
+
210
+
if (atomic_read(&perf_cs_etm_session_active)) {
211
+
/* set release at pending if perf still active */
212
+
coresight_trace_id_set_pend_rel(id, id_map);
213
+
cpumask_set_cpu(cpu, &cpu_id_release_pending);
214
+
} else {
215
+
/* otherwise clear id */
216
+
coresight_trace_id_free(id, id_map);
217
+
atomic_set(&per_cpu(cpu_id, cpu), 0);
218
+
}
219
+
220
+
spin_unlock_irqrestore(&id_map_lock, flags);
221
+
DUMP_ID_CPU(cpu, id);
222
+
DUMP_ID_MAP(id_map);
223
+
}
224
+
225
+
static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map)
226
+
{
227
+
unsigned long flags;
228
+
int id;
229
+
230
+
spin_lock_irqsave(&id_map_lock, flags);
231
+
/* prefer odd IDs for system components to avoid legacy CPU IDS */
232
+
id = coresight_trace_id_alloc_new_id(id_map, 0, true);
233
+
spin_unlock_irqrestore(&id_map_lock, flags);
234
+
235
+
DUMP_ID(id);
236
+
DUMP_ID_MAP(id_map);
237
+
return id;
238
+
}
239
+
240
+
static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map *id_map, int id)
241
+
{
242
+
unsigned long flags;
243
+
244
+
spin_lock_irqsave(&id_map_lock, flags);
245
+
coresight_trace_id_free(id, id_map);
246
+
spin_unlock_irqrestore(&id_map_lock, flags);
247
+
248
+
DUMP_ID(id);
249
+
DUMP_ID_MAP(id_map);
250
+
}
251
+
252
+
/* API functions */
253
+
254
+
int coresight_trace_id_get_cpu_id(int cpu)
255
+
{
256
+
return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default);
257
+
}
258
+
EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id);
259
+
260
+
void coresight_trace_id_put_cpu_id(int cpu)
261
+
{
262
+
coresight_trace_id_map_put_cpu_id(cpu, &id_map_default);
263
+
}
264
+
EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id);
265
+
266
+
int coresight_trace_id_read_cpu_id(int cpu)
267
+
{
268
+
return _coresight_trace_id_read_cpu_id(cpu);
269
+
}
270
+
EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id);
271
+
272
+
int coresight_trace_id_get_system_id(void)
273
+
{
274
+
return coresight_trace_id_map_get_system_id(&id_map_default);
275
+
}
276
+
EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id);
277
+
278
+
void coresight_trace_id_put_system_id(int id)
279
+
{
280
+
coresight_trace_id_map_put_system_id(&id_map_default, id);
281
+
}
282
+
EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id);
283
+
284
+
void coresight_trace_id_perf_start(void)
285
+
{
286
+
atomic_inc(&perf_cs_etm_session_active);
287
+
PERF_SESSION(atomic_read(&perf_cs_etm_session_active));
288
+
}
289
+
EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start);
290
+
291
+
void coresight_trace_id_perf_stop(void)
292
+
{
293
+
if (!atomic_dec_return(&perf_cs_etm_session_active))
294
+
coresight_trace_id_release_all_pending();
295
+
PERF_SESSION(atomic_read(&perf_cs_etm_session_active));
296
+
}
297
+
EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop);
+156
drivers/hwtracing/coresight/coresight-trace-id.h
+156
drivers/hwtracing/coresight/coresight-trace-id.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright(C) 2022 Linaro Limited. All rights reserved.
4
+
* Author: Mike Leach <mike.leach@linaro.org>
5
+
*/
6
+
7
+
#ifndef _CORESIGHT_TRACE_ID_H
8
+
#define _CORESIGHT_TRACE_ID_H
9
+
10
+
/*
11
+
* Coresight trace ID allocation API
12
+
*
13
+
* With multi cpu systems, and more additional trace sources a scalable
14
+
* trace ID reservation system is required.
15
+
*
16
+
* The system will allocate Ids on a demand basis, and allow them to be
17
+
* released when done.
18
+
*
19
+
* In order to ensure that a consistent cpu / ID matching is maintained
20
+
* throughout a perf cs_etm event session - a session in progress flag will
21
+
* be maintained, and released IDs not cleared until the perf session is
22
+
* complete. This allows the same CPU to be re-allocated its prior ID.
23
+
*
24
+
*
25
+
* Trace ID maps will be created and initialised to prevent architecturally
26
+
* reserved IDs from being allocated.
27
+
*
28
+
* API permits multiple maps to be maintained - for large systems where
29
+
* different sets of cpus trace into different independent sinks.
30
+
*/
31
+
32
+
#include <linux/bitops.h>
33
+
#include <linux/types.h>
34
+
35
+
36
+
/* architecturally we have 128 IDs some of which are reserved */
37
+
#define CORESIGHT_TRACE_IDS_MAX 128
38
+
39
+
/* ID 0 is reserved */
40
+
#define CORESIGHT_TRACE_ID_RES_0 0
41
+
42
+
/* ID 0x70 onwards are reserved */
43
+
#define CORESIGHT_TRACE_ID_RES_TOP 0x70
44
+
45
+
/* check an ID is in the valid range */
46
+
#define IS_VALID_CS_TRACE_ID(id) \
47
+
((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP))
48
+
49
+
/**
50
+
* Trace ID map.
51
+
*
52
+
* @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs.
53
+
* Initialised so that the reserved IDs are permanently marked as
54
+
* in use.
55
+
* @pend_rel_ids: CPU IDs that have been released by the trace source but not
56
+
* yet marked as available, to allow re-allocation to the same
57
+
* CPU during a perf session.
58
+
*/
59
+
struct coresight_trace_id_map {
60
+
DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX);
61
+
DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX);
62
+
};
63
+
64
+
/* Allocate and release IDs for a single default trace ID map */
65
+
66
+
/**
67
+
* Read and optionally allocate a CoreSight trace ID and associate with a CPU.
68
+
*
69
+
* Function will read the current trace ID for the associated CPU,
70
+
* allocating an new ID if one is not currently allocated.
71
+
*
72
+
* Numeric ID values allocated use legacy allocation algorithm if possible,
73
+
* otherwise any available ID is used.
74
+
*
75
+
* @cpu: The CPU index to allocate for.
76
+
*
77
+
* return: CoreSight trace ID or -EINVAL if allocation impossible.
78
+
*/
79
+
int coresight_trace_id_get_cpu_id(int cpu);
80
+
81
+
/**
82
+
* Release an allocated trace ID associated with the CPU.
83
+
*
84
+
* This will release the CoreSight trace ID associated with the CPU,
85
+
* unless a perf session is in operation.
86
+
*
87
+
* If a perf session is in operation then the ID will be marked as pending
88
+
* release.
89
+
*
90
+
* @cpu: The CPU index to release the associated trace ID.
91
+
*/
92
+
void coresight_trace_id_put_cpu_id(int cpu);
93
+
94
+
/**
95
+
* Read the current allocated CoreSight Trace ID value for the CPU.
96
+
*
97
+
* Fast read of the current value that does not allocate if no ID allocated
98
+
* for the CPU.
99
+
*
100
+
* Used in perf context where it is known that the value for the CPU will not
101
+
* be changing, when perf starts and event on a core and outputs the Trace ID
102
+
* for the CPU as a packet in the data file. IDs cannot change during a perf
103
+
* session.
104
+
*
105
+
* This function does not take the lock protecting the ID lists, avoiding
106
+
* locking dependency issues with perf locks.
107
+
*
108
+
* @cpu: The CPU index to read.
109
+
*
110
+
* return: current value, will be 0 if unallocated.
111
+
*/
112
+
int coresight_trace_id_read_cpu_id(int cpu);
113
+
114
+
/**
115
+
* Allocate a CoreSight trace ID for a system component.
116
+
*
117
+
* Unconditionally allocates a Trace ID, without associating the ID with a CPU.
118
+
*
119
+
* Used to allocate IDs for system trace sources such as STM.
120
+
*
121
+
* return: Trace ID or -EINVAL if allocation is impossible.
122
+
*/
123
+
int coresight_trace_id_get_system_id(void);
124
+
125
+
/**
126
+
* Release an allocated system trace ID.
127
+
*
128
+
* Unconditionally release a trace ID allocated to a system component.
129
+
*
130
+
* @id: value of trace ID allocated.
131
+
*/
132
+
void coresight_trace_id_put_system_id(int id);
133
+
134
+
/* notifiers for perf session start and stop */
135
+
136
+
/**
137
+
* Notify the Trace ID allocator that a perf session is starting.
138
+
*
139
+
* Increase the perf session reference count - called by perf when setting up
140
+
* a trace event.
141
+
*
142
+
* This reference count is used by the ID allocator to ensure that trace IDs
143
+
* associated with a CPU cannot change or be released during a perf session.
144
+
*/
145
+
void coresight_trace_id_perf_start(void);
146
+
147
+
/**
148
+
* Notify the ID allocator that a perf session is stopping.
149
+
*
150
+
* Decrease the perf session reference count.
151
+
* if this causes the count to go to zero, then all Trace IDs marked as pending
152
+
* release, will be released.
153
+
*/
154
+
void coresight_trace_id_perf_stop(void);
155
+
156
+
#endif /* _CORESIGHT_TRACE_ID_H */
+648
drivers/hwtracing/coresight/ultrasoc-smb.c
+648
drivers/hwtracing/coresight/ultrasoc-smb.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/*
3
+
* Siemens System Memory Buffer driver.
4
+
* Copyright(c) 2022, HiSilicon Limited.
5
+
*/
6
+
7
+
#include <linux/atomic.h>
8
+
#include <linux/acpi.h>
9
+
#include <linux/circ_buf.h>
10
+
#include <linux/err.h>
11
+
#include <linux/fs.h>
12
+
#include <linux/module.h>
13
+
#include <linux/mod_devicetable.h>
14
+
#include <linux/platform_device.h>
15
+
16
+
#include "coresight-etm-perf.h"
17
+
#include "coresight-priv.h"
18
+
#include "ultrasoc-smb.h"
19
+
20
+
DEFINE_CORESIGHT_DEVLIST(sink_devs, "ultra_smb");
21
+
22
+
#define ULTRASOC_SMB_DSM_UUID "82ae1283-7f6a-4cbe-aa06-53e8fb24db18"
23
+
24
+
static bool smb_buffer_not_empty(struct smb_drv_data *drvdata)
25
+
{
26
+
u32 buf_status = readl(drvdata->base + SMB_LB_INT_STS_REG);
27
+
28
+
return FIELD_GET(SMB_LB_INT_STS_NOT_EMPTY_MSK, buf_status);
29
+
}
30
+
31
+
static void smb_update_data_size(struct smb_drv_data *drvdata)
32
+
{
33
+
struct smb_data_buffer *sdb = &drvdata->sdb;
34
+
u32 buf_wrptr;
35
+
36
+
buf_wrptr = readl(drvdata->base + SMB_LB_WR_ADDR_REG) -
37
+
sdb->buf_hw_base;
38
+
39
+
/* Buffer is full */
40
+
if (buf_wrptr == sdb->buf_rdptr && smb_buffer_not_empty(drvdata)) {
41
+
sdb->data_size = sdb->buf_size;
42
+
return;
43
+
}
44
+
45
+
/* The buffer mode is circular buffer mode */
46
+
sdb->data_size = CIRC_CNT(buf_wrptr, sdb->buf_rdptr,
47
+
sdb->buf_size);
48
+
}
49
+
50
+
/*
51
+
* The read pointer adds @nbytes bytes (may round up to the beginning)
52
+
* after the data is read or discarded, while needing to update the
53
+
* available data size.
54
+
*/
55
+
static void smb_update_read_ptr(struct smb_drv_data *drvdata, u32 nbytes)
56
+
{
57
+
struct smb_data_buffer *sdb = &drvdata->sdb;
58
+
59
+
sdb->buf_rdptr += nbytes;
60
+
sdb->buf_rdptr %= sdb->buf_size;
61
+
writel(sdb->buf_hw_base + sdb->buf_rdptr,
62
+
drvdata->base + SMB_LB_RD_ADDR_REG);
63
+
64
+
sdb->data_size -= nbytes;
65
+
}
66
+
67
+
static void smb_reset_buffer(struct smb_drv_data *drvdata)
68
+
{
69
+
struct smb_data_buffer *sdb = &drvdata->sdb;
70
+
u32 write_ptr;
71
+
72
+
/*
73
+
* We must flush and discard any data left in hardware path
74
+
* to avoid corrupting the next session.
75
+
* Note: The write pointer will never exceed the read pointer.
76
+
*/
77
+
writel(SMB_LB_PURGE_PURGED, drvdata->base + SMB_LB_PURGE_REG);
78
+
79
+
/* Reset SMB logical buffer status flags */
80
+
writel(SMB_LB_INT_STS_RESET, drvdata->base + SMB_LB_INT_STS_REG);
81
+
82
+
write_ptr = readl(drvdata->base + SMB_LB_WR_ADDR_REG);
83
+
84
+
/* Do nothing, not data left in hardware path */
85
+
if (!write_ptr || write_ptr == sdb->buf_rdptr + sdb->buf_hw_base)
86
+
return;
87
+
88
+
/*
89
+
* The SMB_LB_WR_ADDR_REG register is read-only,
90
+
* Synchronize the read pointer to write pointer.
91
+
*/
92
+
writel(write_ptr, drvdata->base + SMB_LB_RD_ADDR_REG);
93
+
sdb->buf_rdptr = write_ptr - sdb->buf_hw_base;
94
+
}
95
+
96
+
static int smb_open(struct inode *inode, struct file *file)
97
+
{
98
+
struct smb_drv_data *drvdata = container_of(file->private_data,
99
+
struct smb_drv_data, miscdev);
100
+
int ret = 0;
101
+
102
+
mutex_lock(&drvdata->mutex);
103
+
104
+
if (drvdata->reading) {
105
+
ret = -EBUSY;
106
+
goto out;
107
+
}
108
+
109
+
if (atomic_read(drvdata->csdev->refcnt)) {
110
+
ret = -EBUSY;
111
+
goto out;
112
+
}
113
+
114
+
smb_update_data_size(drvdata);
115
+
116
+
drvdata->reading = true;
117
+
out:
118
+
mutex_unlock(&drvdata->mutex);
119
+
120
+
return ret;
121
+
}
122
+
123
+
static ssize_t smb_read(struct file *file, char __user *data, size_t len,
124
+
loff_t *ppos)
125
+
{
126
+
struct smb_drv_data *drvdata = container_of(file->private_data,
127
+
struct smb_drv_data, miscdev);
128
+
struct smb_data_buffer *sdb = &drvdata->sdb;
129
+
struct device *dev = &drvdata->csdev->dev;
130
+
ssize_t to_copy = 0;
131
+
132
+
if (!len)
133
+
return 0;
134
+
135
+
mutex_lock(&drvdata->mutex);
136
+
137
+
if (!sdb->data_size)
138
+
goto out;
139
+
140
+
to_copy = min(sdb->data_size, len);
141
+
142
+
/* Copy parts of trace data when read pointer wrap around SMB buffer */
143
+
if (sdb->buf_rdptr + to_copy > sdb->buf_size)
144
+
to_copy = sdb->buf_size - sdb->buf_rdptr;
145
+
146
+
if (copy_to_user(data, sdb->buf_base + sdb->buf_rdptr, to_copy)) {
147
+
dev_dbg(dev, "Failed to copy data to user\n");
148
+
to_copy = -EFAULT;
149
+
goto out;
150
+
}
151
+
152
+
*ppos += to_copy;
153
+
154
+
smb_update_read_ptr(drvdata, to_copy);
155
+
156
+
dev_dbg(dev, "%zu bytes copied\n", to_copy);
157
+
out:
158
+
if (!sdb->data_size)
159
+
smb_reset_buffer(drvdata);
160
+
mutex_unlock(&drvdata->mutex);
161
+
162
+
return to_copy;
163
+
}
164
+
165
+
static int smb_release(struct inode *inode, struct file *file)
166
+
{
167
+
struct smb_drv_data *drvdata = container_of(file->private_data,
168
+
struct smb_drv_data, miscdev);
169
+
170
+
mutex_lock(&drvdata->mutex);
171
+
drvdata->reading = false;
172
+
mutex_unlock(&drvdata->mutex);
173
+
174
+
return 0;
175
+
}
176
+
177
+
static const struct file_operations smb_fops = {
178
+
.owner = THIS_MODULE,
179
+
.open = smb_open,
180
+
.read = smb_read,
181
+
.release = smb_release,
182
+
.llseek = no_llseek,
183
+
};
184
+
185
+
static ssize_t buf_size_show(struct device *dev, struct device_attribute *attr,
186
+
char *buf)
187
+
{
188
+
struct smb_drv_data *drvdata = dev_get_drvdata(dev->parent);
189
+
190
+
return sysfs_emit(buf, "0x%lx\n", drvdata->sdb.buf_size);
191
+
}
192
+
static DEVICE_ATTR_RO(buf_size);
193
+
194
+
static struct attribute *smb_sink_attrs[] = {
195
+
coresight_simple_reg32(read_pos, SMB_LB_RD_ADDR_REG),
196
+
coresight_simple_reg32(write_pos, SMB_LB_WR_ADDR_REG),
197
+
coresight_simple_reg32(buf_status, SMB_LB_INT_STS_REG),
198
+
&dev_attr_buf_size.attr,
199
+
NULL
200
+
};
201
+
202
+
static const struct attribute_group smb_sink_group = {
203
+
.attrs = smb_sink_attrs,
204
+
.name = "mgmt",
205
+
};
206
+
207
+
static const struct attribute_group *smb_sink_groups[] = {
208
+
&smb_sink_group,
209
+
NULL
210
+
};
211
+
212
+
static void smb_enable_hw(struct smb_drv_data *drvdata)
213
+
{
214
+
writel(SMB_GLB_EN_HW_ENABLE, drvdata->base + SMB_GLB_EN_REG);
215
+
}
216
+
217
+
static void smb_disable_hw(struct smb_drv_data *drvdata)
218
+
{
219
+
writel(0x0, drvdata->base + SMB_GLB_EN_REG);
220
+
}
221
+
222
+
static void smb_enable_sysfs(struct coresight_device *csdev)
223
+
{
224
+
struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent);
225
+
226
+
if (drvdata->mode != CS_MODE_DISABLED)
227
+
return;
228
+
229
+
smb_enable_hw(drvdata);
230
+
drvdata->mode = CS_MODE_SYSFS;
231
+
}
232
+
233
+
static int smb_enable_perf(struct coresight_device *csdev, void *data)
234
+
{
235
+
struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent);
236
+
struct perf_output_handle *handle = data;
237
+
struct cs_buffers *buf = etm_perf_sink_config(handle);
238
+
pid_t pid;
239
+
240
+
if (!buf)
241
+
return -EINVAL;
242
+
243
+
/* Get a handle on the pid of the target process */
244
+
pid = buf->pid;
245
+
246
+
/* Device is already in used by other session */
247
+
if (drvdata->pid != -1 && drvdata->pid != pid)
248
+
return -EBUSY;
249
+
250
+
if (drvdata->pid == -1) {
251
+
smb_enable_hw(drvdata);
252
+
drvdata->pid = pid;
253
+
drvdata->mode = CS_MODE_PERF;
254
+
}
255
+
256
+
return 0;
257
+
}
258
+
259
+
static int smb_enable(struct coresight_device *csdev, u32 mode, void *data)
260
+
{
261
+
struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent);
262
+
int ret = 0;
263
+
264
+
mutex_lock(&drvdata->mutex);
265
+
266
+
/* Do nothing, the trace data is reading by other interface now */
267
+
if (drvdata->reading) {
268
+
ret = -EBUSY;
269
+
goto out;
270
+
}
271
+
272
+
/* Do nothing, the SMB is already enabled as other mode */
273
+
if (drvdata->mode != CS_MODE_DISABLED && drvdata->mode != mode) {
274
+
ret = -EBUSY;
275
+
goto out;
276
+
}
277
+
278
+
switch (mode) {
279
+
case CS_MODE_SYSFS:
280
+
smb_enable_sysfs(csdev);
281
+
break;
282
+
case CS_MODE_PERF:
283
+
ret = smb_enable_perf(csdev, data);
284
+
break;
285
+
default:
286
+
ret = -EINVAL;
287
+
}
288
+
289
+
if (ret)
290
+
goto out;
291
+
292
+
atomic_inc(csdev->refcnt);
293
+
294
+
dev_dbg(&csdev->dev, "Ultrasoc SMB enabled\n");
295
+
out:
296
+
mutex_unlock(&drvdata->mutex);
297
+
298
+
return ret;
299
+
}
300
+
301
+
static int smb_disable(struct coresight_device *csdev)
302
+
{
303
+
struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent);
304
+
int ret = 0;
305
+
306
+
mutex_lock(&drvdata->mutex);
307
+
308
+
if (drvdata->reading) {
309
+
ret = -EBUSY;
310
+
goto out;
311
+
}
312
+
313
+
if (atomic_dec_return(csdev->refcnt)) {
314
+
ret = -EBUSY;
315
+
goto out;
316
+
}
317
+
318
+
/* Complain if we (somehow) got out of sync */
319
+
WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED);
320
+
321
+
smb_disable_hw(drvdata);
322
+
323
+
/* Dissociate from the target process. */
324
+
drvdata->pid = -1;
325
+
drvdata->mode = CS_MODE_DISABLED;
326
+
327
+
dev_dbg(&csdev->dev, "Ultrasoc SMB disabled\n");
328
+
out:
329
+
mutex_unlock(&drvdata->mutex);
330
+
331
+
return ret;
332
+
}
333
+
334
+
static void *smb_alloc_buffer(struct coresight_device *csdev,
335
+
struct perf_event *event, void **pages,
336
+
int nr_pages, bool overwrite)
337
+
{
338
+
struct cs_buffers *buf;
339
+
int node;
340
+
341
+
node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu);
342
+
buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
343
+
if (!buf)
344
+
return NULL;
345
+
346
+
buf->snapshot = overwrite;
347
+
buf->nr_pages = nr_pages;
348
+
buf->data_pages = pages;
349
+
buf->pid = task_pid_nr(event->owner);
350
+
351
+
return buf;
352
+
}
353
+
354
+
static void smb_free_buffer(void *config)
355
+
{
356
+
struct cs_buffers *buf = config;
357
+
358
+
kfree(buf);
359
+
}
360
+
361
+
static void smb_sync_perf_buffer(struct smb_drv_data *drvdata,
362
+
struct cs_buffers *buf,
363
+
unsigned long head)
364
+
{
365
+
struct smb_data_buffer *sdb = &drvdata->sdb;
366
+
char **dst_pages = (char **)buf->data_pages;
367
+
unsigned long to_copy;
368
+
long pg_idx, pg_offset;
369
+
370
+
pg_idx = head >> PAGE_SHIFT;
371
+
pg_offset = head & (PAGE_SIZE - 1);
372
+
373
+
while (sdb->data_size) {
374
+
unsigned long pg_space = PAGE_SIZE - pg_offset;
375
+
376
+
to_copy = min(sdb->data_size, pg_space);
377
+
378
+
/* Copy parts of trace data when read pointer wrap around */
379
+
if (sdb->buf_rdptr + to_copy > sdb->buf_size)
380
+
to_copy = sdb->buf_size - sdb->buf_rdptr;
381
+
382
+
memcpy(dst_pages[pg_idx] + pg_offset,
383
+
sdb->buf_base + sdb->buf_rdptr, to_copy);
384
+
385
+
pg_offset += to_copy;
386
+
if (pg_offset >= PAGE_SIZE) {
387
+
pg_offset = 0;
388
+
pg_idx++;
389
+
pg_idx %= buf->nr_pages;
390
+
}
391
+
smb_update_read_ptr(drvdata, to_copy);
392
+
}
393
+
394
+
smb_reset_buffer(drvdata);
395
+
}
396
+
397
+
static unsigned long smb_update_buffer(struct coresight_device *csdev,
398
+
struct perf_output_handle *handle,
399
+
void *sink_config)
400
+
{
401
+
struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent);
402
+
struct smb_data_buffer *sdb = &drvdata->sdb;
403
+
struct cs_buffers *buf = sink_config;
404
+
unsigned long data_size = 0;
405
+
bool lost = false;
406
+
407
+
if (!buf)
408
+
return 0;
409
+
410
+
mutex_lock(&drvdata->mutex);
411
+
412
+
/* Don't do anything if another tracer is using this sink. */
413
+
if (atomic_read(csdev->refcnt) != 1)
414
+
goto out;
415
+
416
+
smb_disable_hw(drvdata);
417
+
smb_update_data_size(drvdata);
418
+
419
+
/*
420
+
* The SMB buffer may be bigger than the space available in the
421
+
* perf ring buffer (handle->size). If so advance the offset so
422
+
* that we get the latest trace data.
423
+
*/
424
+
if (sdb->data_size > handle->size) {
425
+
smb_update_read_ptr(drvdata, sdb->data_size - handle->size);
426
+
lost = true;
427
+
}
428
+
429
+
data_size = sdb->data_size;
430
+
smb_sync_perf_buffer(drvdata, buf, handle->head);
431
+
if (!buf->snapshot && lost)
432
+
perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
433
+
out:
434
+
mutex_unlock(&drvdata->mutex);
435
+
436
+
return data_size;
437
+
}
438
+
439
+
static const struct coresight_ops_sink smb_cs_ops = {
440
+
.enable = smb_enable,
441
+
.disable = smb_disable,
442
+
.alloc_buffer = smb_alloc_buffer,
443
+
.free_buffer = smb_free_buffer,
444
+
.update_buffer = smb_update_buffer,
445
+
};
446
+
447
+
static const struct coresight_ops cs_ops = {
448
+
.sink_ops = &smb_cs_ops,
449
+
};
450
+
451
+
static int smb_init_data_buffer(struct platform_device *pdev,
452
+
struct smb_data_buffer *sdb)
453
+
{
454
+
struct resource *res;
455
+
void *base;
456
+
457
+
res = platform_get_resource(pdev, IORESOURCE_MEM, SMB_BUF_ADDR_RES);
458
+
if (!res) {
459
+
dev_err(&pdev->dev, "SMB device failed to get resource\n");
460
+
return -EINVAL;
461
+
}
462
+
463
+
sdb->buf_rdptr = 0;
464
+
sdb->buf_hw_base = FIELD_GET(SMB_BUF_ADDR_LO_MSK, res->start);
465
+
sdb->buf_size = resource_size(res);
466
+
if (sdb->buf_size == 0)
467
+
return -EINVAL;
468
+
469
+
/*
470
+
* This is a chunk of memory, use classic mapping with better
471
+
* performance.
472
+
*/
473
+
base = devm_memremap(&pdev->dev, sdb->buf_hw_base, sdb->buf_size,
474
+
MEMREMAP_WB);
475
+
if (IS_ERR(base))
476
+
return PTR_ERR(base);
477
+
478
+
sdb->buf_base = base;
479
+
480
+
return 0;
481
+
}
482
+
483
+
static void smb_init_hw(struct smb_drv_data *drvdata)
484
+
{
485
+
smb_disable_hw(drvdata);
486
+
smb_reset_buffer(drvdata);
487
+
488
+
writel(SMB_LB_CFG_LO_DEFAULT, drvdata->base + SMB_LB_CFG_LO_REG);
489
+
writel(SMB_LB_CFG_HI_DEFAULT, drvdata->base + SMB_LB_CFG_HI_REG);
490
+
writel(SMB_GLB_CFG_DEFAULT, drvdata->base + SMB_GLB_CFG_REG);
491
+
writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLB_INT_REG);
492
+
writel(SMB_LB_INT_CTRL_CFG, drvdata->base + SMB_LB_INT_CTRL_REG);
493
+
}
494
+
495
+
static int smb_register_sink(struct platform_device *pdev,
496
+
struct smb_drv_data *drvdata)
497
+
{
498
+
struct coresight_platform_data *pdata = NULL;
499
+
struct coresight_desc desc = { 0 };
500
+
int ret;
501
+
502
+
pdata = coresight_get_platform_data(&pdev->dev);
503
+
if (IS_ERR(pdata))
504
+
return PTR_ERR(pdata);
505
+
506
+
desc.type = CORESIGHT_DEV_TYPE_SINK;
507
+
desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
508
+
desc.ops = &cs_ops;
509
+
desc.pdata = pdata;
510
+
desc.dev = &pdev->dev;
511
+
desc.groups = smb_sink_groups;
512
+
desc.name = coresight_alloc_device_name(&sink_devs, &pdev->dev);
513
+
if (!desc.name) {
514
+
dev_err(&pdev->dev, "Failed to alloc coresight device name");
515
+
return -ENOMEM;
516
+
}
517
+
desc.access = CSDEV_ACCESS_IOMEM(drvdata->base);
518
+
519
+
drvdata->csdev = coresight_register(&desc);
520
+
if (IS_ERR(drvdata->csdev))
521
+
return PTR_ERR(drvdata->csdev);
522
+
523
+
drvdata->miscdev.name = desc.name;
524
+
drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
525
+
drvdata->miscdev.fops = &smb_fops;
526
+
ret = misc_register(&drvdata->miscdev);
527
+
if (ret) {
528
+
coresight_unregister(drvdata->csdev);
529
+
dev_err(&pdev->dev, "Failed to register misc, ret=%d\n", ret);
530
+
}
531
+
532
+
return ret;
533
+
}
534
+
535
+
static void smb_unregister_sink(struct smb_drv_data *drvdata)
536
+
{
537
+
misc_deregister(&drvdata->miscdev);
538
+
coresight_unregister(drvdata->csdev);
539
+
}
540
+
541
+
static int smb_config_inport(struct device *dev, bool enable)
542
+
{
543
+
u64 func = enable ? 1 : 0;
544
+
union acpi_object *obj;
545
+
guid_t guid;
546
+
u64 rev = 0;
547
+
548
+
/*
549
+
* Using DSM calls to enable/disable ultrasoc hardwares on
550
+
* tracing path, to prevent ultrasoc packet format being exposed.
551
+
*/
552
+
if (guid_parse(ULTRASOC_SMB_DSM_UUID, &guid)) {
553
+
dev_err(dev, "Get GUID failed\n");
554
+
return -EINVAL;
555
+
}
556
+
557
+
obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, rev, func, NULL);
558
+
if (!obj) {
559
+
dev_err(dev, "ACPI handle failed\n");
560
+
return -ENODEV;
561
+
}
562
+
563
+
ACPI_FREE(obj);
564
+
565
+
return 0;
566
+
}
567
+
568
+
static int smb_probe(struct platform_device *pdev)
569
+
{
570
+
struct device *dev = &pdev->dev;
571
+
struct smb_drv_data *drvdata;
572
+
int ret;
573
+
574
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
575
+
if (!drvdata)
576
+
return -ENOMEM;
577
+
578
+
drvdata->base = devm_platform_ioremap_resource(pdev, SMB_REG_ADDR_RES);
579
+
if (IS_ERR(drvdata->base)) {
580
+
dev_err(dev, "Failed to ioremap resource\n");
581
+
return PTR_ERR(drvdata->base);
582
+
}
583
+
584
+
smb_init_hw(drvdata);
585
+
586
+
ret = smb_init_data_buffer(pdev, &drvdata->sdb);
587
+
if (ret) {
588
+
dev_err(dev, "Failed to init buffer, ret = %d\n", ret);
589
+
return ret;
590
+
}
591
+
592
+
mutex_init(&drvdata->mutex);
593
+
drvdata->pid = -1;
594
+
595
+
ret = smb_register_sink(pdev, drvdata);
596
+
if (ret) {
597
+
dev_err(dev, "Failed to register SMB sink\n");
598
+
return ret;
599
+
}
600
+
601
+
ret = smb_config_inport(dev, true);
602
+
if (ret) {
603
+
smb_unregister_sink(drvdata);
604
+
return ret;
605
+
}
606
+
607
+
platform_set_drvdata(pdev, drvdata);
608
+
609
+
return 0;
610
+
}
611
+
612
+
static int smb_remove(struct platform_device *pdev)
613
+
{
614
+
struct smb_drv_data *drvdata = platform_get_drvdata(pdev);
615
+
int ret;
616
+
617
+
ret = smb_config_inport(&pdev->dev, false);
618
+
if (ret)
619
+
return ret;
620
+
621
+
smb_unregister_sink(drvdata);
622
+
623
+
return 0;
624
+
}
625
+
626
+
#ifdef CONFIG_ACPI
627
+
static const struct acpi_device_id ultrasoc_smb_acpi_match[] = {
628
+
{"HISI03A1", 0},
629
+
{}
630
+
};
631
+
MODULE_DEVICE_TABLE(acpi, ultrasoc_smb_acpi_match);
632
+
#endif
633
+
634
+
static struct platform_driver smb_driver = {
635
+
.driver = {
636
+
.name = "ultrasoc-smb",
637
+
.acpi_match_table = ACPI_PTR(ultrasoc_smb_acpi_match),
638
+
.suppress_bind_attrs = true,
639
+
},
640
+
.probe = smb_probe,
641
+
.remove = smb_remove,
642
+
};
643
+
module_platform_driver(smb_driver);
644
+
645
+
MODULE_DESCRIPTION("UltraSoc SMB CoreSight driver");
646
+
MODULE_LICENSE("Dual MIT/GPL");
647
+
MODULE_AUTHOR("Jonathan Zhou <jonathan.zhouwen@huawei.com>");
648
+
MODULE_AUTHOR("Qi Liu <liuqi115@huawei.com>");
+125
drivers/hwtracing/coresight/ultrasoc-smb.h
+125
drivers/hwtracing/coresight/ultrasoc-smb.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2
+
/*
3
+
* Siemens System Memory Buffer driver.
4
+
* Copyright(c) 2022, HiSilicon Limited.
5
+
*/
6
+
7
+
#ifndef _ULTRASOC_SMB_H
8
+
#define _ULTRASOC_SMB_H
9
+
10
+
#include <linux/miscdevice.h>
11
+
#include <linux/mutex.h>
12
+
13
+
/* Offset of SMB global registers */
14
+
#define SMB_GLB_CFG_REG 0x00
15
+
#define SMB_GLB_EN_REG 0x04
16
+
#define SMB_GLB_INT_REG 0x08
17
+
18
+
/* Offset of SMB logical buffer registers */
19
+
#define SMB_LB_CFG_LO_REG 0x40
20
+
#define SMB_LB_CFG_HI_REG 0x44
21
+
#define SMB_LB_INT_CTRL_REG 0x48
22
+
#define SMB_LB_INT_STS_REG 0x4c
23
+
#define SMB_LB_RD_ADDR_REG 0x5c
24
+
#define SMB_LB_WR_ADDR_REG 0x60
25
+
#define SMB_LB_PURGE_REG 0x64
26
+
27
+
/* Set global config register */
28
+
#define SMB_GLB_CFG_BURST_LEN_MSK GENMASK(11, 4)
29
+
#define SMB_GLB_CFG_IDLE_PRD_MSK GENMASK(15, 12)
30
+
#define SMB_GLB_CFG_MEM_WR_MSK GENMASK(21, 16)
31
+
#define SMB_GLB_CFG_MEM_RD_MSK GENMASK(27, 22)
32
+
#define SMB_GLB_CFG_DEFAULT (FIELD_PREP(SMB_GLB_CFG_BURST_LEN_MSK, 0xf) | \
33
+
FIELD_PREP(SMB_GLB_CFG_IDLE_PRD_MSK, 0xf) | \
34
+
FIELD_PREP(SMB_GLB_CFG_MEM_WR_MSK, 0x3) | \
35
+
FIELD_PREP(SMB_GLB_CFG_MEM_RD_MSK, 0x1b))
36
+
37
+
#define SMB_GLB_EN_HW_ENABLE BIT(0)
38
+
39
+
/* Set global interrupt control register */
40
+
#define SMB_GLB_INT_EN BIT(0)
41
+
#define SMB_GLB_INT_PULSE BIT(1) /* Interrupt type: 1 - Pulse */
42
+
#define SMB_GLB_INT_ACT_H BIT(2) /* Interrupt polarity: 1 - Active high */
43
+
#define SMB_GLB_INT_CFG (SMB_GLB_INT_EN | SMB_GLB_INT_PULSE | \
44
+
SMB_GLB_INT_ACT_H)
45
+
46
+
/* Set logical buffer config register lower 32 bits */
47
+
#define SMB_LB_CFG_LO_EN BIT(0)
48
+
#define SMB_LB_CFG_LO_SINGLE_END BIT(1)
49
+
#define SMB_LB_CFG_LO_INIT BIT(8)
50
+
#define SMB_LB_CFG_LO_CONT BIT(11)
51
+
#define SMB_LB_CFG_LO_FLOW_MSK GENMASK(19, 16)
52
+
#define SMB_LB_CFG_LO_DEFAULT (SMB_LB_CFG_LO_EN | SMB_LB_CFG_LO_SINGLE_END | \
53
+
SMB_LB_CFG_LO_INIT | SMB_LB_CFG_LO_CONT | \
54
+
FIELD_PREP(SMB_LB_CFG_LO_FLOW_MSK, 0xf))
55
+
56
+
/* Set logical buffer config register upper 32 bits */
57
+
#define SMB_LB_CFG_HI_RANGE_UP_MSK GENMASK(15, 8)
58
+
#define SMB_LB_CFG_HI_DEFAULT FIELD_PREP(SMB_LB_CFG_HI_RANGE_UP_MSK, 0xff)
59
+
60
+
/*
61
+
* Set logical buffer interrupt control register.
62
+
* The register control the validity of both real-time events and
63
+
* interrupts. When logical buffer status changes causes to issue
64
+
* an interrupt at the same time as it issues a real-time event.
65
+
* Real-time events are used in SMB driver, which needs to get the buffer
66
+
* status. Interrupts are used in debugger mode.
67
+
* SMB_LB_INT_CTRL_BUF_NOTE_MASK control which events flags or interrupts
68
+
* are valid.
69
+
*/
70
+
#define SMB_LB_INT_CTRL_EN BIT(0)
71
+
#define SMB_LB_INT_CTRL_BUF_NOTE_MSK GENMASK(11, 8)
72
+
#define SMB_LB_INT_CTRL_CFG (SMB_LB_INT_CTRL_EN | \
73
+
FIELD_PREP(SMB_LB_INT_CTRL_BUF_NOTE_MSK, 0xf))
74
+
75
+
/* Set logical buffer interrupt status register */
76
+
#define SMB_LB_INT_STS_NOT_EMPTY_MSK BIT(0)
77
+
#define SMB_LB_INT_STS_BUF_RESET_MSK GENMASK(3, 0)
78
+
#define SMB_LB_INT_STS_RESET FIELD_PREP(SMB_LB_INT_STS_BUF_RESET_MSK, 0xf)
79
+
80
+
#define SMB_LB_PURGE_PURGED BIT(0)
81
+
82
+
#define SMB_REG_ADDR_RES 0
83
+
#define SMB_BUF_ADDR_RES 1
84
+
#define SMB_BUF_ADDR_LO_MSK GENMASK(31, 0)
85
+
86
+
/**
87
+
* struct smb_data_buffer - Details of the buffer used by SMB
88
+
* @buf_base: Memory mapped base address of SMB.
89
+
* @buf_hw_base: SMB buffer start Physical base address, only used 32bits.
90
+
* @buf_size: Size of the buffer.
91
+
* @data_size: Size of the available trace data for SMB.
92
+
* @buf_rdptr: Current read position (index) within the buffer.
93
+
*/
94
+
struct smb_data_buffer {
95
+
void *buf_base;
96
+
u32 buf_hw_base;
97
+
unsigned long buf_size;
98
+
unsigned long data_size;
99
+
unsigned long buf_rdptr;
100
+
};
101
+
102
+
/**
103
+
* struct smb_drv_data - specifics associated to an SMB component
104
+
* @base: Memory mapped base address for SMB component.
105
+
* @csdev: Component vitals needed by the framework.
106
+
* @sdb: Data buffer for SMB.
107
+
* @miscdev: Specifics to handle "/dev/xyz.smb" entry.
108
+
* @mutex: Control data access to one at a time.
109
+
* @reading: Synchronise user space access to SMB buffer.
110
+
* @pid: Process ID of the process being monitored by the
111
+
* session that is using this component.
112
+
* @mode: How this SMB is being used, perf mode or sysfs mode.
113
+
*/
114
+
struct smb_drv_data {
115
+
void __iomem *base;
116
+
struct coresight_device *csdev;
117
+
struct smb_data_buffer sdb;
118
+
struct miscdevice miscdev;
119
+
struct mutex mutex;
120
+
bool reading;
121
+
pid_t pid;
122
+
u32 mode;
123
+
};
124
+
125
+
#endif
+10
drivers/hwtracing/ptt/hisi_ptt.c
+10
drivers/hwtracing/ptt/hisi_ptt.c
···
356
356
357
357
static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data)
358
358
{
359
+
struct pci_dev *root_port = pcie_find_root_port(pdev);
359
360
struct hisi_ptt_filter_desc *filter;
360
361
struct hisi_ptt *hisi_ptt = data;
362
+
u32 port_devid;
363
+
364
+
if (!root_port)
365
+
return 0;
366
+
367
+
port_devid = PCI_DEVID(root_port->bus->number, root_port->devfn);
368
+
if (port_devid < hisi_ptt->lower_bdf ||
369
+
port_devid > hisi_ptt->upper_bdf)
370
+
return 0;
361
371
362
372
/*
363
373
* We won't fail the probe if filter allocation failed here. The filters
+1
-1
drivers/iio/accel/Kconfig
+1
-1
drivers/iio/accel/Kconfig
···
380
380
select IIO_TRIGGERED_BUFFER if (IIO_BUFFER)
381
381
help
382
382
Say yes here to build support for STMicroelectronics accelerometers:
383
-
LSM303DLH, LSM303DLHC, LIS3DH, LSM330D, LSM330DL, LSM330DLC,
383
+
LSM303C, LSM303DLH, LSM303DLHC, LIS3DH, LSM330D, LSM330DL, LSM330DLC,
384
384
LIS331DLH, LSM303DL, LSM303DLM, LSM330, LIS2DH12, H3LIS331DL,
385
385
LNG2DM, LIS3DE, LIS2DE12, LIS2HH12
386
386
-4
drivers/iio/accel/bma400.h
-4
drivers/iio/accel/bma400.h
···
141
141
#define BMA400_SCALE_MIN 9577
142
142
#define BMA400_SCALE_MAX 76617
143
143
144
-
#define BMA400_NUM_REGULATORS 2
145
-
#define BMA400_VDD_REGULATOR 0
146
-
#define BMA400_VDDIO_REGULATOR 1
147
-
148
144
extern const struct regmap_config bma400_regmap_config;
149
145
150
146
int bma400_probe(struct device *dev, struct regmap *regmap, int irq,
+4
-25
drivers/iio/accel/bma400_core.c
+4
-25
drivers/iio/accel/bma400_core.c
···
98
98
struct bma400_data {
99
99
struct device *dev;
100
100
struct regmap *regmap;
101
-
struct regulator_bulk_data regulators[BMA400_NUM_REGULATORS];
102
101
struct mutex mutex; /* data register lock */
103
102
struct iio_mount_matrix orientation;
104
103
enum bma400_power_mode power_mode;
···
831
832
}
832
833
}
833
834
834
-
static void bma400_regulators_disable(void *data_ptr)
835
-
{
836
-
struct bma400_data *data = data_ptr;
837
-
838
-
regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators);
839
-
}
840
-
841
835
static void bma400_power_disable(void *data_ptr)
842
836
{
843
837
struct bma400_data *data = data_ptr;
···
860
868
861
869
static int bma400_init(struct bma400_data *data)
862
870
{
871
+
static const char * const regulator_names[] = { "vdd", "vddio" };
863
872
unsigned int val;
864
873
int ret;
865
874
866
-
data->regulators[BMA400_VDD_REGULATOR].supply = "vdd";
867
-
data->regulators[BMA400_VDDIO_REGULATOR].supply = "vddio";
868
-
ret = devm_regulator_bulk_get(data->dev,
869
-
ARRAY_SIZE(data->regulators),
870
-
data->regulators);
875
+
ret = devm_regulator_bulk_get_enable(data->dev,
876
+
ARRAY_SIZE(regulator_names),
877
+
regulator_names);
871
878
if (ret)
872
879
return dev_err_probe(data->dev, ret, "Failed to get regulators: %d\n",
873
880
ret);
874
-
875
-
ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
876
-
data->regulators);
877
-
if (ret) {
878
-
dev_err(data->dev, "Failed to enable regulators: %d\n",
879
-
ret);
880
-
return ret;
881
-
}
882
-
883
-
ret = devm_add_action_or_reset(data->dev, bma400_regulators_disable, data);
884
-
if (ret)
885
-
return ret;
886
881
887
882
/* Try to read chip_id register. It must return 0x90. */
888
883
ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val);
+8
-2
drivers/iio/accel/mma9551_core.c
+8
-2
drivers/iio/accel/mma9551_core.c
···
296
296
297
297
ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_CONFIG,
298
298
reg, NULL, 0, (u8 *)&v, 2);
299
+
if (ret < 0)
300
+
return ret;
301
+
299
302
*val = be16_to_cpu(v);
300
303
301
-
return ret;
304
+
return 0;
302
305
}
303
306
EXPORT_SYMBOL_NS(mma9551_read_config_word, IIO_MMA9551);
304
307
···
357
354
358
355
ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_STATUS,
359
356
reg, NULL, 0, (u8 *)&v, 2);
357
+
if (ret < 0)
358
+
return ret;
359
+
360
360
*val = be16_to_cpu(v);
361
361
362
-
return ret;
362
+
return 0;
363
363
}
364
364
EXPORT_SYMBOL_NS(mma9551_read_status_word, IIO_MMA9551);
365
365
+1
drivers/iio/accel/st_accel.h
+1
drivers/iio/accel/st_accel.h
+1
drivers/iio/accel/st_accel_core.c
+1
drivers/iio/accel/st_accel_core.c
+5
drivers/iio/accel/st_accel_i2c.c
+5
drivers/iio/accel/st_accel_i2c.c
···
112
112
.data = LIS302DL_ACCEL_DEV_NAME,
113
113
},
114
114
{
115
+
.compatible = "st,lsm303c-accel",
116
+
.data = LSM303C_ACCEL_DEV_NAME,
117
+
},
118
+
{
115
119
.compatible = "silan,sc7a20",
116
120
.data = SC7A20_ACCEL_DEV_NAME,
117
121
},
···
155
151
{ LIS2DE12_ACCEL_DEV_NAME },
156
152
{ LIS2HH12_ACCEL_DEV_NAME },
157
153
{ LIS302DL_ACCEL_DEV_NAME },
154
+
{ LSM303C_ACCEL_DEV_NAME },
158
155
{ SC7A20_ACCEL_DEV_NAME },
159
156
{},
160
157
};
+5
drivers/iio/accel/st_accel_spi.c
+5
drivers/iio/accel/st_accel_spi.c
···
96
96
.compatible = "st,lis302dl",
97
97
.data = LIS302DL_ACCEL_DEV_NAME,
98
98
},
99
+
{
100
+
.compatible = "st,lsm303c-accel",
101
+
.data = LSM303C_ACCEL_DEV_NAME,
102
+
},
99
103
{}
100
104
};
101
105
MODULE_DEVICE_TABLE(of, st_accel_of_match);
···
156
152
{ LIS3DHH_ACCEL_DEV_NAME },
157
153
{ LIS3DE_ACCEL_DEV_NAME },
158
154
{ LIS302DL_ACCEL_DEV_NAME },
155
+
{ LSM303C_ACCEL_DEV_NAME },
159
156
{},
160
157
};
161
158
MODULE_DEVICE_TABLE(spi, st_accel_id_table);
+33
-1
drivers/iio/adc/Kconfig
+33
-1
drivers/iio/adc/Kconfig
···
441
441
442
442
config EP93XX_ADC
443
443
tristate "Cirrus Logic EP93XX ADC driver"
444
-
depends on ARCH_EP93XX
444
+
depends on ARCH_EP93XX || COMPILE_TEST
445
+
depends on HAS_IOMEM
445
446
help
446
447
Driver for the ADC module on the EP93XX series of SoC from Cirrus Logic.
447
448
It's recommended to switch on CONFIG_HIGH_RES_TIMERS option, in this
···
565
564
566
565
This driver can also be built as a module. If so, the module will be
567
566
called imx8qxp-adc.
567
+
568
+
config IMX93_ADC
569
+
tristate "IMX93 ADC driver"
570
+
depends on ARCH_MXC || COMPILE_TEST
571
+
depends on HAS_IOMEM
572
+
help
573
+
Say yes here to build support for IMX93 ADC.
574
+
575
+
This driver can also be built as a module. If so, the module will be
576
+
called imx93_adc.
568
577
569
578
config LP8788_ADC
570
579
tristate "LP8788 ADC driver"
···
1218
1207
This driver can also be built as a module. If so, the module will be
1219
1208
called ti-ads1015.
1220
1209
1210
+
config TI_ADS7924
1211
+
tristate "Texas Instruments ADS7924 ADC"
1212
+
depends on I2C
1213
+
select REGMAP_I2C
1214
+
help
1215
+
If you say yes here you get support for Texas Instruments ADS7924
1216
+
4 channels, 12-bit I2C ADC chip.
1217
+
1218
+
This driver can also be built as a module. If so, the module will be
1219
+
called ti-ads7924.
1220
+
1221
1221
config TI_ADS7950
1222
1222
tristate "Texas Instruments ADS7950 ADC driver"
1223
1223
depends on SPI && GPIOLIB
···
1295
1273
1296
1274
To compile this driver as a module, choose M here: the module will be
1297
1275
called ti_am335x_adc.
1276
+
1277
+
config TI_LMP92064
1278
+
tristate "Texas Instruments LMP92064 ADC driver"
1279
+
depends on SPI
1280
+
help
1281
+
Say yes here to build support for the LMP92064 Precision Current and Voltage
1282
+
sensor.
1283
+
1284
+
This driver can also be built as a module. If so, the module will be called
1285
+
ti-lmp92064.
1298
1286
1299
1287
config TI_TLC4541
1300
1288
tristate "Texas Instruments TLC4541 ADC driver"
+3
drivers/iio/adc/Makefile
+3
drivers/iio/adc/Makefile
···
49
49
obj-$(CONFIG_HX711) += hx711.o
50
50
obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o
51
51
obj-$(CONFIG_IMX8QXP_ADC) += imx8qxp-adc.o
52
+
obj-$(CONFIG_IMX93_ADC) += imx93_adc.o
52
53
obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o
53
54
obj-$(CONFIG_INGENIC_ADC) += ingenic-adc.o
54
55
obj-$(CONFIG_INTEL_MRFLD_ADC) += intel_mrfld_adc.o
···
108
107
obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
109
108
obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o
110
109
obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o
110
+
obj-$(CONFIG_TI_ADS7924) += ti-ads7924.o
111
111
obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o
112
112
obj-$(CONFIG_TI_ADS8344) += ti-ads8344.o
113
113
obj-$(CONFIG_TI_ADS8688) += ti-ads8688.o
114
114
obj-$(CONFIG_TI_ADS124S08) += ti-ads124s08.o
115
115
obj-$(CONFIG_TI_ADS131E08) += ti-ads131e08.o
116
116
obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o
117
+
obj-$(CONFIG_TI_LMP92064) += ti-lmp92064.o
117
118
obj-$(CONFIG_TI_TLC4541) += ti-tlc4541.o
118
119
obj-$(CONFIG_TI_TSC2046) += ti-tsc2046.o
119
120
obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o
+1
-1
drivers/iio/adc/ad7291.c
+1
-1
drivers/iio/adc/ad7291.c
+2
-2
drivers/iio/adc/at91-sama5d2_adc.c
+2
-2
drivers/iio/adc/at91-sama5d2_adc.c
···
2181
2181
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
2182
2182
struct at91_adc_state *st = iio_priv(indio_dev);
2183
2183
2184
-
return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
2184
+
return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan);
2185
2185
}
2186
2186
2187
2187
static ssize_t at91_adc_get_watermark(struct device *dev,
···
2190
2190
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
2191
2191
struct at91_adc_state *st = iio_priv(indio_dev);
2192
2192
2193
-
return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
2193
+
return sysfs_emit(buf, "%d\n", st->dma_st.watermark);
2194
2194
}
2195
2195
2196
2196
static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
+8
drivers/iio/adc/ep93xx_adc.c
+8
drivers/iio/adc/ep93xx_adc.c
···
21
21
#include <linux/module.h>
22
22
#include <linux/mutex.h>
23
23
#include <linux/platform_device.h>
24
+
#include <linux/of.h>
24
25
25
26
/*
26
27
* This code could benefit from real HR Timers, but jiffy granularity would
···
228
227
return 0;
229
228
}
230
229
230
+
static const struct of_device_id ep93xx_adc_of_ids[] = {
231
+
{ .compatible = "cirrus,ep9301-adc" },
232
+
{}
233
+
};
234
+
MODULE_DEVICE_TABLE(of, ep93xx_adc_of_ids);
235
+
231
236
static struct platform_driver ep93xx_adc_driver = {
232
237
.driver = {
233
238
.name = "ep93xx-adc",
239
+
.of_match_table = ep93xx_adc_of_ids,
234
240
},
235
241
.probe = ep93xx_adc_probe,
236
242
.remove = ep93xx_adc_remove,
+484
drivers/iio/adc/imx93_adc.c
+484
drivers/iio/adc/imx93_adc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* NXP i.MX93 ADC driver
4
+
*
5
+
* Copyright 2023 NXP
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/clk.h>
10
+
#include <linux/completion.h>
11
+
#include <linux/err.h>
12
+
#include <linux/iio/iio.h>
13
+
#include <linux/interrupt.h>
14
+
#include <linux/io.h>
15
+
#include <linux/iopoll.h>
16
+
#include <linux/mod_devicetable.h>
17
+
#include <linux/module.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/pm_runtime.h>
20
+
#include <linux/regulator/consumer.h>
21
+
22
+
#define IMX93_ADC_DRIVER_NAME "imx93-adc"
23
+
24
+
/* Register map definition */
25
+
#define IMX93_ADC_MCR 0x00
26
+
#define IMX93_ADC_MSR 0x04
27
+
#define IMX93_ADC_ISR 0x10
28
+
#define IMX93_ADC_IMR 0x20
29
+
#define IMX93_ADC_CIMR0 0x24
30
+
#define IMX93_ADC_CTR0 0x94
31
+
#define IMX93_ADC_NCMR0 0xA4
32
+
#define IMX93_ADC_PCDR0 0x100
33
+
#define IMX93_ADC_PCDR1 0x104
34
+
#define IMX93_ADC_PCDR2 0x108
35
+
#define IMX93_ADC_PCDR3 0x10c
36
+
#define IMX93_ADC_PCDR4 0x110
37
+
#define IMX93_ADC_PCDR5 0x114
38
+
#define IMX93_ADC_PCDR6 0x118
39
+
#define IMX93_ADC_PCDR7 0x11c
40
+
#define IMX93_ADC_CALSTAT 0x39C
41
+
42
+
/* ADC bit shift */
43
+
#define IMX93_ADC_MCR_MODE_MASK BIT(29)
44
+
#define IMX93_ADC_MCR_NSTART_MASK BIT(24)
45
+
#define IMX93_ADC_MCR_CALSTART_MASK BIT(14)
46
+
#define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8)
47
+
#define IMX93_ADC_MCR_PWDN_MASK BIT(0)
48
+
#define IMX93_ADC_MSR_CALFAIL_MASK BIT(30)
49
+
#define IMX93_ADC_MSR_CALBUSY_MASK BIT(29)
50
+
#define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0)
51
+
#define IMX93_ADC_ISR_ECH_MASK BIT(0)
52
+
#define IMX93_ADC_ISR_EOC_MASK BIT(1)
53
+
#define IMX93_ADC_ISR_EOC_ECH_MASK (IMX93_ADC_ISR_EOC_MASK | \
54
+
IMX93_ADC_ISR_ECH_MASK)
55
+
#define IMX93_ADC_IMR_JEOC_MASK BIT(3)
56
+
#define IMX93_ADC_IMR_JECH_MASK BIT(2)
57
+
#define IMX93_ADC_IMR_EOC_MASK BIT(1)
58
+
#define IMX93_ADC_IMR_ECH_MASK BIT(0)
59
+
#define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0)
60
+
61
+
/* ADC status */
62
+
#define IMX93_ADC_MSR_ADCSTATUS_IDLE 0
63
+
#define IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN 1
64
+
#define IMX93_ADC_MSR_ADCSTATUS_WAIT_STATE 2
65
+
#define IMX93_ADC_MSR_ADCSTATUS_BUSY_IN_CALIBRATION 3
66
+
#define IMX93_ADC_MSR_ADCSTATUS_SAMPLE 4
67
+
#define IMX93_ADC_MSR_ADCSTATUS_CONVERSION 6
68
+
69
+
#define IMX93_ADC_TIMEOUT msecs_to_jiffies(100)
70
+
71
+
struct imx93_adc {
72
+
struct device *dev;
73
+
void __iomem *regs;
74
+
struct clk *ipg_clk;
75
+
int irq;
76
+
struct regulator *vref;
77
+
/* lock to protect against multiple access to the device */
78
+
struct mutex lock;
79
+
struct completion completion;
80
+
};
81
+
82
+
#define IMX93_ADC_CHAN(_idx) { \
83
+
.type = IIO_VOLTAGE, \
84
+
.indexed = 1, \
85
+
.channel = (_idx), \
86
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
87
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
88
+
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
89
+
}
90
+
91
+
static const struct iio_chan_spec imx93_adc_iio_channels[] = {
92
+
IMX93_ADC_CHAN(0),
93
+
IMX93_ADC_CHAN(1),
94
+
IMX93_ADC_CHAN(2),
95
+
IMX93_ADC_CHAN(3),
96
+
};
97
+
98
+
static void imx93_adc_power_down(struct imx93_adc *adc)
99
+
{
100
+
u32 mcr, msr;
101
+
int ret;
102
+
103
+
mcr = readl(adc->regs + IMX93_ADC_MCR);
104
+
mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
105
+
writel(mcr, adc->regs + IMX93_ADC_MCR);
106
+
107
+
ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
108
+
((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) ==
109
+
IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN),
110
+
1, 50);
111
+
if (ret == -ETIMEDOUT)
112
+
dev_warn(adc->dev,
113
+
"ADC do not in power down mode, current MSR is %x\n",
114
+
msr);
115
+
}
116
+
117
+
static void imx93_adc_power_up(struct imx93_adc *adc)
118
+
{
119
+
u32 mcr;
120
+
121
+
/* bring ADC out of power down state, in idle state */
122
+
mcr = readl(adc->regs + IMX93_ADC_MCR);
123
+
mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
124
+
writel(mcr, adc->regs + IMX93_ADC_MCR);
125
+
}
126
+
127
+
static void imx93_adc_config_ad_clk(struct imx93_adc *adc)
128
+
{
129
+
u32 mcr;
130
+
131
+
/* put adc in power down mode */
132
+
imx93_adc_power_down(adc);
133
+
134
+
/* config the AD_CLK equal to bus clock */
135
+
mcr = readl(adc->regs + IMX93_ADC_MCR);
136
+
mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
137
+
writel(mcr, adc->regs + IMX93_ADC_MCR);
138
+
139
+
imx93_adc_power_up(adc);
140
+
}
141
+
142
+
static int imx93_adc_calibration(struct imx93_adc *adc)
143
+
{
144
+
u32 mcr, msr;
145
+
int ret;
146
+
147
+
/* make sure ADC in power down mode */
148
+
imx93_adc_power_down(adc);
149
+
150
+
/* config SAR controller operating clock */
151
+
mcr = readl(adc->regs + IMX93_ADC_MCR);
152
+
mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
153
+
writel(mcr, adc->regs + IMX93_ADC_MCR);
154
+
155
+
imx93_adc_power_up(adc);
156
+
157
+
/*
158
+
* TODO: we use the default TSAMP/NRSMPL/AVGEN in MCR,
159
+
* can add the setting of these bit if need in future.
160
+
*/
161
+
162
+
/* run calibration */
163
+
mcr = readl(adc->regs + IMX93_ADC_MCR);
164
+
mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1);
165
+
writel(mcr, adc->regs + IMX93_ADC_MCR);
166
+
167
+
/* wait calibration to be finished */
168
+
ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
169
+
!(msr & IMX93_ADC_MSR_CALBUSY_MASK), 1000, 2000000);
170
+
if (ret == -ETIMEDOUT) {
171
+
dev_warn(adc->dev, "ADC do not finish calibration in 2 min!\n");
172
+
imx93_adc_power_down(adc);
173
+
return ret;
174
+
}
175
+
176
+
/* check whether calbration is success or not */
177
+
msr = readl(adc->regs + IMX93_ADC_MSR);
178
+
if (msr & IMX93_ADC_MSR_CALFAIL_MASK) {
179
+
dev_warn(adc->dev, "ADC calibration failed!\n");
180
+
imx93_adc_power_down(adc);
181
+
return -EAGAIN;
182
+
}
183
+
184
+
return 0;
185
+
}
186
+
187
+
static int imx93_adc_read_channel_conversion(struct imx93_adc *adc,
188
+
int channel_number,
189
+
int *result)
190
+
{
191
+
u32 channel;
192
+
u32 imr, mcr, pcda;
193
+
long ret;
194
+
195
+
reinit_completion(&adc->completion);
196
+
197
+
/* config channel mask register */
198
+
channel = 1 << channel_number;
199
+
writel(channel, adc->regs + IMX93_ADC_NCMR0);
200
+
201
+
/* TODO: can config desired sample time in CTRn if need */
202
+
203
+
/* config interrupt mask */
204
+
imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1);
205
+
writel(imr, adc->regs + IMX93_ADC_IMR);
206
+
writel(channel, adc->regs + IMX93_ADC_CIMR0);
207
+
208
+
/* config one-shot mode */
209
+
mcr = readl(adc->regs + IMX93_ADC_MCR);
210
+
mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1);
211
+
writel(mcr, adc->regs + IMX93_ADC_MCR);
212
+
213
+
/* start normal conversion */
214
+
mcr = readl(adc->regs + IMX93_ADC_MCR);
215
+
mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1);
216
+
writel(mcr, adc->regs + IMX93_ADC_MCR);
217
+
218
+
ret = wait_for_completion_interruptible_timeout(&adc->completion,
219
+
IMX93_ADC_TIMEOUT);
220
+
if (ret == 0)
221
+
return -ETIMEDOUT;
222
+
223
+
if (ret < 0)
224
+
return ret;
225
+
226
+
pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel_number * 4);
227
+
228
+
*result = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda);
229
+
230
+
return ret;
231
+
}
232
+
233
+
static int imx93_adc_read_raw(struct iio_dev *indio_dev,
234
+
struct iio_chan_spec const *chan,
235
+
int *val, int *val2, long mask)
236
+
{
237
+
struct imx93_adc *adc = iio_priv(indio_dev);
238
+
struct device *dev = adc->dev;
239
+
long ret;
240
+
u32 vref_uv;
241
+
242
+
switch (mask) {
243
+
case IIO_CHAN_INFO_RAW:
244
+
pm_runtime_get_sync(dev);
245
+
mutex_lock(&adc->lock);
246
+
ret = imx93_adc_read_channel_conversion(adc, chan->channel, val);
247
+
mutex_unlock(&adc->lock);
248
+
pm_runtime_mark_last_busy(dev);
249
+
pm_runtime_put_sync_autosuspend(dev);
250
+
if (ret < 0)
251
+
return ret;
252
+
253
+
return IIO_VAL_INT;
254
+
255
+
case IIO_CHAN_INFO_SCALE:
256
+
ret = vref_uv = regulator_get_voltage(adc->vref);
257
+
if (ret < 0)
258
+
return ret;
259
+
*val = vref_uv / 1000;
260
+
*val2 = 12;
261
+
return IIO_VAL_FRACTIONAL_LOG2;
262
+
263
+
case IIO_CHAN_INFO_SAMP_FREQ:
264
+
*val = clk_get_rate(adc->ipg_clk);
265
+
return IIO_VAL_INT;
266
+
267
+
default:
268
+
return -EINVAL;
269
+
}
270
+
}
271
+
272
+
static irqreturn_t imx93_adc_isr(int irq, void *dev_id)
273
+
{
274
+
struct imx93_adc *adc = dev_id;
275
+
u32 isr, eoc, unexpected;
276
+
277
+
isr = readl(adc->regs + IMX93_ADC_ISR);
278
+
279
+
if (FIELD_GET(IMX93_ADC_ISR_EOC_ECH_MASK, isr)) {
280
+
eoc = isr & IMX93_ADC_ISR_EOC_ECH_MASK;
281
+
writel(eoc, adc->regs + IMX93_ADC_ISR);
282
+
complete(&adc->completion);
283
+
}
284
+
285
+
unexpected = isr & ~IMX93_ADC_ISR_EOC_ECH_MASK;
286
+
if (unexpected) {
287
+
writel(unexpected, adc->regs + IMX93_ADC_ISR);
288
+
dev_err(adc->dev, "Unexpected interrupt 0x%08x.\n", unexpected);
289
+
return IRQ_NONE;
290
+
}
291
+
292
+
return IRQ_HANDLED;
293
+
}
294
+
295
+
static const struct iio_info imx93_adc_iio_info = {
296
+
.read_raw = &imx93_adc_read_raw,
297
+
};
298
+
299
+
static int imx93_adc_probe(struct platform_device *pdev)
300
+
{
301
+
struct imx93_adc *adc;
302
+
struct iio_dev *indio_dev;
303
+
struct device *dev = &pdev->dev;
304
+
int ret;
305
+
306
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
307
+
if (!indio_dev)
308
+
return dev_err_probe(dev, -ENOMEM,
309
+
"Failed allocating iio device\n");
310
+
311
+
adc = iio_priv(indio_dev);
312
+
adc->dev = dev;
313
+
314
+
mutex_init(&adc->lock);
315
+
adc->regs = devm_platform_ioremap_resource(pdev, 0);
316
+
if (IS_ERR(adc->regs))
317
+
return dev_err_probe(dev, PTR_ERR(adc->regs),
318
+
"Failed getting ioremap resource\n");
319
+
320
+
/* The third irq is for ADC conversion usage */
321
+
adc->irq = platform_get_irq(pdev, 2);
322
+
if (adc->irq < 0)
323
+
return adc->irq;
324
+
325
+
adc->ipg_clk = devm_clk_get(dev, "ipg");
326
+
if (IS_ERR(adc->ipg_clk))
327
+
return dev_err_probe(dev, PTR_ERR(adc->ipg_clk),
328
+
"Failed getting clock.\n");
329
+
330
+
adc->vref = devm_regulator_get(dev, "vref");
331
+
if (IS_ERR(adc->vref))
332
+
return dev_err_probe(dev, PTR_ERR(adc->vref),
333
+
"Failed getting reference voltage.\n");
334
+
335
+
ret = regulator_enable(adc->vref);
336
+
if (ret)
337
+
return dev_err_probe(dev, ret,
338
+
"Failed to enable reference voltage.\n");
339
+
340
+
platform_set_drvdata(pdev, indio_dev);
341
+
342
+
init_completion(&adc->completion);
343
+
344
+
indio_dev->name = "imx93-adc";
345
+
indio_dev->info = &imx93_adc_iio_info;
346
+
indio_dev->modes = INDIO_DIRECT_MODE;
347
+
indio_dev->channels = imx93_adc_iio_channels;
348
+
indio_dev->num_channels = ARRAY_SIZE(imx93_adc_iio_channels);
349
+
350
+
ret = clk_prepare_enable(adc->ipg_clk);
351
+
if (ret) {
352
+
dev_err_probe(dev, ret,
353
+
"Failed to enable ipg clock.\n");
354
+
goto error_regulator_disable;
355
+
}
356
+
357
+
ret = request_irq(adc->irq, imx93_adc_isr, 0, IMX93_ADC_DRIVER_NAME, adc);
358
+
if (ret < 0) {
359
+
dev_err_probe(dev, ret,
360
+
"Failed requesting irq, irq = %d\n", adc->irq);
361
+
goto error_ipg_clk_disable;
362
+
}
363
+
364
+
ret = imx93_adc_calibration(adc);
365
+
if (ret < 0)
366
+
goto error_free_adc_irq;
367
+
368
+
imx93_adc_config_ad_clk(adc);
369
+
370
+
ret = iio_device_register(indio_dev);
371
+
if (ret) {
372
+
dev_err_probe(dev, ret,
373
+
"Failed to register this iio device.\n");
374
+
goto error_adc_power_down;
375
+
}
376
+
377
+
pm_runtime_set_active(dev);
378
+
pm_runtime_set_autosuspend_delay(dev, 50);
379
+
pm_runtime_use_autosuspend(dev);
380
+
pm_runtime_enable(dev);
381
+
382
+
return 0;
383
+
384
+
error_adc_power_down:
385
+
imx93_adc_power_down(adc);
386
+
error_free_adc_irq:
387
+
free_irq(adc->irq, adc);
388
+
error_ipg_clk_disable:
389
+
clk_disable_unprepare(adc->ipg_clk);
390
+
error_regulator_disable:
391
+
regulator_disable(adc->vref);
392
+
393
+
return ret;
394
+
}
395
+
396
+
static int imx93_adc_remove(struct platform_device *pdev)
397
+
{
398
+
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
399
+
struct imx93_adc *adc = iio_priv(indio_dev);
400
+
struct device *dev = adc->dev;
401
+
402
+
/* adc power down need clock on */
403
+
pm_runtime_get_sync(dev);
404
+
405
+
pm_runtime_disable(dev);
406
+
pm_runtime_dont_use_autosuspend(dev);
407
+
pm_runtime_put_noidle(dev);
408
+
409
+
iio_device_unregister(indio_dev);
410
+
imx93_adc_power_down(adc);
411
+
free_irq(adc->irq, adc);
412
+
clk_disable_unprepare(adc->ipg_clk);
413
+
regulator_disable(adc->vref);
414
+
415
+
return 0;
416
+
}
417
+
418
+
static int imx93_adc_runtime_suspend(struct device *dev)
419
+
{
420
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
421
+
struct imx93_adc *adc = iio_priv(indio_dev);
422
+
423
+
imx93_adc_power_down(adc);
424
+
clk_disable_unprepare(adc->ipg_clk);
425
+
regulator_disable(adc->vref);
426
+
427
+
return 0;
428
+
}
429
+
430
+
static int imx93_adc_runtime_resume(struct device *dev)
431
+
{
432
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
433
+
struct imx93_adc *adc = iio_priv(indio_dev);
434
+
int ret;
435
+
436
+
ret = regulator_enable(adc->vref);
437
+
if (ret) {
438
+
dev_err(dev,
439
+
"Can't enable adc reference top voltage, err = %d\n",
440
+
ret);
441
+
return ret;
442
+
}
443
+
444
+
ret = clk_prepare_enable(adc->ipg_clk);
445
+
if (ret) {
446
+
dev_err(dev, "Could not prepare or enable clock.\n");
447
+
goto err_disable_reg;
448
+
}
449
+
450
+
imx93_adc_power_up(adc);
451
+
452
+
return 0;
453
+
454
+
err_disable_reg:
455
+
regulator_disable(adc->vref);
456
+
457
+
return ret;
458
+
}
459
+
460
+
static DEFINE_RUNTIME_DEV_PM_OPS(imx93_adc_pm_ops,
461
+
imx93_adc_runtime_suspend,
462
+
imx93_adc_runtime_resume, NULL);
463
+
464
+
static const struct of_device_id imx93_adc_match[] = {
465
+
{ .compatible = "nxp,imx93-adc", },
466
+
{ /* sentinel */ }
467
+
};
468
+
MODULE_DEVICE_TABLE(of, imx93_adc_match);
469
+
470
+
static struct platform_driver imx93_adc_driver = {
471
+
.probe = imx93_adc_probe,
472
+
.remove = imx93_adc_remove,
473
+
.driver = {
474
+
.name = IMX93_ADC_DRIVER_NAME,
475
+
.of_match_table = imx93_adc_match,
476
+
.pm = pm_ptr(&imx93_adc_pm_ops),
477
+
},
478
+
};
479
+
480
+
module_platform_driver(imx93_adc_driver);
481
+
482
+
MODULE_DESCRIPTION("NXP i.MX93 ADC driver");
483
+
MODULE_AUTHOR("Haibo Chen <haibo.chen@nxp.com>");
484
+
MODULE_LICENSE("GPL");
+2
-1
drivers/iio/adc/max11410.c
+2
-1
drivers/iio/adc/max11410.c
···
4
4
*
5
5
* Copyright 2022 Analog Devices Inc.
6
6
*/
7
-
#include <asm-generic/unaligned.h>
8
7
#include <linux/bitfield.h>
9
8
#include <linux/delay.h>
10
9
#include <linux/device.h>
···
14
15
#include <linux/regmap.h>
15
16
#include <linux/regulator/consumer.h>
16
17
#include <linux/spi/spi.h>
18
+
19
+
#include <asm/unaligned.h>
17
20
18
21
#include <linux/iio/buffer.h>
19
22
#include <linux/iio/sysfs.h>
+4
-4
drivers/iio/adc/qcom-spmi-adc5.c
+4
-4
drivers/iio/adc/qcom-spmi-adc5.c
···
543
543
SCALE_HW_CALIB_DEFAULT)
544
544
[ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
545
545
SCALE_HW_CALIB_XOTHERM)
546
+
[ADC5_BAT_ID_100K_PU] = ADC5_CHAN_TEMP("bat_id", 0,
547
+
SCALE_HW_CALIB_DEFAULT)
546
548
[ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
547
549
SCALE_HW_CALIB_THERM_100K_PULLUP)
548
550
[ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
···
896
894
mutex_init(&adc->lock);
897
895
898
896
ret = adc5_get_fw_data(adc);
899
-
if (ret) {
900
-
dev_err(dev, "adc get dt data failed\n");
901
-
return ret;
902
-
}
897
+
if (ret)
898
+
return dev_err_probe(dev, ret, "adc get dt data failed\n");
903
899
904
900
irq_eoc = platform_get_irq(pdev, 0);
905
901
if (irq_eoc < 0) {
+83
-16
drivers/iio/adc/stm32-dfsdm-core.c
+83
-16
drivers/iio/adc/stm32-dfsdm-core.c
···
6
6
* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
7
7
*/
8
8
9
+
#include <linux/bitfield.h>
9
10
#include <linux/clk.h>
10
11
#include <linux/iio/iio.h>
11
12
#include <linux/iio/sysfs.h>
···
20
19
21
20
#include "stm32-dfsdm.h"
22
21
22
+
/**
23
+
* struct stm32_dfsdm_dev_data - DFSDM compatible configuration data
24
+
* @ipid: DFSDM identification number. Used only if hardware provides identification registers
25
+
* @num_filters: DFSDM number of filters. Unused if identification registers are available
26
+
* @num_channels: DFSDM number of channels. Unused if identification registers are available
27
+
* @regmap_cfg: SAI register map configuration pointer
28
+
*/
23
29
struct stm32_dfsdm_dev_data {
30
+
u32 ipid;
24
31
unsigned int num_filters;
25
32
unsigned int num_channels;
26
33
const struct regmap_config *regmap_cfg;
···
36
27
37
28
#define STM32H7_DFSDM_NUM_FILTERS 4
38
29
#define STM32H7_DFSDM_NUM_CHANNELS 8
39
-
#define STM32MP1_DFSDM_NUM_FILTERS 6
40
-
#define STM32MP1_DFSDM_NUM_CHANNELS 8
41
30
42
31
static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
43
32
{
···
82
75
};
83
76
84
77
static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
85
-
.num_filters = STM32MP1_DFSDM_NUM_FILTERS,
86
-
.num_channels = STM32MP1_DFSDM_NUM_CHANNELS,
78
+
.ipid = STM32MP15_IPIDR_NUMBER,
87
79
.regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
88
80
};
89
81
···
301
295
};
302
296
MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
303
297
298
+
static int stm32_dfsdm_probe_identification(struct platform_device *pdev,
299
+
struct dfsdm_priv *priv,
300
+
const struct stm32_dfsdm_dev_data *dev_data)
301
+
{
302
+
struct device_node *np = pdev->dev.of_node;
303
+
struct device_node *child;
304
+
struct stm32_dfsdm *dfsdm = &priv->dfsdm;
305
+
const char *compat;
306
+
int ret, count = 0;
307
+
u32 id, val;
308
+
309
+
if (!dev_data->ipid) {
310
+
dfsdm->num_fls = dev_data->num_filters;
311
+
dfsdm->num_chs = dev_data->num_channels;
312
+
return 0;
313
+
}
314
+
315
+
ret = regmap_read(dfsdm->regmap, DFSDM_IPIDR, &id);
316
+
if (ret)
317
+
return ret;
318
+
319
+
if (id != dev_data->ipid) {
320
+
dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id);
321
+
return -EINVAL;
322
+
}
323
+
324
+
for_each_child_of_node(np, child) {
325
+
ret = of_property_read_string(child, "compatible", &compat);
326
+
if (ret)
327
+
continue;
328
+
/* Count only child nodes with dfsdm compatible */
329
+
if (strstr(compat, "dfsdm"))
330
+
count++;
331
+
}
332
+
333
+
ret = regmap_read(dfsdm->regmap, DFSDM_HWCFGR, &val);
334
+
if (ret)
335
+
return ret;
336
+
337
+
dfsdm->num_fls = FIELD_GET(DFSDM_HWCFGR_NBF_MASK, val);
338
+
dfsdm->num_chs = FIELD_GET(DFSDM_HWCFGR_NBT_MASK, val);
339
+
340
+
if (count > dfsdm->num_fls) {
341
+
dev_err(&pdev->dev, "Unexpected child number: %d", count);
342
+
return -EINVAL;
343
+
}
344
+
345
+
ret = regmap_read(dfsdm->regmap, DFSDM_VERR, &val);
346
+
if (ret)
347
+
return ret;
348
+
349
+
dev_dbg(&pdev->dev, "DFSDM version: %lu.%lu. %d channels/%d filters\n",
350
+
FIELD_GET(DFSDM_VERR_MAJREV_MASK, val),
351
+
FIELD_GET(DFSDM_VERR_MINREV_MASK, val),
352
+
dfsdm->num_chs, dfsdm->num_fls);
353
+
354
+
return 0;
355
+
}
356
+
304
357
static int stm32_dfsdm_probe(struct platform_device *pdev)
305
358
{
306
359
struct dfsdm_priv *priv;
···
376
311
dev_data = of_device_get_match_data(&pdev->dev);
377
312
378
313
dfsdm = &priv->dfsdm;
379
-
dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
380
-
sizeof(*dfsdm->fl_list), GFP_KERNEL);
381
-
if (!dfsdm->fl_list)
382
-
return -ENOMEM;
383
-
384
-
dfsdm->num_fls = dev_data->num_filters;
385
-
dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
386
-
sizeof(*dfsdm->ch_list),
387
-
GFP_KERNEL);
388
-
if (!dfsdm->ch_list)
389
-
return -ENOMEM;
390
-
dfsdm->num_chs = dev_data->num_channels;
391
314
392
315
ret = stm32_dfsdm_parse_of(pdev, priv);
393
316
if (ret < 0)
···
390
337
__func__, ret);
391
338
return ret;
392
339
}
340
+
341
+
ret = stm32_dfsdm_probe_identification(pdev, priv, dev_data);
342
+
if (ret < 0)
343
+
return ret;
344
+
345
+
dfsdm->fl_list = devm_kcalloc(&pdev->dev, dfsdm->num_fls,
346
+
sizeof(*dfsdm->fl_list), GFP_KERNEL);
347
+
if (!dfsdm->fl_list)
348
+
return -ENOMEM;
349
+
350
+
dfsdm->ch_list = devm_kcalloc(&pdev->dev, dfsdm->num_chs,
351
+
sizeof(*dfsdm->ch_list), GFP_KERNEL);
352
+
if (!dfsdm->ch_list)
353
+
return -ENOMEM;
393
354
394
355
platform_set_drvdata(pdev, dfsdm);
395
356
+41
-19
drivers/iio/adc/stm32-dfsdm.h
+41
-19
drivers/iio/adc/stm32-dfsdm.h
···
13
13
14
14
/*
15
15
* STM32 DFSDM - global register map
16
-
* ________________________________________________________
17
-
* | Offset | Registers block |
18
-
* --------------------------------------------------------
19
-
* | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
20
-
* --------------------------------------------------------
21
-
* | 0x020 | CHANNEL 1 |
22
-
* --------------------------------------------------------
23
-
* | ... | ..... |
24
-
* --------------------------------------------------------
25
-
* | 0x0E0 | CHANNEL 7 |
26
-
* --------------------------------------------------------
27
-
* | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
28
-
* --------------------------------------------------------
29
-
* | 0x200 | FILTER 1 |
30
-
* --------------------------------------------------------
31
-
* | 0x300 | FILTER 2 |
32
-
* --------------------------------------------------------
33
-
* | 0x400 | FILTER 3 |
34
-
* --------------------------------------------------------
16
+
* __________________________________________________________
17
+
* | Offset | Registers block |
18
+
* ----------------------------------------------------------
19
+
* | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
20
+
* ----------------------------------------------------------
21
+
* | 0x020 | CHANNEL 1 |
22
+
* ----------------------------------------------------------
23
+
* | ... | ..... |
24
+
* ----------------------------------------------------------
25
+
* | 0x20 x n | CHANNEL n |
26
+
* ----------------------------------------------------------
27
+
* | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
28
+
* ----------------------------------------------------------
29
+
* | 0x200 | FILTER 1 |
30
+
* ----------------------------------------------------------
31
+
* | | ..... |
32
+
* ----------------------------------------------------------
33
+
* | 0x100 x m | FILTER m |
34
+
* ----------------------------------------------------------
35
+
* | | ..... |
36
+
* ----------------------------------------------------------
37
+
* | 0x7F0-7FC | Identification registers |
38
+
* ----------------------------------------------------------
35
39
*/
36
40
37
41
/*
···
234
230
#define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
235
231
#define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)
236
232
#define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
233
+
234
+
/*
235
+
* Identification register definitions
236
+
*/
237
+
#define DFSDM_HWCFGR 0x7F0
238
+
#define DFSDM_VERR 0x7F4
239
+
#define DFSDM_IPIDR 0x7F8
240
+
#define DFSDM_SIDR 0x7FC
241
+
242
+
/* HWCFGR: Hardware configuration register */
243
+
#define DFSDM_HWCFGR_NBT_MASK GENMASK(7, 0)
244
+
#define DFSDM_HWCFGR_NBF_MASK GENMASK(15, 8)
245
+
246
+
/* VERR: Version register */
247
+
#define DFSDM_VERR_MINREV_MASK GENMASK(3, 0)
248
+
#define DFSDM_VERR_MAJREV_MASK GENMASK(7, 4)
249
+
250
+
#define STM32MP15_IPIDR_NUMBER 0x00110031
237
251
238
252
/* DFSDM filter order */
239
253
enum stm32_dfsdm_sinc_order {
+24
-30
drivers/iio/adc/ti-adc128s052.c
+24
-30
drivers/iio/adc/ti-adc128s052.c
···
9
9
* https://www.ti.com/lit/ds/symlink/adc124s021.pdf
10
10
*/
11
11
12
-
#include <linux/acpi.h>
13
12
#include <linux/err.h>
14
-
#include <linux/spi/spi.h>
15
-
#include <linux/module.h>
16
-
#include <linux/mod_devicetable.h>
17
13
#include <linux/iio/iio.h>
14
+
#include <linux/mod_devicetable.h>
15
+
#include <linux/module.h>
18
16
#include <linux/property.h>
19
17
#include <linux/regulator/consumer.h>
18
+
#include <linux/spi/spi.h>
20
19
21
20
struct adc128_configuration {
22
21
const struct iio_chan_spec *channels;
···
138
139
139
140
static int adc128_probe(struct spi_device *spi)
140
141
{
142
+
const struct adc128_configuration *config;
141
143
struct iio_dev *indio_dev;
142
-
unsigned int config;
143
144
struct adc128 *adc;
144
145
int ret;
145
-
146
-
if (dev_fwnode(&spi->dev))
147
-
config = (unsigned long) device_get_match_data(&spi->dev);
148
-
else
149
-
config = spi_get_device_id(spi)->driver_data;
150
146
151
147
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
152
148
if (!indio_dev)
···
154
160
indio_dev->modes = INDIO_DIRECT_MODE;
155
161
indio_dev->info = &adc128_info;
156
162
157
-
indio_dev->channels = adc128_config[config].channels;
158
-
indio_dev->num_channels = adc128_config[config].num_channels;
163
+
config = spi_get_device_match_data(spi);
164
+
165
+
indio_dev->channels = config->channels;
166
+
indio_dev->num_channels = config->num_channels;
159
167
160
168
adc->reg = devm_regulator_get(&spi->dev, "vref");
161
169
if (IS_ERR(adc->reg))
···
177
181
}
178
182
179
183
static const struct of_device_id adc128_of_match[] = {
180
-
{ .compatible = "ti,adc128s052", .data = (void*)0L, },
181
-
{ .compatible = "ti,adc122s021", .data = (void*)1L, },
182
-
{ .compatible = "ti,adc122s051", .data = (void*)1L, },
183
-
{ .compatible = "ti,adc122s101", .data = (void*)1L, },
184
-
{ .compatible = "ti,adc124s021", .data = (void*)2L, },
185
-
{ .compatible = "ti,adc124s051", .data = (void*)2L, },
186
-
{ .compatible = "ti,adc124s101", .data = (void*)2L, },
184
+
{ .compatible = "ti,adc128s052", .data = &adc128_config[0] },
185
+
{ .compatible = "ti,adc122s021", .data = &adc128_config[1] },
186
+
{ .compatible = "ti,adc122s051", .data = &adc128_config[1] },
187
+
{ .compatible = "ti,adc122s101", .data = &adc128_config[1] },
188
+
{ .compatible = "ti,adc124s021", .data = &adc128_config[2] },
189
+
{ .compatible = "ti,adc124s051", .data = &adc128_config[2] },
190
+
{ .compatible = "ti,adc124s101", .data = &adc128_config[2] },
187
191
{ /* sentinel */ },
188
192
};
189
193
MODULE_DEVICE_TABLE(of, adc128_of_match);
190
194
191
195
static const struct spi_device_id adc128_id[] = {
192
-
{ "adc128s052", 0 }, /* index into adc128_config */
193
-
{ "adc122s021", 1 },
194
-
{ "adc122s051", 1 },
195
-
{ "adc122s101", 1 },
196
-
{ "adc124s021", 2 },
197
-
{ "adc124s051", 2 },
198
-
{ "adc124s101", 2 },
196
+
{ "adc128s052", (kernel_ulong_t)&adc128_config[0] },
197
+
{ "adc122s021", (kernel_ulong_t)&adc128_config[1] },
198
+
{ "adc122s051", (kernel_ulong_t)&adc128_config[1] },
199
+
{ "adc122s101", (kernel_ulong_t)&adc128_config[1] },
200
+
{ "adc124s021", (kernel_ulong_t)&adc128_config[2] },
201
+
{ "adc124s051", (kernel_ulong_t)&adc128_config[2] },
202
+
{ "adc124s101", (kernel_ulong_t)&adc128_config[2] },
199
203
{ }
200
204
};
201
205
MODULE_DEVICE_TABLE(spi, adc128_id);
202
206
203
-
#ifdef CONFIG_ACPI
204
207
static const struct acpi_device_id adc128_acpi_match[] = {
205
-
{ "AANT1280", 2 }, /* ADC124S021 compatible ACPI ID */
208
+
{ "AANT1280", (kernel_ulong_t)&adc128_config[2] },
206
209
{ }
207
210
};
208
211
MODULE_DEVICE_TABLE(acpi, adc128_acpi_match);
209
-
#endif
210
212
211
213
static struct spi_driver adc128_driver = {
212
214
.driver = {
213
215
.name = "adc128s052",
214
216
.of_match_table = adc128_of_match,
215
-
.acpi_match_table = ACPI_PTR(adc128_acpi_match),
217
+
.acpi_match_table = adc128_acpi_match,
216
218
},
217
219
.probe = adc128_probe,
218
220
.id_table = adc128_id,
+474
drivers/iio/adc/ti-ads7924.c
+474
drivers/iio/adc/ti-ads7924.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* IIO driver for Texas Instruments ADS7924 ADC, 12-bit, 4-Channels, I2C
4
+
*
5
+
* Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
6
+
* Copyright 2022 DimOnOff
7
+
*
8
+
* based on iio/adc/ti-ads1015.c
9
+
* Copyright (c) 2016, Intel Corporation.
10
+
*
11
+
* Datasheet: https://www.ti.com/lit/gpn/ads7924
12
+
*/
13
+
14
+
#include <linux/bitfield.h>
15
+
#include <linux/delay.h>
16
+
#include <linux/gpio/consumer.h>
17
+
#include <linux/init.h>
18
+
#include <linux/irq.h>
19
+
#include <linux/i2c.h>
20
+
#include <linux/module.h>
21
+
#include <linux/mutex.h>
22
+
#include <linux/regmap.h>
23
+
#include <linux/regulator/consumer.h>
24
+
25
+
#include <linux/iio/iio.h>
26
+
#include <linux/iio/types.h>
27
+
28
+
#define ADS7924_CHANNELS 4
29
+
#define ADS7924_BITS 12
30
+
#define ADS7924_DATA_SHIFT 4
31
+
32
+
/* Registers. */
33
+
#define ADS7924_MODECNTRL_REG 0x00
34
+
#define ADS7924_INTCNTRL_REG 0x01
35
+
#define ADS7924_DATA0_U_REG 0x02
36
+
#define ADS7924_DATA0_L_REG 0x03
37
+
#define ADS7924_DATA1_U_REG 0x04
38
+
#define ADS7924_DATA1_L_REG 0x05
39
+
#define ADS7924_DATA2_U_REG 0x06
40
+
#define ADS7924_DATA2_L_REG 0x07
41
+
#define ADS7924_DATA3_U_REG 0x08
42
+
#define ADS7924_DATA3_L_REG 0x09
43
+
#define ADS7924_ULR0_REG 0x0A
44
+
#define ADS7924_LLR0_REG 0x0B
45
+
#define ADS7924_ULR1_REG 0x0C
46
+
#define ADS7924_LLR1_REG 0x0D
47
+
#define ADS7924_ULR2_REG 0x0E
48
+
#define ADS7924_LLR2_REG 0x0F
49
+
#define ADS7924_ULR3_REG 0x10
50
+
#define ADS7924_LLR3_REG 0x11
51
+
#define ADS7924_INTCONFIG_REG 0x12
52
+
#define ADS7924_SLPCONFIG_REG 0x13
53
+
#define ADS7924_ACQCONFIG_REG 0x14
54
+
#define ADS7924_PWRCONFIG_REG 0x15
55
+
#define ADS7924_RESET_REG 0x16
56
+
57
+
/*
58
+
* Register address INC bit: when set to '1', the register address is
59
+
* automatically incremented after every register read which allows convenient
60
+
* reading of multiple registers. Set INC to '0' when reading a single register.
61
+
*/
62
+
#define ADS7924_AUTO_INCREMENT_BIT BIT(7)
63
+
64
+
#define ADS7924_MODECNTRL_MODE_MASK GENMASK(7, 2)
65
+
66
+
#define ADS7924_MODECNTRL_SEL_MASK GENMASK(1, 0)
67
+
68
+
#define ADS7924_CFG_INTPOL_BIT 1
69
+
#define ADS7924_CFG_INTTRIG_BIT 0
70
+
71
+
#define ADS7924_CFG_INTPOL_MASK BIT(ADS7924_CFG_INTPOL_BIT)
72
+
#define ADS7924_CFG_INTTRIG_MASK BIT(ADS7924_CFG_INTTRIG_BIT)
73
+
74
+
/* Interrupt pin polarity */
75
+
#define ADS7924_CFG_INTPOL_LOW 0
76
+
#define ADS7924_CFG_INTPOL_HIGH 1
77
+
78
+
/* Interrupt pin signaling */
79
+
#define ADS7924_CFG_INTTRIG_LEVEL 0
80
+
#define ADS7924_CFG_INTTRIG_EDGE 1
81
+
82
+
/* Mode control values */
83
+
#define ADS7924_MODECNTRL_IDLE 0x00
84
+
#define ADS7924_MODECNTRL_AWAKE 0x20
85
+
#define ADS7924_MODECNTRL_MANUAL_SINGLE 0x30
86
+
#define ADS7924_MODECNTRL_MANUAL_SCAN 0x32
87
+
#define ADS7924_MODECNTRL_AUTO_SINGLE 0x31
88
+
#define ADS7924_MODECNTRL_AUTO_SCAN 0x33
89
+
#define ADS7924_MODECNTRL_AUTO_SINGLE_SLEEP 0x39
90
+
#define ADS7924_MODECNTRL_AUTO_SCAN_SLEEP 0x3B
91
+
#define ADS7924_MODECNTRL_AUTO_BURST_SLEEP 0x3F
92
+
93
+
#define ADS7924_ACQTIME_MASK GENMASK(4, 0)
94
+
95
+
#define ADS7924_PWRUPTIME_MASK GENMASK(4, 0)
96
+
97
+
/*
98
+
* The power-up time is allowed to elapse whenever the device has been shutdown
99
+
* in idle mode. Power-up time can allow external circuits, such as an
100
+
* operational amplifier, between the MUXOUT and ADCIN pins to turn on.
101
+
* The nominal time programmed by the PUTIME[4:0] register bits is given by:
102
+
* t PU = PWRUPTIME[4:0] × 2 μs
103
+
* If a power-up time is not required, set the bits to '0' to effectively bypass.
104
+
*/
105
+
#define ADS7924_PWRUPTIME_US 0 /* Bypass (0us). */
106
+
107
+
/*
108
+
* Acquisition Time according to ACQTIME[4:0] register bits.
109
+
* The Acquisition Time is given by:
110
+
* t ACQ = (ACQTIME[4:0] × 2 μs) + 6 μs
111
+
* Using default value of 0 for ACQTIME[4:0] results in a minimum acquisition
112
+
* time of 6us.
113
+
*/
114
+
#define ADS7924_ACQTIME_US 6
115
+
116
+
/* The conversion time is always 4μs and cannot be programmed by the user. */
117
+
#define ADS7924_CONVTIME_US 4
118
+
119
+
#define ADS7924_TOTAL_CONVTIME_US (ADS7924_PWRUPTIME_US + ADS7924_ACQTIME_US + \
120
+
ADS7924_CONVTIME_US)
121
+
122
+
#define ADS7924_V_CHAN(_chan, _addr) { \
123
+
.type = IIO_VOLTAGE, \
124
+
.indexed = 1, \
125
+
.channel = _chan, \
126
+
.address = _addr, \
127
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
128
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
129
+
.datasheet_name = "AIN"#_chan, \
130
+
}
131
+
132
+
struct ads7924_data {
133
+
struct device *dev;
134
+
struct regmap *regmap;
135
+
struct regulator *vref_reg;
136
+
137
+
/* GPIO descriptor for device hard-reset pin. */
138
+
struct gpio_desc *reset_gpio;
139
+
140
+
/*
141
+
* Protects ADC ops, e.g: concurrent sysfs/buffered
142
+
* data reads, configuration updates
143
+
*/
144
+
struct mutex lock;
145
+
146
+
/*
147
+
* Set to true when the ADC is switched to the continuous-conversion
148
+
* mode and exits from a power-down state. This flag is used to avoid
149
+
* getting the stale result from the conversion register.
150
+
*/
151
+
bool conv_invalid;
152
+
};
153
+
154
+
static bool ads7924_is_writeable_reg(struct device *dev, unsigned int reg)
155
+
{
156
+
switch (reg) {
157
+
case ADS7924_MODECNTRL_REG:
158
+
case ADS7924_INTCNTRL_REG:
159
+
case ADS7924_ULR0_REG:
160
+
case ADS7924_LLR0_REG:
161
+
case ADS7924_ULR1_REG:
162
+
case ADS7924_LLR1_REG:
163
+
case ADS7924_ULR2_REG:
164
+
case ADS7924_LLR2_REG:
165
+
case ADS7924_ULR3_REG:
166
+
case ADS7924_LLR3_REG:
167
+
case ADS7924_INTCONFIG_REG:
168
+
case ADS7924_SLPCONFIG_REG:
169
+
case ADS7924_ACQCONFIG_REG:
170
+
case ADS7924_PWRCONFIG_REG:
171
+
case ADS7924_RESET_REG:
172
+
return true;
173
+
default:
174
+
return false;
175
+
}
176
+
}
177
+
178
+
static const struct regmap_config ads7924_regmap_config = {
179
+
.reg_bits = 8,
180
+
.val_bits = 8,
181
+
.max_register = ADS7924_RESET_REG,
182
+
.writeable_reg = ads7924_is_writeable_reg,
183
+
};
184
+
185
+
static const struct iio_chan_spec ads7924_channels[] = {
186
+
ADS7924_V_CHAN(0, ADS7924_DATA0_U_REG),
187
+
ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG),
188
+
ADS7924_V_CHAN(2, ADS7924_DATA2_U_REG),
189
+
ADS7924_V_CHAN(3, ADS7924_DATA3_U_REG),
190
+
};
191
+
192
+
static int ads7924_get_adc_result(struct ads7924_data *data,
193
+
struct iio_chan_spec const *chan, int *val)
194
+
{
195
+
int ret;
196
+
__be16 be_val;
197
+
198
+
if (chan->channel < 0 || chan->channel >= ADS7924_CHANNELS)
199
+
return -EINVAL;
200
+
201
+
if (data->conv_invalid) {
202
+
int conv_time;
203
+
204
+
conv_time = ADS7924_TOTAL_CONVTIME_US;
205
+
/* Allow 10% for internal clock inaccuracy. */
206
+
conv_time += conv_time / 10;
207
+
usleep_range(conv_time, conv_time + 1);
208
+
data->conv_invalid = false;
209
+
}
210
+
211
+
ret = regmap_raw_read(data->regmap, ADS7924_AUTO_INCREMENT_BIT |
212
+
chan->address, &be_val, sizeof(be_val));
213
+
if (ret)
214
+
return ret;
215
+
216
+
*val = be16_to_cpu(be_val) >> ADS7924_DATA_SHIFT;
217
+
218
+
return 0;
219
+
}
220
+
221
+
static int ads7924_read_raw(struct iio_dev *indio_dev,
222
+
struct iio_chan_spec const *chan, int *val,
223
+
int *val2, long mask)
224
+
{
225
+
int ret, vref_uv;
226
+
struct ads7924_data *data = iio_priv(indio_dev);
227
+
228
+
switch (mask) {
229
+
case IIO_CHAN_INFO_RAW:
230
+
mutex_lock(&data->lock);
231
+
ret = ads7924_get_adc_result(data, chan, val);
232
+
mutex_unlock(&data->lock);
233
+
if (ret < 0)
234
+
return ret;
235
+
236
+
return IIO_VAL_INT;
237
+
case IIO_CHAN_INFO_SCALE:
238
+
vref_uv = regulator_get_voltage(data->vref_reg);
239
+
if (vref_uv < 0)
240
+
return vref_uv;
241
+
242
+
*val = vref_uv / 1000; /* Convert reg voltage to mV */
243
+
*val2 = ADS7924_BITS;
244
+
return IIO_VAL_FRACTIONAL_LOG2;
245
+
default:
246
+
return -EINVAL;
247
+
}
248
+
}
249
+
250
+
static const struct iio_info ads7924_info = {
251
+
.read_raw = ads7924_read_raw,
252
+
};
253
+
254
+
static int ads7924_get_channels_config(struct i2c_client *client,
255
+
struct iio_dev *indio_dev)
256
+
{
257
+
struct ads7924_data *priv = iio_priv(indio_dev);
258
+
struct device *dev = priv->dev;
259
+
struct fwnode_handle *node;
260
+
int num_channels = 0;
261
+
262
+
device_for_each_child_node(dev, node) {
263
+
u32 pval;
264
+
unsigned int channel;
265
+
266
+
if (fwnode_property_read_u32(node, "reg", &pval)) {
267
+
dev_err(dev, "invalid reg on %pfw\n", node);
268
+
continue;
269
+
}
270
+
271
+
channel = pval;
272
+
if (channel >= ADS7924_CHANNELS) {
273
+
dev_err(dev, "invalid channel index %d on %pfw\n",
274
+
channel, node);
275
+
continue;
276
+
}
277
+
278
+
num_channels++;
279
+
}
280
+
281
+
if (!num_channels)
282
+
return -EINVAL;
283
+
284
+
return 0;
285
+
}
286
+
287
+
static int ads7924_set_conv_mode(struct ads7924_data *data, int mode)
288
+
{
289
+
int ret;
290
+
unsigned int mode_field;
291
+
struct device *dev = data->dev;
292
+
293
+
/*
294
+
* When switching between modes, be sure to first select the Awake mode
295
+
* and then switch to the desired mode. This procedure ensures the
296
+
* internal control logic is properly synchronized.
297
+
*/
298
+
if (mode != ADS7924_MODECNTRL_IDLE) {
299
+
mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK,
300
+
ADS7924_MODECNTRL_AWAKE);
301
+
302
+
ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
303
+
ADS7924_MODECNTRL_MODE_MASK,
304
+
mode_field);
305
+
if (ret) {
306
+
dev_err(dev, "failed to set awake mode (%pe)\n",
307
+
ERR_PTR(ret));
308
+
return ret;
309
+
}
310
+
}
311
+
312
+
mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, mode);
313
+
314
+
ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
315
+
ADS7924_MODECNTRL_MODE_MASK, mode_field);
316
+
if (ret)
317
+
dev_err(dev, "failed to set mode %d (%pe)\n", mode,
318
+
ERR_PTR(ret));
319
+
320
+
return ret;
321
+
}
322
+
323
+
static int ads7924_reset(struct iio_dev *indio_dev)
324
+
{
325
+
struct ads7924_data *data = iio_priv(indio_dev);
326
+
327
+
if (data->reset_gpio) {
328
+
gpiod_set_value(data->reset_gpio, 1); /* Assert. */
329
+
/* Educated guess: assert time not specified in datasheet... */
330
+
mdelay(100);
331
+
gpiod_set_value(data->reset_gpio, 0); /* Deassert. */
332
+
return 0;
333
+
}
334
+
335
+
/*
336
+
* A write of 10101010 to this register will generate a
337
+
* software reset of the ADS7924.
338
+
*/
339
+
return regmap_write(data->regmap, ADS7924_RESET_REG, 0b10101010);
340
+
};
341
+
342
+
static void ads7924_reg_disable(void *data)
343
+
{
344
+
regulator_disable(data);
345
+
}
346
+
347
+
static void ads7924_set_idle_mode(void *data)
348
+
{
349
+
ads7924_set_conv_mode(data, ADS7924_MODECNTRL_IDLE);
350
+
}
351
+
352
+
static int ads7924_probe(struct i2c_client *client)
353
+
{
354
+
struct iio_dev *indio_dev;
355
+
struct ads7924_data *data;
356
+
struct device *dev = &client->dev;
357
+
int ret;
358
+
359
+
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
360
+
if (!indio_dev)
361
+
return dev_err_probe(dev, -ENOMEM,
362
+
"failed to allocate iio device\n");
363
+
364
+
data = iio_priv(indio_dev);
365
+
366
+
data->dev = dev;
367
+
368
+
/* Initialize the reset GPIO as output with an initial value of 0. */
369
+
data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
370
+
if (IS_ERR(data->reset_gpio))
371
+
return dev_err_probe(dev, PTR_ERR(data->reset_gpio),
372
+
"failed to get request reset GPIO\n");
373
+
374
+
mutex_init(&data->lock);
375
+
376
+
indio_dev->name = "ads7924";
377
+
indio_dev->modes = INDIO_DIRECT_MODE;
378
+
379
+
indio_dev->channels = ads7924_channels;
380
+
indio_dev->num_channels = ARRAY_SIZE(ads7924_channels);
381
+
indio_dev->info = &ads7924_info;
382
+
383
+
ret = ads7924_get_channels_config(client, indio_dev);
384
+
if (ret < 0)
385
+
return dev_err_probe(dev, ret,
386
+
"failed to get channels configuration\n");
387
+
388
+
data->regmap = devm_regmap_init_i2c(client, &ads7924_regmap_config);
389
+
if (IS_ERR(data->regmap))
390
+
return dev_err_probe(dev, PTR_ERR(data->regmap),
391
+
"failed to init regmap\n");
392
+
393
+
data->vref_reg = devm_regulator_get(dev, "vref");
394
+
if (IS_ERR(data->vref_reg))
395
+
return dev_err_probe(dev, PTR_ERR(data->vref_reg),
396
+
"failed to get vref regulator\n");
397
+
398
+
ret = regulator_enable(data->vref_reg);
399
+
if (ret)
400
+
return dev_err_probe(dev, ret,
401
+
"failed to enable regulator\n");
402
+
403
+
ret = devm_add_action_or_reset(dev, ads7924_reg_disable, data->vref_reg);
404
+
if (ret)
405
+
return dev_err_probe(dev, ret,
406
+
"failed to add regulator disable action\n");
407
+
408
+
ret = ads7924_reset(indio_dev);
409
+
if (ret < 0)
410
+
return dev_err_probe(dev, ret,
411
+
"failed to reset device\n");
412
+
413
+
ret = ads7924_set_conv_mode(data, ADS7924_MODECNTRL_AUTO_SCAN);
414
+
if (ret)
415
+
return dev_err_probe(dev, ret,
416
+
"failed to set conversion mode\n");
417
+
418
+
ret = devm_add_action_or_reset(dev, ads7924_set_idle_mode, data);
419
+
if (ret)
420
+
return dev_err_probe(dev, ret,
421
+
"failed to add idle mode action\n");
422
+
423
+
/* Use minimum signal acquire time. */
424
+
ret = regmap_update_bits(data->regmap, ADS7924_ACQCONFIG_REG,
425
+
ADS7924_ACQTIME_MASK,
426
+
FIELD_PREP(ADS7924_ACQTIME_MASK, 0));
427
+
if (ret < 0)
428
+
return dev_err_probe(dev, ret,
429
+
"failed to configure signal acquire time\n");
430
+
431
+
/* Disable power-up time. */
432
+
ret = regmap_update_bits(data->regmap, ADS7924_PWRCONFIG_REG,
433
+
ADS7924_PWRUPTIME_MASK,
434
+
FIELD_PREP(ADS7924_PWRUPTIME_MASK, 0));
435
+
if (ret < 0)
436
+
return dev_err_probe(dev, ret,
437
+
"failed to configure power-up time\n");
438
+
439
+
data->conv_invalid = true;
440
+
441
+
ret = devm_iio_device_register(dev, indio_dev);
442
+
if (ret < 0)
443
+
return dev_err_probe(dev, ret,
444
+
"failed to register IIO device\n");
445
+
446
+
return 0;
447
+
}
448
+
449
+
static const struct i2c_device_id ads7924_id[] = {
450
+
{ "ads7924", 0 },
451
+
{}
452
+
};
453
+
MODULE_DEVICE_TABLE(i2c, ads7924_id);
454
+
455
+
static const struct of_device_id ads7924_of_match[] = {
456
+
{ .compatible = "ti,ads7924", },
457
+
{}
458
+
};
459
+
MODULE_DEVICE_TABLE(of, ads7924_of_match);
460
+
461
+
static struct i2c_driver ads7924_driver = {
462
+
.driver = {
463
+
.name = "ads7924",
464
+
.of_match_table = ads7924_of_match,
465
+
},
466
+
.probe_new = ads7924_probe,
467
+
.id_table = ads7924_id,
468
+
};
469
+
470
+
module_i2c_driver(ads7924_driver);
471
+
472
+
MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@dimonoff.com>");
473
+
MODULE_DESCRIPTION("Texas Instruments ADS7924 ADC I2C driver");
474
+
MODULE_LICENSE("GPL");
+332
drivers/iio/adc/ti-lmp92064.c
+332
drivers/iio/adc/ti-lmp92064.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Texas Instruments LMP92064 SPI ADC driver
4
+
*
5
+
* Copyright (c) 2022 Leonard Göhrs <kernel@pengutronix.de>, Pengutronix
6
+
*
7
+
* Based on linux/drivers/iio/adc/ti-tsc2046.c
8
+
* Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
9
+
*/
10
+
11
+
#include <linux/delay.h>
12
+
#include <linux/gpio/consumer.h>
13
+
#include <linux/module.h>
14
+
#include <linux/regmap.h>
15
+
#include <linux/regulator/consumer.h>
16
+
#include <linux/spi/spi.h>
17
+
18
+
#include <linux/iio/iio.h>
19
+
#include <linux/iio/driver.h>
20
+
21
+
#define TI_LMP92064_REG_CONFIG_A 0x0000
22
+
#define TI_LMP92064_REG_CONFIG_B 0x0001
23
+
#define TI_LMP92064_REG_CHIP_REV 0x0006
24
+
25
+
#define TI_LMP92064_REG_MFR_ID1 0x000C
26
+
#define TI_LMP92064_REG_MFR_ID2 0x000D
27
+
28
+
#define TI_LMP92064_REG_REG_UPDATE 0x000F
29
+
#define TI_LMP92064_REG_CONFIG_REG 0x0100
30
+
#define TI_LMP92064_REG_STATUS 0x0103
31
+
32
+
#define TI_LMP92064_REG_DATA_VOUT_LSB 0x0200
33
+
#define TI_LMP92064_REG_DATA_VOUT_MSB 0x0201
34
+
#define TI_LMP92064_REG_DATA_COUT_LSB 0x0202
35
+
#define TI_LMP92064_REG_DATA_COUT_MSB 0x0203
36
+
37
+
#define TI_LMP92064_VAL_CONFIG_A 0x99
38
+
#define TI_LMP92064_VAL_CONFIG_B 0x00
39
+
#define TI_LMP92064_VAL_STATUS_OK 0x01
40
+
41
+
/*
42
+
* Channel number definitions for the two channels of the device
43
+
* - IN Current (INC)
44
+
* - IN Voltage (INV)
45
+
*/
46
+
#define TI_LMP92064_CHAN_INC 0
47
+
#define TI_LMP92064_CHAN_INV 1
48
+
49
+
static const struct regmap_range lmp92064_readable_reg_ranges[] = {
50
+
regmap_reg_range(TI_LMP92064_REG_CONFIG_A, TI_LMP92064_REG_CHIP_REV),
51
+
regmap_reg_range(TI_LMP92064_REG_MFR_ID1, TI_LMP92064_REG_MFR_ID2),
52
+
regmap_reg_range(TI_LMP92064_REG_REG_UPDATE, TI_LMP92064_REG_REG_UPDATE),
53
+
regmap_reg_range(TI_LMP92064_REG_CONFIG_REG, TI_LMP92064_REG_CONFIG_REG),
54
+
regmap_reg_range(TI_LMP92064_REG_STATUS, TI_LMP92064_REG_STATUS),
55
+
regmap_reg_range(TI_LMP92064_REG_DATA_VOUT_LSB, TI_LMP92064_REG_DATA_COUT_MSB),
56
+
};
57
+
58
+
static const struct regmap_access_table lmp92064_readable_regs = {
59
+
.yes_ranges = lmp92064_readable_reg_ranges,
60
+
.n_yes_ranges = ARRAY_SIZE(lmp92064_readable_reg_ranges),
61
+
};
62
+
63
+
static const struct regmap_range lmp92064_writable_reg_ranges[] = {
64
+
regmap_reg_range(TI_LMP92064_REG_CONFIG_A, TI_LMP92064_REG_CONFIG_B),
65
+
regmap_reg_range(TI_LMP92064_REG_REG_UPDATE, TI_LMP92064_REG_REG_UPDATE),
66
+
regmap_reg_range(TI_LMP92064_REG_CONFIG_REG, TI_LMP92064_REG_CONFIG_REG),
67
+
};
68
+
69
+
static const struct regmap_access_table lmp92064_writable_regs = {
70
+
.yes_ranges = lmp92064_writable_reg_ranges,
71
+
.n_yes_ranges = ARRAY_SIZE(lmp92064_writable_reg_ranges),
72
+
};
73
+
74
+
static const struct regmap_config lmp92064_spi_regmap_config = {
75
+
.reg_bits = 16,
76
+
.val_bits = 8,
77
+
.max_register = TI_LMP92064_REG_DATA_COUT_MSB,
78
+
.rd_table = &lmp92064_readable_regs,
79
+
.wr_table = &lmp92064_writable_regs,
80
+
};
81
+
82
+
struct lmp92064_adc_priv {
83
+
int shunt_resistor_uohm;
84
+
struct spi_device *spi;
85
+
struct regmap *regmap;
86
+
};
87
+
88
+
static const struct iio_chan_spec lmp92064_adc_channels[] = {
89
+
{
90
+
.type = IIO_CURRENT,
91
+
.address = TI_LMP92064_CHAN_INC,
92
+
.info_mask_separate =
93
+
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
94
+
.datasheet_name = "INC",
95
+
},
96
+
{
97
+
.type = IIO_VOLTAGE,
98
+
.address = TI_LMP92064_CHAN_INV,
99
+
.info_mask_separate =
100
+
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
101
+
.datasheet_name = "INV",
102
+
},
103
+
};
104
+
105
+
static int lmp92064_read_meas(struct lmp92064_adc_priv *priv, u16 *res)
106
+
{
107
+
__be16 raw[2];
108
+
int ret;
109
+
110
+
/*
111
+
* The ADC only latches in new samples if all DATA registers are read
112
+
* in descending sequential order.
113
+
* The ADC auto-decrements the register index with each clocked byte.
114
+
* Read both channels in single SPI transfer by selecting the highest
115
+
* register using the command below and clocking out all four data
116
+
* bytes.
117
+
*/
118
+
119
+
ret = regmap_bulk_read(priv->regmap, TI_LMP92064_REG_DATA_COUT_MSB,
120
+
&raw, sizeof(raw));
121
+
122
+
if (ret) {
123
+
dev_err(&priv->spi->dev, "regmap_bulk_read failed: %pe\n",
124
+
ERR_PTR(ret));
125
+
return ret;
126
+
}
127
+
128
+
res[0] = be16_to_cpu(raw[0]);
129
+
res[1] = be16_to_cpu(raw[1]);
130
+
131
+
return 0;
132
+
}
133
+
134
+
static int lmp92064_read_raw(struct iio_dev *indio_dev,
135
+
struct iio_chan_spec const *chan, int *val,
136
+
int *val2, long mask)
137
+
{
138
+
struct lmp92064_adc_priv *priv = iio_priv(indio_dev);
139
+
u16 raw[2];
140
+
int ret;
141
+
142
+
switch (mask) {
143
+
case IIO_CHAN_INFO_RAW:
144
+
ret = lmp92064_read_meas(priv, raw);
145
+
if (ret < 0)
146
+
return ret;
147
+
148
+
*val = (chan->address == TI_LMP92064_CHAN_INC) ? raw[0] : raw[1];
149
+
150
+
return IIO_VAL_INT;
151
+
case IIO_CHAN_INFO_SCALE:
152
+
if (chan->address == TI_LMP92064_CHAN_INC) {
153
+
/*
154
+
* processed (mA) = raw * current_lsb (mA)
155
+
* current_lsb (mA) = shunt_voltage_lsb (nV) / shunt_resistor (uOhm)
156
+
* shunt_voltage_lsb (nV) = 81920000 / 4096 = 20000
157
+
*/
158
+
*val = 20000;
159
+
*val2 = priv->shunt_resistor_uohm;
160
+
} else {
161
+
/*
162
+
* processed (mV) = raw * voltage_lsb (mV)
163
+
* voltage_lsb (mV) = 2048 / 4096
164
+
*/
165
+
*val = 2048;
166
+
*val2 = 4096;
167
+
}
168
+
return IIO_VAL_FRACTIONAL;
169
+
default:
170
+
return -EINVAL;
171
+
}
172
+
}
173
+
174
+
static int lmp92064_reset(struct lmp92064_adc_priv *priv,
175
+
struct gpio_desc *gpio_reset)
176
+
{
177
+
unsigned int status;
178
+
int ret, i;
179
+
180
+
if (gpio_reset) {
181
+
/*
182
+
* Perform a hard reset if gpio_reset is available.
183
+
* The datasheet specifies a very low 3.5ns reset pulse duration and does not
184
+
* specify how long to wait after a reset to access the device.
185
+
* Use more conservative pulse lengths to allow analog RC filtering of the
186
+
* reset line at the board level (as recommended in the datasheet).
187
+
*/
188
+
gpiod_set_value_cansleep(gpio_reset, 1);
189
+
usleep_range(1, 10);
190
+
gpiod_set_value_cansleep(gpio_reset, 0);
191
+
usleep_range(500, 750);
192
+
} else {
193
+
/*
194
+
* Perform a soft-reset if not.
195
+
* Also write default values to the config registers that are not
196
+
* affected by soft reset.
197
+
*/
198
+
ret = regmap_write(priv->regmap, TI_LMP92064_REG_CONFIG_A,
199
+
TI_LMP92064_VAL_CONFIG_A);
200
+
if (ret < 0)
201
+
return ret;
202
+
203
+
ret = regmap_write(priv->regmap, TI_LMP92064_REG_CONFIG_B,
204
+
TI_LMP92064_VAL_CONFIG_B);
205
+
if (ret < 0)
206
+
return ret;
207
+
}
208
+
209
+
/*
210
+
* Wait for the device to signal readiness to prevent reading bogus data
211
+
* and make sure device is actually connected.
212
+
* The datasheet does not specify how long this takes but usually it is
213
+
* not more than 3-4 iterations of this loop.
214
+
*/
215
+
for (i = 0; i < 10; i++) {
216
+
ret = regmap_read(priv->regmap, TI_LMP92064_REG_STATUS, &status);
217
+
if (ret < 0)
218
+
return ret;
219
+
220
+
if (status == TI_LMP92064_VAL_STATUS_OK)
221
+
return 0;
222
+
223
+
usleep_range(1000, 2000);
224
+
}
225
+
226
+
/*
227
+
* No (correct) response received.
228
+
* Device is mostly likely not connected to the bus.
229
+
*/
230
+
return -ENXIO;
231
+
}
232
+
233
+
static const struct iio_info lmp92064_adc_info = {
234
+
.read_raw = lmp92064_read_raw,
235
+
};
236
+
237
+
static int lmp92064_adc_probe(struct spi_device *spi)
238
+
{
239
+
struct device *dev = &spi->dev;
240
+
struct lmp92064_adc_priv *priv;
241
+
struct gpio_desc *gpio_reset;
242
+
struct iio_dev *indio_dev;
243
+
u32 shunt_resistor_uohm;
244
+
struct regmap *regmap;
245
+
int ret;
246
+
247
+
ret = spi_setup(spi);
248
+
if (ret < 0)
249
+
return dev_err_probe(dev, ret, "Error in SPI setup\n");
250
+
251
+
regmap = devm_regmap_init_spi(spi, &lmp92064_spi_regmap_config);
252
+
if (IS_ERR(regmap))
253
+
return dev_err_probe(dev, PTR_ERR(regmap),
254
+
"Failed to set up SPI regmap\n");
255
+
256
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
257
+
if (!indio_dev)
258
+
return -ENOMEM;
259
+
260
+
priv = iio_priv(indio_dev);
261
+
262
+
priv->spi = spi;
263
+
priv->regmap = regmap;
264
+
265
+
ret = device_property_read_u32(dev, "shunt-resistor-micro-ohms",
266
+
&shunt_resistor_uohm);
267
+
if (ret < 0)
268
+
return dev_err_probe(dev, ret,
269
+
"Failed to get shunt-resistor value\n");
270
+
271
+
/*
272
+
* The shunt resistance is passed to userspace as the denominator of an iio
273
+
* fraction. Make sure it is in range for that.
274
+
*/
275
+
if (shunt_resistor_uohm == 0 || shunt_resistor_uohm > INT_MAX) {
276
+
dev_err(dev, "Shunt resistance is out of range\n");
277
+
return -EINVAL;
278
+
}
279
+
280
+
priv->shunt_resistor_uohm = shunt_resistor_uohm;
281
+
282
+
ret = devm_regulator_get_enable(dev, "vdd");
283
+
if (ret)
284
+
return ret;
285
+
286
+
ret = devm_regulator_get_enable(dev, "vdig");
287
+
if (ret)
288
+
return ret;
289
+
290
+
gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
291
+
if (IS_ERR(gpio_reset))
292
+
return dev_err_probe(dev, PTR_ERR(gpio_reset),
293
+
"Failed to get GPIO reset pin\n");
294
+
295
+
ret = lmp92064_reset(priv, gpio_reset);
296
+
if (ret < 0)
297
+
return dev_err_probe(dev, ret, "Failed to reset device\n");
298
+
299
+
indio_dev->name = "lmp92064";
300
+
indio_dev->modes = INDIO_DIRECT_MODE;
301
+
indio_dev->channels = lmp92064_adc_channels;
302
+
indio_dev->num_channels = ARRAY_SIZE(lmp92064_adc_channels);
303
+
indio_dev->info = &lmp92064_adc_info;
304
+
305
+
return devm_iio_device_register(dev, indio_dev);
306
+
}
307
+
308
+
static const struct spi_device_id lmp92064_id_table[] = {
309
+
{ "lmp92064" },
310
+
{}
311
+
};
312
+
MODULE_DEVICE_TABLE(spi, lmp92064_id_table);
313
+
314
+
static const struct of_device_id lmp92064_of_table[] = {
315
+
{ .compatible = "ti,lmp92064" },
316
+
{}
317
+
};
318
+
MODULE_DEVICE_TABLE(of, lmp92064_of_table);
319
+
320
+
static struct spi_driver lmp92064_adc_driver = {
321
+
.driver = {
322
+
.name = "lmp92064",
323
+
.of_match_table = lmp92064_of_table,
324
+
},
325
+
.probe = lmp92064_adc_probe,
326
+
.id_table = lmp92064_id_table,
327
+
};
328
+
module_spi_driver(lmp92064_adc_driver);
329
+
330
+
MODULE_AUTHOR("Leonard Göhrs <kernel@pengutronix.de>");
331
+
MODULE_DESCRIPTION("TI LMP92064 ADC");
332
+
MODULE_LICENSE("GPL");
+3
-6
drivers/iio/adc/xilinx-ams.c
+3
-6
drivers/iio/adc/xilinx-ams.c
···
1220
1220
int num_channels = 0;
1221
1221
int ret;
1222
1222
1223
-
if (fwnode_property_match_string(fwnode, "compatible",
1224
-
"xlnx,zynqmp-ams-ps") == 0) {
1223
+
if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) {
1225
1224
ams->ps_base = fwnode_iomap(fwnode, 0);
1226
1225
if (!ams->ps_base)
1227
1226
return -ENXIO;
···
1231
1232
/* add PS channels to iio device channels */
1232
1233
memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels));
1233
1234
num_channels = ARRAY_SIZE(ams_ps_channels);
1234
-
} else if (fwnode_property_match_string(fwnode, "compatible",
1235
-
"xlnx,zynqmp-ams-pl") == 0) {
1235
+
} else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) {
1236
1236
ams->pl_base = fwnode_iomap(fwnode, 0);
1237
1237
if (!ams->pl_base)
1238
1238
return -ENXIO;
···
1245
1247
num_channels += AMS_PL_MAX_FIXED_CHANNEL;
1246
1248
num_channels = ams_get_ext_chan(fwnode, channels,
1247
1249
num_channels);
1248
-
} else if (fwnode_property_match_string(fwnode, "compatible",
1249
-
"xlnx,zynqmp-ams") == 0) {
1250
+
} else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) {
1250
1251
/* add AMS channels to iio device channels */
1251
1252
memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels));
1252
1253
num_channels += ARRAY_SIZE(ams_ctrl_channels);
+1
-2
drivers/iio/cdc/ad7746.c
+1
-2
drivers/iio/cdc/ad7746.c
+17
-29
drivers/iio/chemical/scd30_core.c
+17
-29
drivers/iio/chemical/scd30_core.c
···
354
354
ssize_t len = 0;
355
355
356
356
do {
357
-
len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09u ", 1000000000 / i);
357
+
len += sysfs_emit_at(buf, len, "0.%09u ", 1000000000 / i);
358
358
/*
359
359
* Not all values fit PAGE_SIZE buffer hence print every 6th
360
360
* (each frequency differs by 6s in time domain from the
···
380
380
ret = scd30_command_read(state, CMD_ASC, &val);
381
381
mutex_unlock(&state->lock);
382
382
383
-
return ret ?: sprintf(buf, "%d\n", val);
383
+
return ret ?: sysfs_emit(buf, "%d\n", val);
384
384
}
385
385
386
386
static ssize_t calibration_auto_enable_store(struct device *dev, struct device_attribute *attr,
···
414
414
ret = scd30_command_read(state, CMD_FRC, &val);
415
415
mutex_unlock(&state->lock);
416
416
417
-
return ret ?: sprintf(buf, "%d\n", val);
417
+
return ret ?: sysfs_emit(buf, "%d\n", val);
418
418
}
419
419
420
420
static ssize_t calibration_forced_value_store(struct device *dev, struct device_attribute *attr,
···
642
642
643
643
trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
644
644
iio_device_id(indio_dev));
645
-
if (!trig) {
646
-
dev_err(dev, "failed to allocate trigger\n");
647
-
return -ENOMEM;
648
-
}
645
+
if (!trig)
646
+
return dev_err_probe(dev, -ENOMEM, "failed to allocate trigger\n");
649
647
650
648
trig->ops = &scd30_trigger_ops;
651
649
iio_trigger_set_drvdata(trig, indio_dev);
···
665
667
IRQF_NO_AUTOEN,
666
668
indio_dev->name, indio_dev);
667
669
if (ret)
668
-
dev_err(dev, "failed to request irq\n");
670
+
return dev_err_probe(dev, ret, "failed to request irq\n");
669
671
670
-
return ret;
672
+
return 0;
671
673
}
672
674
673
675
int scd30_probe(struct device *dev, int irq, const char *name, void *priv,
···
715
717
return ret;
716
718
717
719
ret = scd30_reset(state);
718
-
if (ret) {
719
-
dev_err(dev, "failed to reset device: %d\n", ret);
720
-
return ret;
721
-
}
720
+
if (ret)
721
+
return dev_err_probe(dev, ret, "failed to reset device\n");
722
722
723
723
if (state->irq > 0) {
724
724
ret = scd30_setup_trigger(indio_dev);
725
-
if (ret) {
726
-
dev_err(dev, "failed to setup trigger: %d\n", ret);
727
-
return ret;
728
-
}
725
+
if (ret)
726
+
return dev_err_probe(dev, ret, "failed to setup trigger\n");
729
727
}
730
728
731
729
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, scd30_trigger_handler, NULL);
···
729
735
return ret;
730
736
731
737
ret = scd30_command_read(state, CMD_FW_VERSION, &val);
732
-
if (ret) {
733
-
dev_err(dev, "failed to read firmware version: %d\n", ret);
734
-
return ret;
735
-
}
738
+
if (ret)
739
+
return dev_err_probe(dev, ret, "failed to read firmware version\n");
736
740
dev_info(dev, "firmware version: %d.%d\n", val >> 8, (char)val);
737
741
738
742
ret = scd30_command_write(state, CMD_MEAS_INTERVAL, state->meas_interval);
739
-
if (ret) {
740
-
dev_err(dev, "failed to set measurement interval: %d\n", ret);
741
-
return ret;
742
-
}
743
+
if (ret)
744
+
return dev_err_probe(dev, ret, "failed to set measurement interval\n");
743
745
744
746
ret = scd30_command_write(state, CMD_START_MEAS, state->pressure_comp);
745
-
if (ret) {
746
-
dev_err(dev, "failed to start measurement: %d\n", ret);
747
-
return ret;
748
-
}
747
+
if (ret)
748
+
return dev_err_probe(dev, ret, "failed to start measurement\n");
749
749
750
750
ret = devm_add_action_or_reset(dev, scd30_stop_meas, state);
751
751
if (ret)
+2
-2
drivers/iio/common/scmi_sensors/scmi_iio.c
+2
-2
drivers/iio/common/scmi_sensors/scmi_iio.c
···
400
400
rem = do_div(resolution,
401
401
int_pow(10, abs(exponent))
402
402
);
403
-
len = scnprintf(buf, PAGE_SIZE,
403
+
len = sysfs_emit(buf,
404
404
"[%lld %llu.%llu %lld]\n", min_range,
405
405
resolution, rem, max_range);
406
406
} else {
407
407
resolution = resolution * int_pow(10, exponent);
408
-
len = scnprintf(buf, PAGE_SIZE, "[%lld %llu %lld]\n",
408
+
len = sysfs_emit(buf, "[%lld %llu %lld]\n",
409
409
min_range, resolution, max_range);
410
410
}
411
411
}
+17
-4
drivers/iio/dac/Kconfig
+17
-4
drivers/iio/dac/Kconfig
···
162
162
depends on I2C
163
163
select AD5686
164
164
help
165
-
Say yes here to build support for Analog Devices AD5311R, AD5338R,
166
-
AD5671R, AD5673R, AD5675R, AD5677R, AD5691R, AD5692R, AD5693, AD5693R,
167
-
AD5694, AD5694R, AD5695R, AD5696, and AD5696R Digital to Analog
168
-
converters.
165
+
Say yes here to build support for Analog Devices AD5311R, AD5337,
166
+
AD5338R, AD5671R, AD5673R, AD5675R, AD5677R, AD5691R, AD5692R, AD5693,
167
+
AD5693R, AD5694, AD5694R, AD5695R, AD5696, and AD5696R Digital to
168
+
Analog converters.
169
169
170
170
To compile this driver as a module, choose M here: the module will be
171
171
called ad5696.
···
356
356
357
357
This driver can also be built as a module. If so, the module
358
358
will be called max517.
359
+
360
+
config MAX5522
361
+
tristate "Maxim MAX5522 DAC driver"
362
+
depends on SPI_MASTER
363
+
select REGMAP_SPI
364
+
help
365
+
Say Y here if you want to build a driver for the Maxim MAX5522.
366
+
367
+
MAX5522 is a dual, ultra-low-power, 10-Bit, voltage-output
368
+
digital to analog converter (DAC) offering rail-to-rail buffered
369
+
voltage outputs.
370
+
371
+
If compiled as a module, it will be called max5522.
359
372
360
373
config MAX5821
361
374
tristate "Maxim MAX5821 DAC driver"
+1
drivers/iio/dac/Makefile
+1
drivers/iio/dac/Makefile
+7
drivers/iio/dac/ad5686.c
+7
drivers/iio/dac/ad5686.c
···
258
258
259
259
DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2);
260
260
DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6);
261
+
DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8);
261
262
DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6);
262
263
DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4);
263
264
DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4);
···
283
282
.int_vref_mv = 2500,
284
283
.num_channels = 1,
285
284
.regmap_type = AD5693_REGMAP,
285
+
},
286
+
[ID_AD5337R] = {
287
+
.channels = ad5337r_channels,
288
+
.int_vref_mv = 2500,
289
+
.num_channels = 2,
290
+
.regmap_type = AD5686_REGMAP,
286
291
},
287
292
[ID_AD5338R] = {
288
293
.channels = ad5338r_channels,
+1
drivers/iio/dac/ad5686.h
+1
drivers/iio/dac/ad5686.h
+2
drivers/iio/dac/ad5696-i2c.c
+2
drivers/iio/dac/ad5696-i2c.c
···
72
72
73
73
static const struct i2c_device_id ad5686_i2c_id[] = {
74
74
{"ad5311r", ID_AD5311R},
75
+
{"ad5337r", ID_AD5337R},
75
76
{"ad5338r", ID_AD5338R},
76
77
{"ad5671r", ID_AD5671R},
77
78
{"ad5673r", ID_AD5673R},
···
93
92
94
93
static const struct of_device_id ad5686_of_match[] = {
95
94
{ .compatible = "adi,ad5311r" },
95
+
{ .compatible = "adi,ad5337r" },
96
96
{ .compatible = "adi,ad5338r" },
97
97
{ .compatible = "adi,ad5671r" },
98
98
{ .compatible = "adi,ad5675r" },
+207
drivers/iio/dac/max5522.c
+207
drivers/iio/dac/max5522.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Maxim MAX5522
4
+
* Dual, Ultra-Low-Power 10-Bit, Voltage-Output DACs
5
+
*
6
+
* Copyright 2022 Timesys Corp.
7
+
*/
8
+
9
+
#include <linux/device.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/module.h>
12
+
#include <linux/mod_devicetable.h>
13
+
#include <linux/regmap.h>
14
+
#include <linux/regulator/consumer.h>
15
+
#include <linux/slab.h>
16
+
#include <linux/spi/spi.h>
17
+
18
+
#include <linux/iio/iio.h>
19
+
20
+
#define MAX5522_MAX_ADDR 15
21
+
#define MAX5522_CTRL_NONE 0
22
+
#define MAX5522_CTRL_LOAD_IN_A 9
23
+
#define MAX5522_CTRL_LOAD_IN_B 10
24
+
25
+
#define MAX5522_REG_DATA(x) ((x) + MAX5522_CTRL_LOAD_IN_A)
26
+
27
+
struct max5522_chip_info {
28
+
const char *name;
29
+
const struct iio_chan_spec *channels;
30
+
unsigned int num_channels;
31
+
};
32
+
33
+
struct max5522_state {
34
+
struct regmap *regmap;
35
+
const struct max5522_chip_info *chip_info;
36
+
unsigned short dac_cache[2];
37
+
struct regulator *vrefin_reg;
38
+
};
39
+
40
+
#define MAX5522_CHANNEL(chan) { \
41
+
.type = IIO_VOLTAGE, \
42
+
.indexed = 1, \
43
+
.output = 1, \
44
+
.channel = chan, \
45
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
46
+
BIT(IIO_CHAN_INFO_SCALE), \
47
+
.scan_type = { \
48
+
.sign = 'u', \
49
+
.realbits = 10, \
50
+
.storagebits = 16, \
51
+
.shift = 2, \
52
+
} \
53
+
}
54
+
55
+
const struct iio_chan_spec max5522_channels[] = {
56
+
MAX5522_CHANNEL(0),
57
+
MAX5522_CHANNEL(1),
58
+
};
59
+
60
+
enum max5522_type {
61
+
ID_MAX5522,
62
+
};
63
+
64
+
static const struct max5522_chip_info max5522_chip_info_tbl[] = {
65
+
[ID_MAX5522] = {
66
+
.name = "max5522",
67
+
.channels = max5522_channels,
68
+
.num_channels = 2,
69
+
},
70
+
};
71
+
72
+
static inline int max5522_info_to_reg(struct iio_chan_spec const *chan)
73
+
{
74
+
return MAX5522_REG_DATA(chan->channel);
75
+
}
76
+
77
+
static int max5522_read_raw(struct iio_dev *indio_dev,
78
+
struct iio_chan_spec const *chan,
79
+
int *val, int *val2, long info)
80
+
{
81
+
struct max5522_state *state = iio_priv(indio_dev);
82
+
int ret;
83
+
84
+
switch (info) {
85
+
case IIO_CHAN_INFO_RAW:
86
+
*val = state->dac_cache[chan->channel];
87
+
return IIO_VAL_INT;
88
+
case IIO_CHAN_INFO_SCALE:
89
+
ret = regulator_get_voltage(state->vrefin_reg);
90
+
if (ret < 0)
91
+
return -EINVAL;
92
+
*val = ret / 1000;
93
+
*val2 = 10;
94
+
return IIO_VAL_FRACTIONAL_LOG2;
95
+
default:
96
+
return -EINVAL;
97
+
}
98
+
99
+
return -EINVAL;
100
+
}
101
+
102
+
static int max5522_write_raw(struct iio_dev *indio_dev,
103
+
struct iio_chan_spec const *chan,
104
+
int val, int val2, long info)
105
+
{
106
+
struct max5522_state *state = iio_priv(indio_dev);
107
+
int rval;
108
+
109
+
if (val > 1023 || val < 0)
110
+
return -EINVAL;
111
+
112
+
rval = regmap_write(state->regmap, max5522_info_to_reg(chan),
113
+
val << chan->scan_type.shift);
114
+
if (rval < 0)
115
+
return rval;
116
+
117
+
state->dac_cache[chan->channel] = val;
118
+
119
+
return 0;
120
+
}
121
+
122
+
static const struct iio_info max5522_info = {
123
+
.read_raw = max5522_read_raw,
124
+
.write_raw = max5522_write_raw,
125
+
};
126
+
127
+
static const struct regmap_config max5522_regmap_config = {
128
+
.reg_bits = 4,
129
+
.val_bits = 12,
130
+
.max_register = MAX5522_MAX_ADDR,
131
+
};
132
+
133
+
static int max5522_spi_probe(struct spi_device *spi)
134
+
{
135
+
const struct spi_device_id *id = spi_get_device_id(spi);
136
+
struct iio_dev *indio_dev;
137
+
struct max5522_state *state;
138
+
int ret;
139
+
140
+
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
141
+
if (indio_dev == NULL) {
142
+
dev_err(&spi->dev, "failed to allocate iio device\n");
143
+
return -ENOMEM;
144
+
}
145
+
146
+
state = iio_priv(indio_dev);
147
+
state->chip_info = device_get_match_data(&spi->dev);
148
+
if (!state->chip_info) {
149
+
state->chip_info =
150
+
(struct max5522_chip_info *)(id->driver_data);
151
+
if (!state->chip_info)
152
+
return -EINVAL;
153
+
}
154
+
155
+
state->vrefin_reg = devm_regulator_get(&spi->dev, "vrefin");
156
+
if (IS_ERR(state->vrefin_reg))
157
+
return dev_err_probe(&spi->dev, PTR_ERR(state->vrefin_reg),
158
+
"Vrefin regulator not specified\n");
159
+
160
+
ret = regulator_enable(state->vrefin_reg);
161
+
if (ret) {
162
+
return dev_err_probe(&spi->dev, ret,
163
+
"Failed to enable vref regulators\n");
164
+
}
165
+
166
+
state->regmap = devm_regmap_init_spi(spi, &max5522_regmap_config);
167
+
168
+
if (IS_ERR(state->regmap))
169
+
return PTR_ERR(state->regmap);
170
+
171
+
indio_dev->info = &max5522_info;
172
+
indio_dev->modes = INDIO_DIRECT_MODE;
173
+
indio_dev->channels = max5522_channels;
174
+
indio_dev->num_channels = ARRAY_SIZE(max5522_channels);
175
+
indio_dev->name = max5522_chip_info_tbl[ID_MAX5522].name;
176
+
177
+
return devm_iio_device_register(&spi->dev, indio_dev);
178
+
}
179
+
180
+
static const struct spi_device_id max5522_ids[] = {
181
+
{ "max5522", (kernel_ulong_t)&max5522_chip_info_tbl[ID_MAX5522] },
182
+
{}
183
+
};
184
+
MODULE_DEVICE_TABLE(spi, max5522_ids);
185
+
186
+
static const struct of_device_id max5522_of_match[] = {
187
+
{
188
+
.compatible = "maxim,max5522",
189
+
.data = &max5522_chip_info_tbl[ID_MAX5522],
190
+
},
191
+
{}
192
+
};
193
+
MODULE_DEVICE_TABLE(of, max5522_of_match);
194
+
195
+
static struct spi_driver max5522_spi_driver = {
196
+
.driver = {
197
+
.name = "max5522",
198
+
.of_match_table = max5522_of_match,
199
+
},
200
+
.probe = max5522_spi_probe,
201
+
.id_table = max5522_ids,
202
+
};
203
+
module_spi_driver(max5522_spi_driver);
204
+
205
+
MODULE_AUTHOR("Angelo Dureghello <angelo.dureghello@timesys.com");
206
+
MODULE_DESCRIPTION("MAX5522 DAC driver");
207
+
MODULE_LICENSE("GPL");
+1
-1
drivers/iio/imu/bno055/bno055_ser_trace.c
+1
-1
drivers/iio/imu/bno055/bno055_ser_trace.c
+1
-1
drivers/iio/imu/kmx61.c
+1
-1
drivers/iio/imu/kmx61.c
+3
-2
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
+3
-2
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
···
93
93
.endianness = IIO_LE, \
94
94
}, \
95
95
.event_spec = &st_lsm6dsx_event, \
96
-
.ext_info = st_lsm6dsx_accel_ext_info, \
96
+
.ext_info = st_lsm6dsx_ext_info, \
97
97
.num_event_specs = 1, \
98
98
}
99
99
···
113
113
.storagebits = 16, \
114
114
.endianness = IIO_LE, \
115
115
}, \
116
+
.ext_info = st_lsm6dsx_ext_info, \
116
117
}
117
118
118
119
struct st_lsm6dsx_reg {
···
529
528
}
530
529
531
530
static const
532
-
struct iio_chan_spec_ext_info __maybe_unused st_lsm6dsx_accel_ext_info[] = {
531
+
struct iio_chan_spec_ext_info __maybe_unused st_lsm6dsx_ext_info[] = {
533
532
IIO_MOUNT_MATRIX(IIO_SHARED_BY_ALL, st_lsm6dsx_get_mount_matrix),
534
533
{ }
535
534
};
+6
-6
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c
+6
-6
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c
···
704
704
static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_shub_sampling_freq_avail);
705
705
static IIO_DEVICE_ATTR(in_scale_available, 0444,
706
706
st_lsm6dsx_shub_scale_avail, NULL, 0);
707
-
static struct attribute *st_lsm6dsx_ext_attributes[] = {
707
+
static struct attribute *st_lsm6dsx_shub_attributes[] = {
708
708
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
709
709
&iio_dev_attr_in_scale_available.dev_attr.attr,
710
710
NULL,
711
711
};
712
712
713
-
static const struct attribute_group st_lsm6dsx_ext_attribute_group = {
714
-
.attrs = st_lsm6dsx_ext_attributes,
713
+
static const struct attribute_group st_lsm6dsx_shub_attribute_group = {
714
+
.attrs = st_lsm6dsx_shub_attributes,
715
715
};
716
716
717
-
static const struct iio_info st_lsm6dsx_ext_info = {
718
-
.attrs = &st_lsm6dsx_ext_attribute_group,
717
+
static const struct iio_info st_lsm6dsx_shub_info = {
718
+
.attrs = &st_lsm6dsx_shub_attribute_group,
719
719
.read_raw = st_lsm6dsx_shub_read_raw,
720
720
.write_raw = st_lsm6dsx_shub_write_raw,
721
721
.hwfifo_set_watermark = st_lsm6dsx_set_watermark,
···
737
737
return NULL;
738
738
739
739
iio_dev->modes = INDIO_DIRECT_MODE;
740
-
iio_dev->info = &st_lsm6dsx_ext_info;
740
+
iio_dev->info = &st_lsm6dsx_shub_info;
741
741
742
742
sensor = iio_priv(iio_dev);
743
743
sensor->id = id;
+19
-47
drivers/iio/industrialio-core.c
+19
-47
drivers/iio/industrialio-core.c
···
8
8
9
9
#define pr_fmt(fmt) "iio-core: " fmt
10
10
11
-
#include <linux/kernel.h>
12
-
#include <linux/module.h>
11
+
#include <linux/anon_inodes.h>
12
+
#include <linux/cdev.h>
13
+
#include <linux/debugfs.h>
14
+
#include <linux/device.h>
15
+
#include <linux/err.h>
16
+
#include <linux/fs.h>
13
17
#include <linux/idr.h>
14
18
#include <linux/kdev_t.h>
15
-
#include <linux/err.h>
16
-
#include <linux/device.h>
17
-
#include <linux/fs.h>
19
+
#include <linux/kernel.h>
20
+
#include <linux/module.h>
21
+
#include <linux/mutex.h>
18
22
#include <linux/poll.h>
19
23
#include <linux/property.h>
20
24
#include <linux/sched.h>
21
-
#include <linux/wait.h>
22
-
#include <linux/cdev.h>
23
25
#include <linux/slab.h>
24
-
#include <linux/anon_inodes.h>
25
-
#include <linux/debugfs.h>
26
-
#include <linux/mutex.h>
27
-
#include <linux/iio/iio.h>
28
-
#include <linux/iio/iio-opaque.h>
29
-
#include "iio_core.h"
30
-
#include "iio_core_trigger.h"
31
-
#include <linux/iio/sysfs.h>
32
-
#include <linux/iio/events.h>
26
+
#include <linux/wait.h>
27
+
33
28
#include <linux/iio/buffer.h>
34
29
#include <linux/iio/buffer_impl.h>
30
+
#include <linux/iio/events.h>
31
+
#include <linux/iio/iio-opaque.h>
32
+
#include <linux/iio/iio.h>
33
+
#include <linux/iio/sysfs.h>
34
+
35
+
#include "iio_core.h"
36
+
#include "iio_core_trigger.h"
35
37
36
38
/* IDA to assign each registered device a unique id */
37
39
static DEFINE_IDA(iio_ida);
···
206
204
INDIO_BUFFER_SOFTWARE);
207
205
}
208
206
EXPORT_SYMBOL_GPL(iio_buffer_enabled);
209
-
210
-
/**
211
-
* iio_sysfs_match_string_with_gaps - matches given string in an array with gaps
212
-
* @array: array of strings
213
-
* @n: number of strings in the array
214
-
* @str: string to match with
215
-
*
216
-
* Returns index of @str in the @array or -EINVAL, similar to match_string().
217
-
* Uses sysfs_streq instead of strcmp for matching.
218
-
*
219
-
* This routine will look for a string in an array of strings.
220
-
* The search will continue until the element is found or the n-th element
221
-
* is reached, regardless of any NULL elements in the array.
222
-
*/
223
-
static int iio_sysfs_match_string_with_gaps(const char * const *array, size_t n,
224
-
const char *str)
225
-
{
226
-
const char *item;
227
-
int index;
228
-
229
-
for (index = 0; index < n; index++) {
230
-
item = array[index];
231
-
if (!item)
232
-
continue;
233
-
if (sysfs_streq(item, str))
234
-
return index;
235
-
}
236
-
237
-
return -EINVAL;
238
-
}
239
207
240
208
#if defined(CONFIG_DEBUG_FS)
241
209
/*
···
541
569
if (!e->set)
542
570
return -EINVAL;
543
571
544
-
ret = iio_sysfs_match_string_with_gaps(e->items, e->num_items, buf);
572
+
ret = __sysfs_match_string(e->items, e->num_items, buf);
545
573
if (ret < 0)
546
574
return ret;
547
575
+1
-1
drivers/iio/light/Makefile
+1
-1
drivers/iio/light/Makefile
···
39
39
obj-$(CONFIG_OPT3001) += opt3001.o
40
40
obj-$(CONFIG_PA12203001) += pa12203001.o
41
41
obj-$(CONFIG_RPR0521) += rpr0521.o
42
-
obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o
43
42
obj-$(CONFIG_SI1133) += si1133.o
44
43
obj-$(CONFIG_SI1145) += si1145.o
45
44
obj-$(CONFIG_STK3310) += stk3310.o
···
47
48
obj-$(CONFIG_ST_UVIS25_SPI) += st_uvis25_spi.o
48
49
obj-$(CONFIG_TCS3414) += tcs3414.o
49
50
obj-$(CONFIG_TCS3472) += tcs3472.o
51
+
obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o
50
52
obj-$(CONFIG_TSL2583) += tsl2583.o
51
53
obj-$(CONFIG_TSL2591) += tsl2591.o
52
54
obj-$(CONFIG_TSL2772) += tsl2772.o
+2
-3
drivers/iio/light/max44009.c
+2
-3
drivers/iio/light/max44009.c
···
487
487
return IRQ_NONE;
488
488
}
489
489
490
-
static int max44009_probe(struct i2c_client *client,
491
-
const struct i2c_device_id *id)
490
+
static int max44009_probe(struct i2c_client *client)
492
491
{
493
492
struct max44009_data *data;
494
493
struct iio_dev *indio_dev;
···
537
538
.driver = {
538
539
.name = MAX44009_DRV_NAME,
539
540
},
540
-
.probe = max44009_probe,
541
+
.probe_new = max44009_probe,
541
542
.id_table = max44009_id,
542
543
};
543
544
module_i2c_driver(max44009_driver);
+86
-103
drivers/iio/light/tsl2563.c
+86
-103
drivers/iio/light/tsl2563.c
···
11
11
* Amit Kucheria <amit.kucheria@verdurent.com>
12
12
*/
13
13
14
-
#include <linux/module.h>
15
-
#include <linux/mod_devicetable.h>
16
-
#include <linux/property.h>
14
+
#include <linux/bits.h>
15
+
#include <linux/delay.h>
16
+
#include <linux/err.h>
17
17
#include <linux/i2c.h>
18
18
#include <linux/interrupt.h>
19
19
#include <linux/irq.h>
20
-
#include <linux/sched.h>
20
+
#include <linux/math.h>
21
+
#include <linux/mod_devicetable.h>
22
+
#include <linux/module.h>
21
23
#include <linux/mutex.h>
22
-
#include <linux/delay.h>
23
24
#include <linux/pm.h>
24
-
#include <linux/err.h>
25
+
#include <linux/property.h>
26
+
#include <linux/sched.h>
25
27
#include <linux/slab.h>
26
28
29
+
#include <linux/iio/events.h>
27
30
#include <linux/iio/iio.h>
28
31
#include <linux/iio/sysfs.h>
29
-
#include <linux/iio/events.h>
30
-
#include <linux/platform_data/tsl2563.h>
31
32
32
33
/* Use this many bits for fraction part. */
33
34
#define ADC_FRAC_BITS 14
34
35
35
36
/* Given number of 1/10000's in ADC_FRAC_BITS precision. */
36
-
#define FRAC10K(f) (((f) * (1L << (ADC_FRAC_BITS))) / (10000))
37
+
#define FRAC10K(f) (((f) * BIT(ADC_FRAC_BITS)) / (10000))
37
38
38
39
/* Bits used for fraction in calibration coefficients.*/
39
40
#define CALIB_FRAC_BITS 10
40
-
/* 0.5 in CALIB_FRAC_BITS precision */
41
-
#define CALIB_FRAC_HALF (1 << (CALIB_FRAC_BITS - 1))
42
-
/* Make a fraction from a number n that was multiplied with b. */
43
-
#define CALIB_FRAC(n, b) (((n) << CALIB_FRAC_BITS) / (b))
44
41
/* Decimal 10^(digits in sysfs presentation) */
45
42
#define CALIB_BASE_SYSFS 1000
46
43
47
-
#define TSL2563_CMD 0x80
48
-
#define TSL2563_CLEARINT 0x40
44
+
#define TSL2563_CMD BIT(7)
45
+
#define TSL2563_CLEARINT BIT(6)
49
46
50
47
#define TSL2563_REG_CTRL 0x00
51
48
#define TSL2563_REG_TIMING 0x01
52
-
#define TSL2563_REG_LOWLOW 0x02 /* data0 low threshold, 2 bytes */
53
-
#define TSL2563_REG_LOWHIGH 0x03
54
-
#define TSL2563_REG_HIGHLOW 0x04 /* data0 high threshold, 2 bytes */
55
-
#define TSL2563_REG_HIGHHIGH 0x05
49
+
#define TSL2563_REG_LOW 0x02 /* data0 low threshold, 2 bytes */
50
+
#define TSL2563_REG_HIGH 0x04 /* data0 high threshold, 2 bytes */
56
51
#define TSL2563_REG_INT 0x06
57
52
#define TSL2563_REG_ID 0x0a
58
-
#define TSL2563_REG_DATA0LOW 0x0c /* broadband sensor value, 2 bytes */
59
-
#define TSL2563_REG_DATA0HIGH 0x0d
60
-
#define TSL2563_REG_DATA1LOW 0x0e /* infrared sensor value, 2 bytes */
61
-
#define TSL2563_REG_DATA1HIGH 0x0f
53
+
#define TSL2563_REG_DATA0 0x0c /* broadband sensor value, 2 bytes */
54
+
#define TSL2563_REG_DATA1 0x0e /* infrared sensor value, 2 bytes */
62
55
63
56
#define TSL2563_CMD_POWER_ON 0x03
64
57
#define TSL2563_CMD_POWER_OFF 0x00
65
-
#define TSL2563_CTRL_POWER_MASK 0x03
58
+
#define TSL2563_CTRL_POWER_MASK GENMASK(1, 0)
66
59
67
60
#define TSL2563_TIMING_13MS 0x00
68
61
#define TSL2563_TIMING_100MS 0x01
69
62
#define TSL2563_TIMING_400MS 0x02
70
-
#define TSL2563_TIMING_MASK 0x03
63
+
#define TSL2563_TIMING_MASK GENMASK(1, 0)
71
64
#define TSL2563_TIMING_GAIN16 0x10
72
65
#define TSL2563_TIMING_GAIN1 0x00
73
66
74
67
#define TSL2563_INT_DISABLED 0x00
75
68
#define TSL2563_INT_LEVEL 0x10
76
-
#define TSL2563_INT_PERSIST(n) ((n) & 0x0F)
69
+
#define TSL2563_INT_MASK GENMASK(5, 4)
70
+
#define TSL2563_INT_PERSIST(n) ((n) & GENMASK(3, 0))
77
71
78
72
struct tsl2563_gainlevel_coeff {
79
73
u8 gaintime;
···
155
161
chip->gainlevel->gaintime);
156
162
if (ret)
157
163
goto error_ret;
158
-
ret = i2c_smbus_write_byte_data(chip->client,
159
-
TSL2563_CMD | TSL2563_REG_HIGHLOW,
160
-
chip->high_thres & 0xFF);
164
+
ret = i2c_smbus_write_word_data(chip->client,
165
+
TSL2563_CMD | TSL2563_REG_HIGH,
166
+
chip->high_thres);
161
167
if (ret)
162
168
goto error_ret;
163
-
ret = i2c_smbus_write_byte_data(chip->client,
164
-
TSL2563_CMD | TSL2563_REG_HIGHHIGH,
165
-
(chip->high_thres >> 8) & 0xFF);
169
+
ret = i2c_smbus_write_word_data(chip->client,
170
+
TSL2563_CMD | TSL2563_REG_LOW,
171
+
chip->low_thres);
166
172
if (ret)
167
173
goto error_ret;
168
-
ret = i2c_smbus_write_byte_data(chip->client,
169
-
TSL2563_CMD | TSL2563_REG_LOWLOW,
170
-
chip->low_thres & 0xFF);
171
-
if (ret)
172
-
goto error_ret;
173
-
ret = i2c_smbus_write_byte_data(chip->client,
174
-
TSL2563_CMD | TSL2563_REG_LOWHIGH,
175
-
(chip->low_thres >> 8) & 0xFF);
176
174
/*
177
175
* Interrupt register is automatically written anyway if it is relevant
178
176
* so is not here.
···
206
220
207
221
*id = ret;
208
222
223
+
return 0;
224
+
}
225
+
226
+
static int tsl2563_configure_irq(struct tsl2563_chip *chip, bool enable)
227
+
{
228
+
int ret;
229
+
230
+
chip->intr &= ~TSL2563_INT_MASK;
231
+
if (enable)
232
+
chip->intr |= TSL2563_INT_LEVEL;
233
+
234
+
ret = i2c_smbus_write_byte_data(chip->client,
235
+
TSL2563_CMD | TSL2563_REG_INT,
236
+
chip->intr);
237
+
if (ret < 0)
238
+
return ret;
239
+
240
+
chip->int_enabled = enable;
209
241
return 0;
210
242
}
211
243
···
329
325
330
326
while (retry) {
331
327
ret = i2c_smbus_read_word_data(client,
332
-
TSL2563_CMD | TSL2563_REG_DATA0LOW);
328
+
TSL2563_CMD | TSL2563_REG_DATA0);
333
329
if (ret < 0)
334
330
goto out;
335
331
adc0 = ret;
336
332
337
333
ret = i2c_smbus_read_word_data(client,
338
-
TSL2563_CMD | TSL2563_REG_DATA1LOW);
334
+
TSL2563_CMD | TSL2563_REG_DATA1);
339
335
if (ret < 0)
340
336
goto out;
341
337
adc1 = ret;
···
356
352
357
353
static inline int tsl2563_calib_to_sysfs(u32 calib)
358
354
{
359
-
return (int) (((calib * CALIB_BASE_SYSFS) +
360
-
CALIB_FRAC_HALF) >> CALIB_FRAC_BITS);
355
+
return (int)DIV_ROUND_CLOSEST(calib * CALIB_BASE_SYSFS, BIT(CALIB_FRAC_BITS));
361
356
}
362
357
363
358
static inline u32 tsl2563_calib_from_sysfs(int value)
364
359
{
360
+
/* Make a fraction from a number n that was multiplied with b. */
365
361
return (((u32) value) << CALIB_FRAC_BITS) / CALIB_BASE_SYSFS;
366
362
}
367
363
···
588
584
{
589
585
struct tsl2563_chip *chip = iio_priv(indio_dev);
590
586
int ret;
591
-
u8 address;
587
+
588
+
mutex_lock(&chip->lock);
592
589
593
590
if (dir == IIO_EV_DIR_RISING)
594
-
address = TSL2563_REG_HIGHLOW;
591
+
ret = i2c_smbus_write_word_data(chip->client,
592
+
TSL2563_CMD | TSL2563_REG_HIGH, val);
595
593
else
596
-
address = TSL2563_REG_LOWLOW;
597
-
mutex_lock(&chip->lock);
598
-
ret = i2c_smbus_write_byte_data(chip->client, TSL2563_CMD | address,
599
-
val & 0xFF);
594
+
ret = i2c_smbus_write_word_data(chip->client,
595
+
TSL2563_CMD | TSL2563_REG_LOW, val);
600
596
if (ret)
601
597
goto error_ret;
602
-
ret = i2c_smbus_write_byte_data(chip->client,
603
-
TSL2563_CMD | (address + 1),
604
-
(val >> 8) & 0xFF);
598
+
605
599
if (dir == IIO_EV_DIR_RISING)
606
600
chip->high_thres = val;
607
601
else
···
636
634
int ret = 0;
637
635
638
636
mutex_lock(&chip->lock);
639
-
if (state && !(chip->intr & 0x30)) {
640
-
chip->intr &= ~0x30;
641
-
chip->intr |= 0x10;
637
+
if (state && !(chip->intr & TSL2563_INT_MASK)) {
642
638
/* ensure the chip is actually on */
643
639
cancel_delayed_work_sync(&chip->poweroff_work);
644
640
if (!tsl2563_get_power(chip)) {
···
647
647
if (ret)
648
648
goto out;
649
649
}
650
-
ret = i2c_smbus_write_byte_data(chip->client,
651
-
TSL2563_CMD | TSL2563_REG_INT,
652
-
chip->intr);
653
-
chip->int_enabled = true;
650
+
ret = tsl2563_configure_irq(chip, true);
654
651
}
655
652
656
-
if (!state && (chip->intr & 0x30)) {
657
-
chip->intr &= ~0x30;
658
-
ret = i2c_smbus_write_byte_data(chip->client,
659
-
TSL2563_CMD | TSL2563_REG_INT,
660
-
chip->intr);
661
-
chip->int_enabled = false;
653
+
if (!state && (chip->intr & TSL2563_INT_MASK)) {
654
+
ret = tsl2563_configure_irq(chip, false);
662
655
/* now the interrupt is not enabled, we can go to sleep */
663
656
schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
664
657
}
···
675
682
if (ret < 0)
676
683
return ret;
677
684
678
-
return !!(ret & 0x30);
685
+
return !!(ret & TSL2563_INT_MASK);
679
686
}
680
687
681
688
static const struct iio_info tsl2563_info_no_irq = {
···
694
701
695
702
static int tsl2563_probe(struct i2c_client *client)
696
703
{
704
+
struct device *dev = &client->dev;
697
705
struct iio_dev *indio_dev;
698
706
struct tsl2563_chip *chip;
699
-
struct tsl2563_platform_data *pdata = client->dev.platform_data;
700
-
int err = 0;
707
+
unsigned long irq_flags;
701
708
u8 id = 0;
709
+
int err;
702
710
703
-
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
711
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
704
712
if (!indio_dev)
705
713
return -ENOMEM;
706
714
···
711
717
chip->client = client;
712
718
713
719
err = tsl2563_detect(chip);
714
-
if (err) {
715
-
dev_err(&client->dev, "detect error %d\n", -err);
716
-
return err;
717
-
}
720
+
if (err)
721
+
return dev_err_probe(dev, err, "detect error\n");
718
722
719
723
err = tsl2563_read_id(chip, &id);
720
-
if (err) {
721
-
dev_err(&client->dev, "read id error %d\n", -err);
722
-
return err;
723
-
}
724
+
if (err)
725
+
return dev_err_probe(dev, err, "read id error\n");
724
726
725
727
mutex_init(&chip->lock);
726
728
···
728
738
chip->calib0 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS);
729
739
chip->calib1 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS);
730
740
731
-
if (pdata) {
732
-
chip->cover_comp_gain = pdata->cover_comp_gain;
733
-
} else {
734
-
err = device_property_read_u32(&client->dev, "amstaos,cover-comp-gain",
735
-
&chip->cover_comp_gain);
736
-
if (err)
737
-
chip->cover_comp_gain = 1;
738
-
}
741
+
chip->cover_comp_gain = 1;
742
+
device_property_read_u32(dev, "amstaos,cover-comp-gain", &chip->cover_comp_gain);
739
743
740
-
dev_info(&client->dev, "model %d, rev. %d\n", id >> 4, id & 0x0f);
744
+
dev_info(dev, "model %d, rev. %d\n", id >> 4, id & 0x0f);
741
745
indio_dev->name = client->name;
742
746
indio_dev->channels = tsl2563_channels;
743
747
indio_dev->num_channels = ARRAY_SIZE(tsl2563_channels);
···
743
759
indio_dev->info = &tsl2563_info_no_irq;
744
760
745
761
if (client->irq) {
746
-
err = devm_request_threaded_irq(&client->dev, client->irq,
762
+
irq_flags = irq_get_trigger_type(client->irq);
763
+
if (irq_flags == IRQF_TRIGGER_NONE)
764
+
irq_flags = IRQF_TRIGGER_RISING;
765
+
irq_flags |= IRQF_ONESHOT;
766
+
767
+
err = devm_request_threaded_irq(dev, client->irq,
747
768
NULL,
748
769
&tsl2563_event_handler,
749
-
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
770
+
irq_flags,
750
771
"tsl2563_event",
751
772
indio_dev);
752
-
if (err) {
753
-
dev_err(&client->dev, "irq request error %d\n", -err);
754
-
return err;
755
-
}
773
+
if (err)
774
+
return dev_err_probe(dev, err, "irq request error\n");
756
775
}
757
776
758
777
err = tsl2563_configure(chip);
759
-
if (err) {
760
-
dev_err(&client->dev, "configure error %d\n", -err);
761
-
return err;
762
-
}
778
+
if (err)
779
+
return dev_err_probe(dev, err, "configure error\n");
763
780
764
781
INIT_DELAYED_WORK(&chip->poweroff_work, tsl2563_poweroff_work);
765
782
···
769
784
770
785
err = iio_device_register(indio_dev);
771
786
if (err) {
772
-
dev_err(&client->dev, "iio registration error %d\n", -err);
787
+
dev_err_probe(dev, err, "iio registration error\n");
773
788
goto fail;
774
789
}
775
790
···
789
804
if (!chip->int_enabled)
790
805
cancel_delayed_work_sync(&chip->poweroff_work);
791
806
/* Ensure that interrupts are disabled - then flush any bottom halves */
792
-
chip->intr &= ~0x30;
793
-
i2c_smbus_write_byte_data(chip->client, TSL2563_CMD | TSL2563_REG_INT,
794
-
chip->intr);
807
+
tsl2563_configure_irq(chip, false);
795
808
tsl2563_set_power(chip, 0);
796
809
}
797
810
798
811
static int tsl2563_suspend(struct device *dev)
799
812
{
800
-
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
813
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
801
814
struct tsl2563_chip *chip = iio_priv(indio_dev);
802
815
int ret;
803
816
···
814
831
815
832
static int tsl2563_resume(struct device *dev)
816
833
{
817
-
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
834
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
818
835
struct tsl2563_chip *chip = iio_priv(indio_dev);
819
836
int ret;
820
837
+322
-149
drivers/iio/light/vcnl4000.c
+322
-149
drivers/iio/light/vcnl4000.c
···
60
60
61
61
#define VCNL4200_AL_CONF 0x00 /* Ambient light configuration */
62
62
#define VCNL4200_PS_CONF1 0x03 /* Proximity configuration */
63
+
#define VCNL4040_PS_THDL_LM 0x06 /* Proximity threshold low */
64
+
#define VCNL4040_PS_THDH_LM 0x07 /* Proximity threshold high */
63
65
#define VCNL4200_PS_DATA 0x08 /* Proximity data */
64
66
#define VCNL4200_AL_DATA 0x09 /* Ambient light data */
67
+
#define VCNL4040_INT_FLAGS 0x0b /* Interrupt register */
65
68
#define VCNL4200_DEV_ID 0x0e /* Device ID, slave address and version */
66
69
67
70
#define VCNL4040_DEV_ID 0x0c /* Device ID and version */
···
81
78
#define VCNL4040_ALS_CONF_ALS_SHUTDOWN BIT(0)
82
79
#define VCNL4040_PS_CONF1_PS_SHUTDOWN BIT(0)
83
80
#define VCNL4040_PS_CONF2_PS_IT GENMASK(3, 1) /* Proximity integration time */
81
+
#define VCNL4040_PS_CONF2_PS_INT GENMASK(9, 8) /* Proximity interrupt mode */
82
+
#define VCNL4040_PS_IF_AWAY BIT(8) /* Proximity event cross low threshold */
83
+
#define VCNL4040_PS_IF_CLOSE BIT(9) /* Proximity event cross high threshold */
84
84
85
85
/* Bit masks for interrupt registers. */
86
86
#define VCNL4010_INT_THR_SEL BIT(0) /* Select threshold interrupt source */
···
144
138
enum vcnl4000_device_ids id;
145
139
int rev;
146
140
int al_scale;
141
+
u8 ps_int; /* proximity interrupt mode */
147
142
const struct vcnl4000_chip_spec *chip_spec;
148
143
struct mutex vcnl4000_lock;
149
144
struct vcnl4200_channel vcnl4200_al;
···
157
150
struct iio_chan_spec const *channels;
158
151
const int num_channels;
159
152
const struct iio_info *info;
160
-
bool irq_support;
153
+
const struct iio_buffer_setup_ops *buffer_setup_ops;
161
154
int (*init)(struct vcnl4000_data *data);
162
155
int (*measure_light)(struct vcnl4000_data *data, int *val);
163
156
int (*measure_proximity)(struct vcnl4000_data *data, int *val);
164
157
int (*set_power_state)(struct vcnl4000_data *data, bool on);
158
+
irqreturn_t (*irq_thread)(int irq, void *priv);
159
+
irqreturn_t (*trig_buffer_func)(int irq, void *priv);
165
160
};
166
161
167
162
static const struct i2c_device_id vcnl4000_id[] = {
···
263
254
{
264
255
int ret;
265
256
257
+
/* Do not power down if interrupts are enabled */
258
+
if (!on && data->ps_int)
259
+
return 0;
260
+
266
261
ret = vcnl4000_write_als_enable(data, on);
267
262
if (ret < 0)
268
263
return ret;
···
308
295
dev_dbg(&data->client->dev, "device id 0x%x", id);
309
296
310
297
data->rev = (ret >> 8) & 0xf;
298
+
data->ps_int = 0;
311
299
312
300
data->vcnl4200_al.reg = VCNL4200_AL_DATA;
313
301
data->vcnl4200_ps.reg = VCNL4200_PS_DATA;
···
809
795
}
810
796
}
811
797
798
+
static int vcnl4040_read_event(struct iio_dev *indio_dev,
799
+
const struct iio_chan_spec *chan,
800
+
enum iio_event_type type,
801
+
enum iio_event_direction dir,
802
+
enum iio_event_info info,
803
+
int *val, int *val2)
804
+
{
805
+
int ret;
806
+
struct vcnl4000_data *data = iio_priv(indio_dev);
807
+
808
+
switch (dir) {
809
+
case IIO_EV_DIR_RISING:
810
+
ret = i2c_smbus_read_word_data(data->client,
811
+
VCNL4040_PS_THDH_LM);
812
+
if (ret < 0)
813
+
return ret;
814
+
*val = ret;
815
+
return IIO_VAL_INT;
816
+
case IIO_EV_DIR_FALLING:
817
+
ret = i2c_smbus_read_word_data(data->client,
818
+
VCNL4040_PS_THDL_LM);
819
+
if (ret < 0)
820
+
return ret;
821
+
*val = ret;
822
+
return IIO_VAL_INT;
823
+
default:
824
+
return -EINVAL;
825
+
}
826
+
}
827
+
828
+
static int vcnl4040_write_event(struct iio_dev *indio_dev,
829
+
const struct iio_chan_spec *chan,
830
+
enum iio_event_type type,
831
+
enum iio_event_direction dir,
832
+
enum iio_event_info info,
833
+
int val, int val2)
834
+
{
835
+
int ret;
836
+
struct vcnl4000_data *data = iio_priv(indio_dev);
837
+
838
+
switch (dir) {
839
+
case IIO_EV_DIR_RISING:
840
+
ret = i2c_smbus_write_word_data(data->client,
841
+
VCNL4040_PS_THDH_LM, val);
842
+
if (ret < 0)
843
+
return ret;
844
+
return IIO_VAL_INT;
845
+
case IIO_EV_DIR_FALLING:
846
+
ret = i2c_smbus_write_word_data(data->client,
847
+
VCNL4040_PS_THDL_LM, val);
848
+
if (ret < 0)
849
+
return ret;
850
+
return IIO_VAL_INT;
851
+
default:
852
+
return -EINVAL;
853
+
}
854
+
}
855
+
812
856
static bool vcnl4010_is_thr_enabled(struct vcnl4000_data *data)
813
857
{
814
858
int ret;
···
949
877
}
950
878
}
951
879
880
+
static int vcnl4040_read_event_config(struct iio_dev *indio_dev,
881
+
const struct iio_chan_spec *chan,
882
+
enum iio_event_type type,
883
+
enum iio_event_direction dir)
884
+
{
885
+
int ret;
886
+
struct vcnl4000_data *data = iio_priv(indio_dev);
887
+
888
+
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
889
+
if (ret < 0)
890
+
return ret;
891
+
892
+
data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, ret);
893
+
894
+
return (dir == IIO_EV_DIR_RISING) ?
895
+
FIELD_GET(VCNL4040_PS_IF_AWAY, ret) :
896
+
FIELD_GET(VCNL4040_PS_IF_CLOSE, ret);
897
+
}
898
+
899
+
static int vcnl4040_write_event_config(struct iio_dev *indio_dev,
900
+
const struct iio_chan_spec *chan,
901
+
enum iio_event_type type,
902
+
enum iio_event_direction dir, int state)
903
+
{
904
+
int ret;
905
+
u16 val, mask;
906
+
struct vcnl4000_data *data = iio_priv(indio_dev);
907
+
908
+
mutex_lock(&data->vcnl4000_lock);
909
+
910
+
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
911
+
if (ret < 0)
912
+
goto out;
913
+
914
+
if (dir == IIO_EV_DIR_RISING)
915
+
mask = VCNL4040_PS_IF_AWAY;
916
+
else
917
+
mask = VCNL4040_PS_IF_CLOSE;
918
+
919
+
val = state ? (ret | mask) : (ret & ~mask);
920
+
921
+
data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, val);
922
+
ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, val);
923
+
924
+
out:
925
+
mutex_unlock(&data->vcnl4000_lock);
926
+
data->chip_spec->set_power_state(data, data->ps_int != 0);
927
+
928
+
return ret;
929
+
}
930
+
931
+
static irqreturn_t vcnl4040_irq_thread(int irq, void *p)
932
+
{
933
+
struct iio_dev *indio_dev = p;
934
+
struct vcnl4000_data *data = iio_priv(indio_dev);
935
+
int ret;
936
+
937
+
ret = i2c_smbus_read_word_data(data->client, VCNL4040_INT_FLAGS);
938
+
if (ret < 0)
939
+
return IRQ_HANDLED;
940
+
941
+
if (ret & VCNL4040_PS_IF_CLOSE) {
942
+
iio_push_event(indio_dev,
943
+
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
944
+
IIO_EV_TYPE_THRESH,
945
+
IIO_EV_DIR_RISING),
946
+
iio_get_time_ns(indio_dev));
947
+
}
948
+
949
+
if (ret & VCNL4040_PS_IF_AWAY) {
950
+
iio_push_event(indio_dev,
951
+
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
952
+
IIO_EV_TYPE_THRESH,
953
+
IIO_EV_DIR_FALLING),
954
+
iio_get_time_ns(indio_dev));
955
+
}
956
+
957
+
return IRQ_HANDLED;
958
+
}
959
+
952
960
static ssize_t vcnl4000_read_near_level(struct iio_dev *indio_dev,
953
961
uintptr_t priv,
954
962
const struct iio_chan_spec *chan,
···
1038
886
1039
887
return sprintf(buf, "%u\n", data->near_level);
1040
888
}
1041
-
1042
-
static const struct iio_chan_spec_ext_info vcnl4000_ext_info[] = {
1043
-
{
1044
-
.name = "nearlevel",
1045
-
.shared = IIO_SEPARATE,
1046
-
.read = vcnl4000_read_near_level,
1047
-
},
1048
-
{ /* sentinel */ }
1049
-
};
1050
-
1051
-
static const struct iio_event_spec vcnl4000_event_spec[] = {
1052
-
{
1053
-
.type = IIO_EV_TYPE_THRESH,
1054
-
.dir = IIO_EV_DIR_RISING,
1055
-
.mask_separate = BIT(IIO_EV_INFO_VALUE),
1056
-
}, {
1057
-
.type = IIO_EV_TYPE_THRESH,
1058
-
.dir = IIO_EV_DIR_FALLING,
1059
-
.mask_separate = BIT(IIO_EV_INFO_VALUE),
1060
-
}, {
1061
-
.type = IIO_EV_TYPE_THRESH,
1062
-
.dir = IIO_EV_DIR_EITHER,
1063
-
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
1064
-
}
1065
-
};
1066
-
1067
-
static const struct iio_chan_spec vcnl4000_channels[] = {
1068
-
{
1069
-
.type = IIO_LIGHT,
1070
-
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1071
-
BIT(IIO_CHAN_INFO_SCALE),
1072
-
}, {
1073
-
.type = IIO_PROXIMITY,
1074
-
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1075
-
.ext_info = vcnl4000_ext_info,
1076
-
}
1077
-
};
1078
-
1079
-
static const struct iio_chan_spec vcnl4010_channels[] = {
1080
-
{
1081
-
.type = IIO_LIGHT,
1082
-
.scan_index = -1,
1083
-
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1084
-
BIT(IIO_CHAN_INFO_SCALE),
1085
-
}, {
1086
-
.type = IIO_PROXIMITY,
1087
-
.scan_index = 0,
1088
-
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1089
-
BIT(IIO_CHAN_INFO_SAMP_FREQ),
1090
-
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
1091
-
.event_spec = vcnl4000_event_spec,
1092
-
.num_event_specs = ARRAY_SIZE(vcnl4000_event_spec),
1093
-
.ext_info = vcnl4000_ext_info,
1094
-
.scan_type = {
1095
-
.sign = 'u',
1096
-
.realbits = 16,
1097
-
.storagebits = 16,
1098
-
.endianness = IIO_CPU,
1099
-
},
1100
-
},
1101
-
IIO_CHAN_SOFT_TIMESTAMP(1),
1102
-
};
1103
-
1104
-
static const struct iio_chan_spec vcnl4040_channels[] = {
1105
-
{
1106
-
.type = IIO_LIGHT,
1107
-
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1108
-
BIT(IIO_CHAN_INFO_SCALE),
1109
-
}, {
1110
-
.type = IIO_PROXIMITY,
1111
-
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1112
-
BIT(IIO_CHAN_INFO_INT_TIME),
1113
-
.info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME),
1114
-
.ext_info = vcnl4000_ext_info,
1115
-
}
1116
-
};
1117
-
1118
-
static const struct iio_info vcnl4000_info = {
1119
-
.read_raw = vcnl4000_read_raw,
1120
-
};
1121
-
1122
-
static const struct iio_info vcnl4010_info = {
1123
-
.read_raw = vcnl4010_read_raw,
1124
-
.read_avail = vcnl4010_read_avail,
1125
-
.write_raw = vcnl4010_write_raw,
1126
-
.read_event_value = vcnl4010_read_event,
1127
-
.write_event_value = vcnl4010_write_event,
1128
-
.read_event_config = vcnl4010_read_event_config,
1129
-
.write_event_config = vcnl4010_write_event_config,
1130
-
};
1131
-
1132
-
static const struct iio_info vcnl4040_info = {
1133
-
.read_raw = vcnl4000_read_raw,
1134
-
.write_raw = vcnl4040_write_raw,
1135
-
.read_avail = vcnl4040_read_avail,
1136
-
};
1137
-
1138
-
static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = {
1139
-
[VCNL4000] = {
1140
-
.prod = "VCNL4000",
1141
-
.init = vcnl4000_init,
1142
-
.measure_light = vcnl4000_measure_light,
1143
-
.measure_proximity = vcnl4000_measure_proximity,
1144
-
.set_power_state = vcnl4000_set_power_state,
1145
-
.channels = vcnl4000_channels,
1146
-
.num_channels = ARRAY_SIZE(vcnl4000_channels),
1147
-
.info = &vcnl4000_info,
1148
-
.irq_support = false,
1149
-
},
1150
-
[VCNL4010] = {
1151
-
.prod = "VCNL4010/4020",
1152
-
.init = vcnl4000_init,
1153
-
.measure_light = vcnl4000_measure_light,
1154
-
.measure_proximity = vcnl4000_measure_proximity,
1155
-
.set_power_state = vcnl4000_set_power_state,
1156
-
.channels = vcnl4010_channels,
1157
-
.num_channels = ARRAY_SIZE(vcnl4010_channels),
1158
-
.info = &vcnl4010_info,
1159
-
.irq_support = true,
1160
-
},
1161
-
[VCNL4040] = {
1162
-
.prod = "VCNL4040",
1163
-
.init = vcnl4200_init,
1164
-
.measure_light = vcnl4200_measure_light,
1165
-
.measure_proximity = vcnl4200_measure_proximity,
1166
-
.set_power_state = vcnl4200_set_power_state,
1167
-
.channels = vcnl4040_channels,
1168
-
.num_channels = ARRAY_SIZE(vcnl4040_channels),
1169
-
.info = &vcnl4040_info,
1170
-
.irq_support = false,
1171
-
},
1172
-
[VCNL4200] = {
1173
-
.prod = "VCNL4200",
1174
-
.init = vcnl4200_init,
1175
-
.measure_light = vcnl4200_measure_light,
1176
-
.measure_proximity = vcnl4200_measure_proximity,
1177
-
.set_power_state = vcnl4200_set_power_state,
1178
-
.channels = vcnl4000_channels,
1179
-
.num_channels = ARRAY_SIZE(vcnl4000_channels),
1180
-
.info = &vcnl4000_info,
1181
-
.irq_support = false,
1182
-
},
1183
-
};
1184
889
1185
890
static irqreturn_t vcnl4010_irq_thread(int irq, void *p)
1186
891
{
···
1167
1158
.predisable = &vcnl4010_buffer_predisable,
1168
1159
};
1169
1160
1161
+
static const struct iio_chan_spec_ext_info vcnl4000_ext_info[] = {
1162
+
{
1163
+
.name = "nearlevel",
1164
+
.shared = IIO_SEPARATE,
1165
+
.read = vcnl4000_read_near_level,
1166
+
},
1167
+
{ /* sentinel */ }
1168
+
};
1169
+
1170
+
static const struct iio_event_spec vcnl4000_event_spec[] = {
1171
+
{
1172
+
.type = IIO_EV_TYPE_THRESH,
1173
+
.dir = IIO_EV_DIR_RISING,
1174
+
.mask_separate = BIT(IIO_EV_INFO_VALUE),
1175
+
}, {
1176
+
.type = IIO_EV_TYPE_THRESH,
1177
+
.dir = IIO_EV_DIR_FALLING,
1178
+
.mask_separate = BIT(IIO_EV_INFO_VALUE),
1179
+
}, {
1180
+
.type = IIO_EV_TYPE_THRESH,
1181
+
.dir = IIO_EV_DIR_EITHER,
1182
+
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
1183
+
}
1184
+
};
1185
+
1186
+
static const struct iio_event_spec vcnl4040_event_spec[] = {
1187
+
{
1188
+
.type = IIO_EV_TYPE_THRESH,
1189
+
.dir = IIO_EV_DIR_RISING,
1190
+
.mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
1191
+
}, {
1192
+
.type = IIO_EV_TYPE_THRESH,
1193
+
.dir = IIO_EV_DIR_FALLING,
1194
+
.mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
1195
+
},
1196
+
};
1197
+
1198
+
static const struct iio_chan_spec vcnl4000_channels[] = {
1199
+
{
1200
+
.type = IIO_LIGHT,
1201
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1202
+
BIT(IIO_CHAN_INFO_SCALE),
1203
+
}, {
1204
+
.type = IIO_PROXIMITY,
1205
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1206
+
.ext_info = vcnl4000_ext_info,
1207
+
}
1208
+
};
1209
+
1210
+
static const struct iio_chan_spec vcnl4010_channels[] = {
1211
+
{
1212
+
.type = IIO_LIGHT,
1213
+
.scan_index = -1,
1214
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1215
+
BIT(IIO_CHAN_INFO_SCALE),
1216
+
}, {
1217
+
.type = IIO_PROXIMITY,
1218
+
.scan_index = 0,
1219
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1220
+
BIT(IIO_CHAN_INFO_SAMP_FREQ),
1221
+
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
1222
+
.event_spec = vcnl4000_event_spec,
1223
+
.num_event_specs = ARRAY_SIZE(vcnl4000_event_spec),
1224
+
.ext_info = vcnl4000_ext_info,
1225
+
.scan_type = {
1226
+
.sign = 'u',
1227
+
.realbits = 16,
1228
+
.storagebits = 16,
1229
+
.endianness = IIO_CPU,
1230
+
},
1231
+
},
1232
+
IIO_CHAN_SOFT_TIMESTAMP(1),
1233
+
};
1234
+
1235
+
static const struct iio_chan_spec vcnl4040_channels[] = {
1236
+
{
1237
+
.type = IIO_LIGHT,
1238
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1239
+
BIT(IIO_CHAN_INFO_SCALE),
1240
+
}, {
1241
+
.type = IIO_PROXIMITY,
1242
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1243
+
BIT(IIO_CHAN_INFO_INT_TIME),
1244
+
.info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME),
1245
+
.ext_info = vcnl4000_ext_info,
1246
+
.event_spec = vcnl4040_event_spec,
1247
+
.num_event_specs = ARRAY_SIZE(vcnl4040_event_spec),
1248
+
}
1249
+
};
1250
+
1251
+
static const struct iio_info vcnl4000_info = {
1252
+
.read_raw = vcnl4000_read_raw,
1253
+
};
1254
+
1255
+
static const struct iio_info vcnl4010_info = {
1256
+
.read_raw = vcnl4010_read_raw,
1257
+
.read_avail = vcnl4010_read_avail,
1258
+
.write_raw = vcnl4010_write_raw,
1259
+
.read_event_value = vcnl4010_read_event,
1260
+
.write_event_value = vcnl4010_write_event,
1261
+
.read_event_config = vcnl4010_read_event_config,
1262
+
.write_event_config = vcnl4010_write_event_config,
1263
+
};
1264
+
1265
+
static const struct iio_info vcnl4040_info = {
1266
+
.read_raw = vcnl4000_read_raw,
1267
+
.write_raw = vcnl4040_write_raw,
1268
+
.read_event_value = vcnl4040_read_event,
1269
+
.write_event_value = vcnl4040_write_event,
1270
+
.read_event_config = vcnl4040_read_event_config,
1271
+
.write_event_config = vcnl4040_write_event_config,
1272
+
.read_avail = vcnl4040_read_avail,
1273
+
};
1274
+
1275
+
static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = {
1276
+
[VCNL4000] = {
1277
+
.prod = "VCNL4000",
1278
+
.init = vcnl4000_init,
1279
+
.measure_light = vcnl4000_measure_light,
1280
+
.measure_proximity = vcnl4000_measure_proximity,
1281
+
.set_power_state = vcnl4000_set_power_state,
1282
+
.channels = vcnl4000_channels,
1283
+
.num_channels = ARRAY_SIZE(vcnl4000_channels),
1284
+
.info = &vcnl4000_info,
1285
+
},
1286
+
[VCNL4010] = {
1287
+
.prod = "VCNL4010/4020",
1288
+
.init = vcnl4000_init,
1289
+
.measure_light = vcnl4000_measure_light,
1290
+
.measure_proximity = vcnl4000_measure_proximity,
1291
+
.set_power_state = vcnl4000_set_power_state,
1292
+
.channels = vcnl4010_channels,
1293
+
.num_channels = ARRAY_SIZE(vcnl4010_channels),
1294
+
.info = &vcnl4010_info,
1295
+
.irq_thread = vcnl4010_irq_thread,
1296
+
.trig_buffer_func = vcnl4010_trigger_handler,
1297
+
.buffer_setup_ops = &vcnl4010_buffer_ops,
1298
+
},
1299
+
[VCNL4040] = {
1300
+
.prod = "VCNL4040",
1301
+
.init = vcnl4200_init,
1302
+
.measure_light = vcnl4200_measure_light,
1303
+
.measure_proximity = vcnl4200_measure_proximity,
1304
+
.set_power_state = vcnl4200_set_power_state,
1305
+
.channels = vcnl4040_channels,
1306
+
.num_channels = ARRAY_SIZE(vcnl4040_channels),
1307
+
.info = &vcnl4040_info,
1308
+
.irq_thread = vcnl4040_irq_thread,
1309
+
},
1310
+
[VCNL4200] = {
1311
+
.prod = "VCNL4200",
1312
+
.init = vcnl4200_init,
1313
+
.measure_light = vcnl4200_measure_light,
1314
+
.measure_proximity = vcnl4200_measure_proximity,
1315
+
.set_power_state = vcnl4200_set_power_state,
1316
+
.channels = vcnl4000_channels,
1317
+
.num_channels = ARRAY_SIZE(vcnl4000_channels),
1318
+
.info = &vcnl4000_info,
1319
+
},
1320
+
};
1321
+
1170
1322
static const struct iio_trigger_ops vcnl4010_trigger_ops = {
1171
1323
.validate_device = iio_trigger_validate_own_device,
1172
1324
};
···
1384
1214
indio_dev->name = VCNL4000_DRV_NAME;
1385
1215
indio_dev->modes = INDIO_DIRECT_MODE;
1386
1216
1387
-
if (client->irq && data->chip_spec->irq_support) {
1217
+
if (data->chip_spec->trig_buffer_func &&
1218
+
data->chip_spec->buffer_setup_ops) {
1388
1219
ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
1389
1220
NULL,
1390
-
vcnl4010_trigger_handler,
1391
-
&vcnl4010_buffer_ops);
1221
+
data->chip_spec->trig_buffer_func,
1222
+
data->chip_spec->buffer_setup_ops);
1392
1223
if (ret < 0) {
1393
1224
dev_err(&client->dev,
1394
1225
"unable to setup iio triggered buffer\n");
1395
1226
return ret;
1396
1227
}
1228
+
}
1397
1229
1230
+
if (client->irq && data->chip_spec->irq_thread) {
1398
1231
ret = devm_request_threaded_irq(&client->dev, client->irq,
1399
-
NULL, vcnl4010_irq_thread,
1232
+
NULL, data->chip_spec->irq_thread,
1400
1233
IRQF_TRIGGER_FALLING |
1401
1234
IRQF_ONESHOT,
1402
-
"vcnl4010_irq",
1235
+
"vcnl4000_irq",
1403
1236
indio_dev);
1404
1237
if (ret < 0) {
1405
1238
dev_err(&client->dev, "irq request failed\n");
+13
-1
drivers/iio/magnetometer/Kconfig
+13
-1
drivers/iio/magnetometer/Kconfig
···
119
119
select IIO_TRIGGERED_BUFFER if (IIO_BUFFER)
120
120
help
121
121
Say yes here to build support for STMicroelectronics magnetometers:
122
-
LSM303DLHC, LSM303DLM, LIS3MDL.
122
+
LSM303C, LSM303DLHC, LSM303DLM, LIS3MDL.
123
123
124
124
Also need to enable at least one of I2C and SPI interface drivers
125
125
below.
···
207
207
This driver can also be compiled as a module.
208
208
To compile this driver as a module, choose M here: the module
209
209
will be called rm3100-spi.
210
+
211
+
config TI_TMAG5273
212
+
tristate "TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor"
213
+
depends on I2C
214
+
select REGMAP_I2C
215
+
help
216
+
Say Y here to add support for the TI TMAG5273 Low-Power
217
+
Linear 3D Hall-Effect Sensor.
218
+
219
+
This driver can also be compiled as a module.
220
+
To compile this driver as a module, choose M here: the module
221
+
will be called tmag5273.
210
222
211
223
config YAMAHA_YAS530
212
224
tristate "Yamaha YAS530 family of 3-Axis Magnetometers (I2C)"
+2
drivers/iio/magnetometer/Makefile
+2
drivers/iio/magnetometer/Makefile
+1
drivers/iio/magnetometer/st_magn.h
+1
drivers/iio/magnetometer/st_magn.h
+1
drivers/iio/magnetometer/st_magn_core.c
+1
drivers/iio/magnetometer/st_magn_core.c
+5
drivers/iio/magnetometer/st_magn_i2c.c
+5
drivers/iio/magnetometer/st_magn_i2c.c
···
50
50
.compatible = "st,iis2mdc",
51
51
.data = IIS2MDC_MAGN_DEV_NAME,
52
52
},
53
+
{
54
+
.compatible = "st,lsm303c-magn",
55
+
.data = LSM303C_MAGN_DEV_NAME,
56
+
},
53
57
{},
54
58
};
55
59
MODULE_DEVICE_TABLE(of, st_magn_of_match);
···
101
97
{ LIS2MDL_MAGN_DEV_NAME },
102
98
{ LSM9DS1_MAGN_DEV_NAME },
103
99
{ IIS2MDC_MAGN_DEV_NAME },
100
+
{ LSM303C_MAGN_DEV_NAME },
104
101
{},
105
102
};
106
103
MODULE_DEVICE_TABLE(i2c, st_magn_id_table);
+5
drivers/iio/magnetometer/st_magn_spi.c
+5
drivers/iio/magnetometer/st_magn_spi.c
···
45
45
.compatible = "st,iis2mdc",
46
46
.data = IIS2MDC_MAGN_DEV_NAME,
47
47
},
48
+
{
49
+
.compatible = "st,lsm303c-magn",
50
+
.data = LSM303C_MAGN_DEV_NAME,
51
+
},
48
52
{}
49
53
};
50
54
MODULE_DEVICE_TABLE(of, st_magn_of_match);
···
93
89
{ LIS2MDL_MAGN_DEV_NAME },
94
90
{ LSM9DS1_MAGN_DEV_NAME },
95
91
{ IIS2MDC_MAGN_DEV_NAME },
92
+
{ LSM303C_MAGN_DEV_NAME },
96
93
{},
97
94
};
98
95
MODULE_DEVICE_TABLE(spi, st_magn_id_table);
+743
drivers/iio/magnetometer/tmag5273.c
+743
drivers/iio/magnetometer/tmag5273.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Driver for the TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor
4
+
*
5
+
* Copyright (C) 2022 WolfVision GmbH
6
+
*
7
+
* Author: Gerald Loacker <gerald.loacker@wolfvision.net>
8
+
*/
9
+
10
+
#include <linux/bitfield.h>
11
+
#include <linux/bits.h>
12
+
#include <linux/delay.h>
13
+
#include <linux/module.h>
14
+
#include <linux/i2c.h>
15
+
#include <linux/regmap.h>
16
+
#include <linux/pm_runtime.h>
17
+
18
+
#include <linux/iio/iio.h>
19
+
#include <linux/iio/sysfs.h>
20
+
21
+
#define TMAG5273_DEVICE_CONFIG_1 0x00
22
+
#define TMAG5273_DEVICE_CONFIG_2 0x01
23
+
#define TMAG5273_SENSOR_CONFIG_1 0x02
24
+
#define TMAG5273_SENSOR_CONFIG_2 0x03
25
+
#define TMAG5273_X_THR_CONFIG 0x04
26
+
#define TMAG5273_Y_THR_CONFIG 0x05
27
+
#define TMAG5273_Z_THR_CONFIG 0x06
28
+
#define TMAG5273_T_CONFIG 0x07
29
+
#define TMAG5273_INT_CONFIG_1 0x08
30
+
#define TMAG5273_MAG_GAIN_CONFIG 0x09
31
+
#define TMAG5273_MAG_OFFSET_CONFIG_1 0x0A
32
+
#define TMAG5273_MAG_OFFSET_CONFIG_2 0x0B
33
+
#define TMAG5273_I2C_ADDRESS 0x0C
34
+
#define TMAG5273_DEVICE_ID 0x0D
35
+
#define TMAG5273_MANUFACTURER_ID_LSB 0x0E
36
+
#define TMAG5273_MANUFACTURER_ID_MSB 0x0F
37
+
#define TMAG5273_T_MSB_RESULT 0x10
38
+
#define TMAG5273_T_LSB_RESULT 0x11
39
+
#define TMAG5273_X_MSB_RESULT 0x12
40
+
#define TMAG5273_X_LSB_RESULT 0x13
41
+
#define TMAG5273_Y_MSB_RESULT 0x14
42
+
#define TMAG5273_Y_LSB_RESULT 0x15
43
+
#define TMAG5273_Z_MSB_RESULT 0x16
44
+
#define TMAG5273_Z_LSB_RESULT 0x17
45
+
#define TMAG5273_CONV_STATUS 0x18
46
+
#define TMAG5273_ANGLE_RESULT_MSB 0x19
47
+
#define TMAG5273_ANGLE_RESULT_LSB 0x1A
48
+
#define TMAG5273_MAGNITUDE_RESULT 0x1B
49
+
#define TMAG5273_DEVICE_STATUS 0x1C
50
+
#define TMAG5273_MAX_REG TMAG5273_DEVICE_STATUS
51
+
52
+
#define TMAG5273_AUTOSLEEP_DELAY_MS 5000
53
+
#define TMAG5273_MAX_AVERAGE 32
54
+
55
+
/*
56
+
* bits in the TMAG5273_MANUFACTURER_ID_LSB / MSB register
57
+
* 16-bit unique manufacturer ID 0x49 / 0x54 = "TI"
58
+
*/
59
+
#define TMAG5273_MANUFACTURER_ID 0x5449
60
+
61
+
/* bits in the TMAG5273_DEVICE_CONFIG_1 register */
62
+
#define TMAG5273_AVG_MODE_MASK GENMASK(4, 2)
63
+
#define TMAG5273_AVG_1_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 0)
64
+
#define TMAG5273_AVG_2_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 1)
65
+
#define TMAG5273_AVG_4_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 2)
66
+
#define TMAG5273_AVG_8_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 3)
67
+
#define TMAG5273_AVG_16_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 4)
68
+
#define TMAG5273_AVG_32_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 5)
69
+
70
+
/* bits in the TMAG5273_DEVICE_CONFIG_2 register */
71
+
#define TMAG5273_OP_MODE_MASK GENMASK(1, 0)
72
+
#define TMAG5273_OP_MODE_STANDBY FIELD_PREP(TMAG5273_OP_MODE_MASK, 0)
73
+
#define TMAG5273_OP_MODE_SLEEP FIELD_PREP(TMAG5273_OP_MODE_MASK, 1)
74
+
#define TMAG5273_OP_MODE_CONT FIELD_PREP(TMAG5273_OP_MODE_MASK, 2)
75
+
#define TMAG5273_OP_MODE_WAKEUP FIELD_PREP(TMAG5273_OP_MODE_MASK, 3)
76
+
77
+
/* bits in the TMAG5273_SENSOR_CONFIG_1 register */
78
+
#define TMAG5273_MAG_CH_EN_MASK GENMASK(7, 4)
79
+
#define TMAG5273_MAG_CH_EN_X_Y_Z 7
80
+
81
+
/* bits in the TMAG5273_SENSOR_CONFIG_2 register */
82
+
#define TMAG5273_Z_RANGE_MASK BIT(0)
83
+
#define TMAG5273_X_Y_RANGE_MASK BIT(1)
84
+
#define TMAG5273_ANGLE_EN_MASK GENMASK(3, 2)
85
+
#define TMAG5273_ANGLE_EN_OFF 0
86
+
#define TMAG5273_ANGLE_EN_X_Y 1
87
+
#define TMAG5273_ANGLE_EN_Y_Z 2
88
+
#define TMAG5273_ANGLE_EN_X_Z 3
89
+
90
+
/* bits in the TMAG5273_T_CONFIG register */
91
+
#define TMAG5273_T_CH_EN BIT(0)
92
+
93
+
/* bits in the TMAG5273_DEVICE_ID register */
94
+
#define TMAG5273_VERSION_MASK GENMASK(1, 0)
95
+
96
+
/* bits in the TMAG5273_CONV_STATUS register */
97
+
#define TMAG5273_CONV_STATUS_COMPLETE BIT(0)
98
+
99
+
enum tmag5273_channels {
100
+
TEMPERATURE = 0,
101
+
AXIS_X,
102
+
AXIS_Y,
103
+
AXIS_Z,
104
+
ANGLE,
105
+
MAGNITUDE,
106
+
};
107
+
108
+
enum tmag5273_scale_index {
109
+
MAGN_RANGE_LOW = 0,
110
+
MAGN_RANGE_HIGH,
111
+
MAGN_RANGE_NUM
112
+
};
113
+
114
+
/* state container for the TMAG5273 driver */
115
+
struct tmag5273_data {
116
+
struct device *dev;
117
+
unsigned int devid;
118
+
unsigned int version;
119
+
char name[16];
120
+
unsigned int conv_avg;
121
+
unsigned int scale;
122
+
enum tmag5273_scale_index scale_index;
123
+
unsigned int angle_measurement;
124
+
struct regmap *map;
125
+
struct regulator *vcc;
126
+
127
+
/*
128
+
* Locks the sensor for exclusive use during a measurement (which
129
+
* involves several register transactions so the regmap lock is not
130
+
* enough) so that measurements get serialized in a
131
+
* first-come-first-serve manner.
132
+
*/
133
+
struct mutex lock;
134
+
};
135
+
136
+
static const char *const tmag5273_angle_names[] = { "off", "x-y", "y-z", "x-z" };
137
+
138
+
/*
139
+
* Averaging enables additional sampling of the sensor data to reduce the noise
140
+
* effect, but also increases conversion time.
141
+
*/
142
+
static const unsigned int tmag5273_avg_table[] = {
143
+
1, 2, 4, 8, 16, 32,
144
+
};
145
+
146
+
/*
147
+
* Magnetic resolution in Gauss for different TMAG5273 versions.
148
+
* Scale[Gauss] = Range[mT] * 1000 / 2^15 * 10, (1 mT = 10 Gauss)
149
+
* Only version 1 and 2 are valid, version 0 and 3 are reserved.
150
+
*/
151
+
static const struct iio_val_int_plus_micro tmag5273_scale[][MAGN_RANGE_NUM] = {
152
+
{ { 0, 0 }, { 0, 0 } },
153
+
{ { 0, 12200 }, { 0, 24400 } },
154
+
{ { 0, 40600 }, { 0, 81200 } },
155
+
{ { 0, 0 }, { 0, 0 } },
156
+
};
157
+
158
+
static int tmag5273_get_measure(struct tmag5273_data *data, s16 *t, s16 *x,
159
+
s16 *y, s16 *z, u16 *angle, u16 *magnitude)
160
+
{
161
+
unsigned int status, val;
162
+
__be16 reg_data[4];
163
+
int ret;
164
+
165
+
mutex_lock(&data->lock);
166
+
167
+
/*
168
+
* Max. conversion time is 2425 us in 32x averaging mode for all three
169
+
* channels. Since we are in continuous measurement mode, a measurement
170
+
* may already be there, so poll for completed measurement with
171
+
* timeout.
172
+
*/
173
+
ret = regmap_read_poll_timeout(data->map, TMAG5273_CONV_STATUS, status,
174
+
status & TMAG5273_CONV_STATUS_COMPLETE,
175
+
100, 10000);
176
+
if (ret) {
177
+
dev_err(data->dev, "timeout waiting for measurement\n");
178
+
goto out_unlock;
179
+
}
180
+
181
+
ret = regmap_bulk_read(data->map, TMAG5273_T_MSB_RESULT, reg_data,
182
+
sizeof(reg_data));
183
+
if (ret)
184
+
goto out_unlock;
185
+
*t = be16_to_cpu(reg_data[0]);
186
+
*x = be16_to_cpu(reg_data[1]);
187
+
*y = be16_to_cpu(reg_data[2]);
188
+
*z = be16_to_cpu(reg_data[3]);
189
+
190
+
ret = regmap_bulk_read(data->map, TMAG5273_ANGLE_RESULT_MSB,
191
+
®_data[0], sizeof(reg_data[0]));
192
+
if (ret)
193
+
goto out_unlock;
194
+
/*
195
+
* angle has 9 bits integer value and 4 bits fractional part
196
+
* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
197
+
* 0 0 0 a a a a a a a a a f f f f
198
+
*/
199
+
*angle = be16_to_cpu(reg_data[0]);
200
+
201
+
ret = regmap_read(data->map, TMAG5273_MAGNITUDE_RESULT, &val);
202
+
if (ret < 0)
203
+
goto out_unlock;
204
+
*magnitude = val;
205
+
206
+
out_unlock:
207
+
mutex_unlock(&data->lock);
208
+
return ret;
209
+
}
210
+
211
+
static int tmag5273_write_osr(struct tmag5273_data *data, int val)
212
+
{
213
+
int i;
214
+
215
+
if (val == data->conv_avg)
216
+
return 0;
217
+
218
+
for (i = 0; i < ARRAY_SIZE(tmag5273_avg_table); i++) {
219
+
if (tmag5273_avg_table[i] == val)
220
+
break;
221
+
}
222
+
if (i == ARRAY_SIZE(tmag5273_avg_table))
223
+
return -EINVAL;
224
+
data->conv_avg = val;
225
+
226
+
return regmap_update_bits(data->map, TMAG5273_DEVICE_CONFIG_1,
227
+
TMAG5273_AVG_MODE_MASK,
228
+
FIELD_PREP(TMAG5273_AVG_MODE_MASK, i));
229
+
}
230
+
231
+
static int tmag5273_write_scale(struct tmag5273_data *data, int scale_micro)
232
+
{
233
+
u32 value;
234
+
int i;
235
+
236
+
for (i = 0; i < ARRAY_SIZE(tmag5273_scale[0]); i++) {
237
+
if (tmag5273_scale[data->version][i].micro == scale_micro)
238
+
break;
239
+
}
240
+
if (i == ARRAY_SIZE(tmag5273_scale[0]))
241
+
return -EINVAL;
242
+
data->scale_index = i;
243
+
244
+
if (data->scale_index == MAGN_RANGE_LOW)
245
+
value = 0;
246
+
else
247
+
value = TMAG5273_Z_RANGE_MASK | TMAG5273_X_Y_RANGE_MASK;
248
+
249
+
return regmap_update_bits(data->map, TMAG5273_SENSOR_CONFIG_2,
250
+
TMAG5273_Z_RANGE_MASK | TMAG5273_X_Y_RANGE_MASK, value);
251
+
}
252
+
253
+
static int tmag5273_read_avail(struct iio_dev *indio_dev,
254
+
struct iio_chan_spec const *chan,
255
+
const int **vals, int *type, int *length,
256
+
long mask)
257
+
{
258
+
struct tmag5273_data *data = iio_priv(indio_dev);
259
+
260
+
switch (mask) {
261
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
262
+
*vals = tmag5273_avg_table;
263
+
*type = IIO_VAL_INT;
264
+
*length = ARRAY_SIZE(tmag5273_avg_table);
265
+
return IIO_AVAIL_LIST;
266
+
case IIO_CHAN_INFO_SCALE:
267
+
switch (chan->type) {
268
+
case IIO_MAGN:
269
+
*type = IIO_VAL_INT_PLUS_MICRO;
270
+
*vals = (int *)tmag5273_scale[data->version];
271
+
*length = ARRAY_SIZE(tmag5273_scale[data->version]) *
272
+
MAGN_RANGE_NUM;
273
+
return IIO_AVAIL_LIST;
274
+
default:
275
+
return -EINVAL;
276
+
}
277
+
default:
278
+
return -EINVAL;
279
+
}
280
+
}
281
+
282
+
static int tmag5273_read_raw(struct iio_dev *indio_dev,
283
+
const struct iio_chan_spec *chan, int *val,
284
+
int *val2, long mask)
285
+
{
286
+
struct tmag5273_data *data = iio_priv(indio_dev);
287
+
s16 t, x, y, z;
288
+
u16 angle, magnitude;
289
+
int ret;
290
+
291
+
switch (mask) {
292
+
case IIO_CHAN_INFO_PROCESSED:
293
+
case IIO_CHAN_INFO_RAW:
294
+
ret = pm_runtime_resume_and_get(data->dev);
295
+
if (ret < 0)
296
+
return ret;
297
+
298
+
ret = tmag5273_get_measure(data, &t, &x, &y, &z, &angle, &magnitude);
299
+
if (ret)
300
+
return ret;
301
+
302
+
pm_runtime_mark_last_busy(data->dev);
303
+
pm_runtime_put_autosuspend(data->dev);
304
+
305
+
switch (chan->address) {
306
+
case TEMPERATURE:
307
+
*val = t;
308
+
return IIO_VAL_INT;
309
+
case AXIS_X:
310
+
*val = x;
311
+
return IIO_VAL_INT;
312
+
case AXIS_Y:
313
+
*val = y;
314
+
return IIO_VAL_INT;
315
+
case AXIS_Z:
316
+
*val = z;
317
+
return IIO_VAL_INT;
318
+
case ANGLE:
319
+
*val = angle;
320
+
return IIO_VAL_INT;
321
+
case MAGNITUDE:
322
+
*val = magnitude;
323
+
return IIO_VAL_INT;
324
+
default:
325
+
return -EINVAL;
326
+
}
327
+
case IIO_CHAN_INFO_SCALE:
328
+
switch (chan->type) {
329
+
case IIO_TEMP:
330
+
/*
331
+
* Convert device specific value to millicelsius.
332
+
* Resolution from the sensor is 60.1 LSB/celsius and
333
+
* the reference value at 25 celsius is 17508 LSBs.
334
+
*/
335
+
*val = 10000;
336
+
*val2 = 601;
337
+
return IIO_VAL_FRACTIONAL;
338
+
case IIO_MAGN:
339
+
/* Magnetic resolution in uT */
340
+
*val = 0;
341
+
*val2 = tmag5273_scale[data->version]
342
+
[data->scale_index].micro;
343
+
return IIO_VAL_INT_PLUS_MICRO;
344
+
case IIO_ANGL:
345
+
/*
346
+
* Angle is in degrees and has four fractional bits,
347
+
* therefore use 1/16 * pi/180 to convert to radians.
348
+
*/
349
+
*val = 1000;
350
+
*val2 = 916732;
351
+
return IIO_VAL_FRACTIONAL;
352
+
default:
353
+
return -EINVAL;
354
+
}
355
+
case IIO_CHAN_INFO_OFFSET:
356
+
switch (chan->type) {
357
+
case IIO_TEMP:
358
+
*val = -266314;
359
+
return IIO_VAL_INT;
360
+
default:
361
+
return -EINVAL;
362
+
}
363
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
364
+
*val = data->conv_avg;
365
+
return IIO_VAL_INT;
366
+
367
+
default:
368
+
return -EINVAL;
369
+
}
370
+
}
371
+
372
+
static int tmag5273_write_raw(struct iio_dev *indio_dev,
373
+
struct iio_chan_spec const *chan, int val,
374
+
int val2, long mask)
375
+
{
376
+
struct tmag5273_data *data = iio_priv(indio_dev);
377
+
378
+
switch (mask) {
379
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
380
+
return tmag5273_write_osr(data, val);
381
+
case IIO_CHAN_INFO_SCALE:
382
+
switch (chan->type) {
383
+
case IIO_MAGN:
384
+
if (val)
385
+
return -EINVAL;
386
+
return tmag5273_write_scale(data, val2);
387
+
default:
388
+
return -EINVAL;
389
+
}
390
+
default:
391
+
return -EINVAL;
392
+
}
393
+
}
394
+
395
+
#define TMAG5273_AXIS_CHANNEL(axis, index) \
396
+
{ \
397
+
.type = IIO_MAGN, \
398
+
.modified = 1, \
399
+
.channel2 = IIO_MOD_##axis, \
400
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
401
+
BIT(IIO_CHAN_INFO_SCALE), \
402
+
.info_mask_shared_by_type_available = \
403
+
BIT(IIO_CHAN_INFO_SCALE), \
404
+
.info_mask_shared_by_all = \
405
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
406
+
.info_mask_shared_by_all_available = \
407
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
408
+
.address = index, \
409
+
.scan_index = index, \
410
+
.scan_type = { \
411
+
.sign = 's', \
412
+
.realbits = 16, \
413
+
.storagebits = 16, \
414
+
.endianness = IIO_CPU, \
415
+
}, \
416
+
}
417
+
418
+
static const struct iio_chan_spec tmag5273_channels[] = {
419
+
{
420
+
.type = IIO_TEMP,
421
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
422
+
BIT(IIO_CHAN_INFO_SCALE) |
423
+
BIT(IIO_CHAN_INFO_OFFSET),
424
+
.address = TEMPERATURE,
425
+
.scan_index = TEMPERATURE,
426
+
.scan_type = {
427
+
.sign = 'u',
428
+
.realbits = 16,
429
+
.storagebits = 16,
430
+
.endianness = IIO_CPU,
431
+
},
432
+
},
433
+
TMAG5273_AXIS_CHANNEL(X, AXIS_X),
434
+
TMAG5273_AXIS_CHANNEL(Y, AXIS_Y),
435
+
TMAG5273_AXIS_CHANNEL(Z, AXIS_Z),
436
+
{
437
+
.type = IIO_ANGL,
438
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
439
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
440
+
.info_mask_shared_by_all =
441
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
442
+
.info_mask_shared_by_all_available =
443
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
444
+
.address = ANGLE,
445
+
.scan_index = ANGLE,
446
+
.scan_type = {
447
+
.sign = 'u',
448
+
.realbits = 16,
449
+
.storagebits = 16,
450
+
.endianness = IIO_CPU,
451
+
},
452
+
},
453
+
{
454
+
.type = IIO_DISTANCE,
455
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
456
+
.info_mask_shared_by_all =
457
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
458
+
.info_mask_shared_by_all_available =
459
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
460
+
.address = MAGNITUDE,
461
+
.scan_index = MAGNITUDE,
462
+
.scan_type = {
463
+
.sign = 'u',
464
+
.realbits = 16,
465
+
.storagebits = 16,
466
+
.endianness = IIO_CPU,
467
+
},
468
+
},
469
+
IIO_CHAN_SOFT_TIMESTAMP(6),
470
+
};
471
+
472
+
static const struct iio_info tmag5273_info = {
473
+
.read_avail = tmag5273_read_avail,
474
+
.read_raw = tmag5273_read_raw,
475
+
.write_raw = tmag5273_write_raw,
476
+
};
477
+
478
+
static bool tmag5273_volatile_reg(struct device *dev, unsigned int reg)
479
+
{
480
+
return reg >= TMAG5273_T_MSB_RESULT && reg <= TMAG5273_MAGNITUDE_RESULT;
481
+
}
482
+
483
+
static const struct regmap_config tmag5273_regmap_config = {
484
+
.reg_bits = 8,
485
+
.val_bits = 8,
486
+
.max_register = TMAG5273_MAX_REG,
487
+
.volatile_reg = tmag5273_volatile_reg,
488
+
};
489
+
490
+
static int tmag5273_set_operating_mode(struct tmag5273_data *data,
491
+
unsigned int val)
492
+
{
493
+
return regmap_write(data->map, TMAG5273_DEVICE_CONFIG_2, val);
494
+
}
495
+
496
+
static void tmag5273_read_device_property(struct tmag5273_data *data)
497
+
{
498
+
struct device *dev = data->dev;
499
+
const char *str;
500
+
int ret;
501
+
502
+
data->angle_measurement = TMAG5273_ANGLE_EN_X_Y;
503
+
504
+
ret = device_property_read_string(dev, "ti,angle-measurement", &str);
505
+
if (ret)
506
+
return;
507
+
508
+
ret = match_string(tmag5273_angle_names,
509
+
ARRAY_SIZE(tmag5273_angle_names), str);
510
+
if (ret >= 0)
511
+
data->angle_measurement = ret;
512
+
}
513
+
514
+
static void tmag5273_wake_up(struct tmag5273_data *data)
515
+
{
516
+
int val;
517
+
518
+
/* Wake up the chip by sending a dummy I2C command */
519
+
regmap_read(data->map, TMAG5273_DEVICE_ID, &val);
520
+
/*
521
+
* Time to go to stand-by mode from sleep mode is 50us
522
+
* typically, during this time no I2C access is possible.
523
+
*/
524
+
usleep_range(80, 200);
525
+
}
526
+
527
+
static int tmag5273_chip_init(struct tmag5273_data *data)
528
+
{
529
+
int ret;
530
+
531
+
ret = regmap_write(data->map, TMAG5273_DEVICE_CONFIG_1,
532
+
TMAG5273_AVG_32_MODE);
533
+
if (ret)
534
+
return ret;
535
+
data->conv_avg = 32;
536
+
537
+
ret = regmap_write(data->map, TMAG5273_DEVICE_CONFIG_2,
538
+
TMAG5273_OP_MODE_CONT);
539
+
if (ret)
540
+
return ret;
541
+
542
+
ret = regmap_write(data->map, TMAG5273_SENSOR_CONFIG_1,
543
+
FIELD_PREP(TMAG5273_MAG_CH_EN_MASK,
544
+
TMAG5273_MAG_CH_EN_X_Y_Z));
545
+
if (ret)
546
+
return ret;
547
+
548
+
ret = regmap_write(data->map, TMAG5273_SENSOR_CONFIG_2,
549
+
FIELD_PREP(TMAG5273_ANGLE_EN_MASK,
550
+
data->angle_measurement));
551
+
if (ret)
552
+
return ret;
553
+
data->scale_index = MAGN_RANGE_LOW;
554
+
555
+
return regmap_write(data->map, TMAG5273_T_CONFIG, TMAG5273_T_CH_EN);
556
+
}
557
+
558
+
static int tmag5273_check_device_id(struct tmag5273_data *data)
559
+
{
560
+
__le16 devid;
561
+
int val, ret;
562
+
563
+
ret = regmap_read(data->map, TMAG5273_DEVICE_ID, &val);
564
+
if (ret)
565
+
return dev_err_probe(data->dev, ret, "failed to power on device\n");
566
+
data->version = FIELD_PREP(TMAG5273_VERSION_MASK, val);
567
+
568
+
ret = regmap_bulk_read(data->map, TMAG5273_MANUFACTURER_ID_LSB, &devid,
569
+
sizeof(devid));
570
+
if (ret)
571
+
return dev_err_probe(data->dev, ret, "failed to read device ID\n");
572
+
data->devid = le16_to_cpu(devid);
573
+
574
+
switch (data->devid) {
575
+
case TMAG5273_MANUFACTURER_ID:
576
+
/*
577
+
* The device name matches the orderable part number. 'x' stands
578
+
* for A, B, C or D devices, which have different I2C addresses.
579
+
* Versions 1 or 2 (0 and 3 is reserved) stands for different
580
+
* magnetic strengths.
581
+
*/
582
+
snprintf(data->name, sizeof(data->name), "tmag5273x%1u", data->version);
583
+
if (data->version < 1 || data->version > 2)
584
+
dev_warn(data->dev, "Unsupported device %s\n", data->name);
585
+
return 0;
586
+
default:
587
+
/*
588
+
* Only print warning in case of unknown device ID to allow
589
+
* fallback compatible in device tree.
590
+
*/
591
+
dev_warn(data->dev, "Unknown device ID 0x%x\n", data->devid);
592
+
return 0;
593
+
}
594
+
}
595
+
596
+
static void tmag5273_power_down(void *data)
597
+
{
598
+
tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_SLEEP);
599
+
}
600
+
601
+
static int tmag5273_probe(struct i2c_client *i2c)
602
+
{
603
+
struct device *dev = &i2c->dev;
604
+
struct tmag5273_data *data;
605
+
struct iio_dev *indio_dev;
606
+
int ret;
607
+
608
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
609
+
if (!indio_dev)
610
+
return -ENOMEM;
611
+
612
+
data = iio_priv(indio_dev);
613
+
data->dev = dev;
614
+
i2c_set_clientdata(i2c, indio_dev);
615
+
616
+
data->map = devm_regmap_init_i2c(i2c, &tmag5273_regmap_config);
617
+
if (IS_ERR(data->map))
618
+
return dev_err_probe(dev, PTR_ERR(data->map),
619
+
"failed to allocate register map\n");
620
+
621
+
mutex_init(&data->lock);
622
+
623
+
ret = devm_regulator_get_enable(dev, "vcc");
624
+
if (ret)
625
+
return dev_err_probe(dev, ret, "failed to enable regulator\n");
626
+
627
+
tmag5273_wake_up(data);
628
+
629
+
ret = tmag5273_check_device_id(data);
630
+
if (ret)
631
+
return ret;
632
+
633
+
ret = tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_CONT);
634
+
if (ret)
635
+
return dev_err_probe(dev, ret, "failed to power on device\n");
636
+
637
+
/*
638
+
* Register powerdown deferred callback which suspends the chip
639
+
* after module unloaded.
640
+
*
641
+
* TMAG5273 should be in SUSPEND mode in the two cases:
642
+
* 1) When driver is loaded, but we do not have any data or
643
+
* configuration requests to it (we are solving it using
644
+
* autosuspend feature).
645
+
* 2) When driver is unloaded and device is not used (devm action is
646
+
* used in this case).
647
+
*/
648
+
ret = devm_add_action_or_reset(dev, tmag5273_power_down, data);
649
+
if (ret)
650
+
return dev_err_probe(dev, ret, "failed to add powerdown action\n");
651
+
652
+
ret = pm_runtime_set_active(dev);
653
+
if (ret < 0)
654
+
return ret;
655
+
656
+
ret = devm_pm_runtime_enable(dev);
657
+
if (ret)
658
+
return ret;
659
+
660
+
pm_runtime_get_noresume(dev);
661
+
pm_runtime_set_autosuspend_delay(dev, TMAG5273_AUTOSLEEP_DELAY_MS);
662
+
pm_runtime_use_autosuspend(dev);
663
+
664
+
tmag5273_read_device_property(data);
665
+
666
+
ret = tmag5273_chip_init(data);
667
+
if (ret)
668
+
return dev_err_probe(dev, ret, "failed to init device\n");
669
+
670
+
indio_dev->info = &tmag5273_info;
671
+
indio_dev->modes = INDIO_DIRECT_MODE;
672
+
indio_dev->name = data->name;
673
+
indio_dev->channels = tmag5273_channels;
674
+
indio_dev->num_channels = ARRAY_SIZE(tmag5273_channels);
675
+
676
+
pm_runtime_mark_last_busy(dev);
677
+
pm_runtime_put_autosuspend(dev);
678
+
679
+
ret = devm_iio_device_register(dev, indio_dev);
680
+
if (ret)
681
+
return dev_err_probe(dev, ret, "device register failed\n");
682
+
683
+
return 0;
684
+
}
685
+
686
+
static int tmag5273_runtime_suspend(struct device *dev)
687
+
{
688
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
689
+
struct tmag5273_data *data = iio_priv(indio_dev);
690
+
int ret;
691
+
692
+
ret = tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_SLEEP);
693
+
if (ret)
694
+
dev_err(dev, "failed to power off device (%pe)\n", ERR_PTR(ret));
695
+
696
+
return ret;
697
+
}
698
+
699
+
static int tmag5273_runtime_resume(struct device *dev)
700
+
{
701
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
702
+
struct tmag5273_data *data = iio_priv(indio_dev);
703
+
int ret;
704
+
705
+
tmag5273_wake_up(data);
706
+
707
+
ret = tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_CONT);
708
+
if (ret)
709
+
dev_err(dev, "failed to power on device (%pe)\n", ERR_PTR(ret));
710
+
711
+
return ret;
712
+
}
713
+
714
+
static DEFINE_RUNTIME_DEV_PM_OPS(tmag5273_pm_ops,
715
+
tmag5273_runtime_suspend, tmag5273_runtime_resume,
716
+
NULL);
717
+
718
+
static const struct i2c_device_id tmag5273_id[] = {
719
+
{ "tmag5273" },
720
+
{ /* sentinel */ }
721
+
};
722
+
MODULE_DEVICE_TABLE(i2c, tmag5273_id);
723
+
724
+
static const struct of_device_id tmag5273_of_match[] = {
725
+
{ .compatible = "ti,tmag5273" },
726
+
{ /* sentinel */ }
727
+
};
728
+
MODULE_DEVICE_TABLE(of, tmag5273_of_match);
729
+
730
+
static struct i2c_driver tmag5273_driver = {
731
+
.driver = {
732
+
.name = "tmag5273",
733
+
.of_match_table = tmag5273_of_match,
734
+
.pm = pm_ptr(&tmag5273_pm_ops),
735
+
},
736
+
.probe_new = tmag5273_probe,
737
+
.id_table = tmag5273_id,
738
+
};
739
+
module_i2c_driver(tmag5273_driver);
740
+
741
+
MODULE_DESCRIPTION("TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor driver");
742
+
MODULE_AUTHOR("Gerald Loacker <gerald.loacker@wolfvision.net>");
743
+
MODULE_LICENSE("GPL");
-4
drivers/iio/pressure/ms5611.h
-4
drivers/iio/pressure/ms5611.h
···
13
13
#include <linux/iio/iio.h>
14
14
#include <linux/mutex.h>
15
15
16
-
struct regulator;
17
-
18
16
#define MS5611_RESET 0x1e
19
17
#define MS5611_READ_ADC 0x00
20
18
#define MS5611_READ_PROM_WORD 0xA0
···
50
52
51
53
int (*compensate_temp_and_pressure)(struct ms5611_state *st, s32 *temp,
52
54
s32 *pressure);
53
-
struct regulator *vdd;
54
55
};
55
56
56
57
int ms5611_probe(struct iio_dev *indio_dev, struct device *dev,
57
58
const char *name, int type);
58
-
void ms5611_remove(struct iio_dev *indio_dev);
59
59
60
60
#endif /* _MS5611_H */
+8
-41
drivers/iio/pressure/ms5611_core.c
+8
-41
drivers/iio/pressure/ms5611_core.c
···
380
380
static int ms5611_init(struct iio_dev *indio_dev)
381
381
{
382
382
int ret;
383
-
struct ms5611_state *st = iio_priv(indio_dev);
384
383
385
384
/* Enable attached regulator if any. */
386
-
st->vdd = devm_regulator_get(indio_dev->dev.parent, "vdd");
387
-
if (IS_ERR(st->vdd))
388
-
return PTR_ERR(st->vdd);
389
-
390
-
ret = regulator_enable(st->vdd);
391
-
if (ret) {
392
-
dev_err(indio_dev->dev.parent,
393
-
"failed to enable Vdd supply: %d\n", ret);
385
+
ret = devm_regulator_get_enable(indio_dev->dev.parent, "vdd");
386
+
if (ret)
394
387
return ret;
395
-
}
396
388
397
389
ret = ms5611_reset(indio_dev);
398
390
if (ret < 0)
399
-
goto err_regulator_disable;
391
+
return ret;
400
392
401
393
ret = ms5611_read_prom(indio_dev);
402
394
if (ret < 0)
403
-
goto err_regulator_disable;
395
+
return ret;
404
396
405
397
return 0;
406
-
407
-
err_regulator_disable:
408
-
regulator_disable(st->vdd);
409
-
return ret;
410
-
}
411
-
412
-
static void ms5611_fini(const struct iio_dev *indio_dev)
413
-
{
414
-
const struct ms5611_state *st = iio_priv(indio_dev);
415
-
416
-
regulator_disable(st->vdd);
417
398
}
418
399
419
400
int ms5611_probe(struct iio_dev *indio_dev, struct device *dev,
···
434
453
if (ret < 0)
435
454
return ret;
436
455
437
-
ret = iio_triggered_buffer_setup(indio_dev, NULL,
456
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
438
457
ms5611_trigger_handler, NULL);
439
458
if (ret < 0) {
440
459
dev_err(dev, "iio triggered buffer setup failed\n");
441
-
goto err_fini;
460
+
return ret;
442
461
}
443
462
444
-
ret = iio_device_register(indio_dev);
463
+
ret = devm_iio_device_register(dev, indio_dev);
445
464
if (ret < 0) {
446
465
dev_err(dev, "unable to register iio device\n");
447
-
goto err_buffer_cleanup;
466
+
return ret;
448
467
}
449
468
450
469
return 0;
451
-
452
-
err_buffer_cleanup:
453
-
iio_triggered_buffer_cleanup(indio_dev);
454
-
err_fini:
455
-
ms5611_fini(indio_dev);
456
-
return ret;
457
470
}
458
471
EXPORT_SYMBOL_NS(ms5611_probe, IIO_MS5611);
459
-
460
-
void ms5611_remove(struct iio_dev *indio_dev)
461
-
{
462
-
iio_device_unregister(indio_dev);
463
-
iio_triggered_buffer_cleanup(indio_dev);
464
-
ms5611_fini(indio_dev);
465
-
}
466
-
EXPORT_SYMBOL_NS(ms5611_remove, IIO_MS5611);
467
472
468
473
MODULE_AUTHOR("Tomasz Duszynski <tduszyns@gmail.com>");
469
474
MODULE_DESCRIPTION("MS5611 core driver");
-6
drivers/iio/pressure/ms5611_i2c.c
-6
drivers/iio/pressure/ms5611_i2c.c
···
105
105
return ms5611_probe(indio_dev, &client->dev, id->name, id->driver_data);
106
106
}
107
107
108
-
static void ms5611_i2c_remove(struct i2c_client *client)
109
-
{
110
-
ms5611_remove(i2c_get_clientdata(client));
111
-
}
112
-
113
108
static const struct of_device_id ms5611_i2c_matches[] = {
114
109
{ .compatible = "meas,ms5611" },
115
110
{ .compatible = "meas,ms5607" },
···
126
131
},
127
132
.id_table = ms5611_id,
128
133
.probe_new = ms5611_i2c_probe,
129
-
.remove = ms5611_i2c_remove,
130
134
};
131
135
module_i2c_driver(ms5611_driver);
132
136
-6
drivers/iio/pressure/ms5611_spi.c
-6
drivers/iio/pressure/ms5611_spi.c
···
107
107
spi_get_device_id(spi)->driver_data);
108
108
}
109
109
110
-
static void ms5611_spi_remove(struct spi_device *spi)
111
-
{
112
-
ms5611_remove(spi_get_drvdata(spi));
113
-
}
114
-
115
110
static const struct of_device_id ms5611_spi_matches[] = {
116
111
{ .compatible = "meas,ms5611" },
117
112
{ .compatible = "meas,ms5607" },
···
128
133
},
129
134
.id_table = ms5611_id,
130
135
.probe = ms5611_spi_probe,
131
-
.remove = ms5611_spi_remove,
132
136
};
133
137
module_spi_driver(ms5611_driver);
134
138
+9
-5
drivers/interconnect/core.c
+9
-5
drivers/interconnect/core.c
···
1079
1079
}
1080
1080
EXPORT_SYMBOL_GPL(icc_provider_del);
1081
1081
1082
+
static const struct of_device_id __maybe_unused ignore_list[] = {
1083
+
{ .compatible = "qcom,sc7180-ipa-virt" },
1084
+
{ .compatible = "qcom,sc8180x-ipa-virt" },
1085
+
{ .compatible = "qcom,sdx55-ipa-virt" },
1086
+
{ .compatible = "qcom,sm8150-ipa-virt" },
1087
+
{ .compatible = "qcom,sm8250-ipa-virt" },
1088
+
{}
1089
+
};
1090
+
1082
1091
static int of_count_icc_providers(struct device_node *np)
1083
1092
{
1084
1093
struct device_node *child;
1085
1094
int count = 0;
1086
-
const struct of_device_id __maybe_unused ignore_list[] = {
1087
-
{ .compatible = "qcom,sc7180-ipa-virt" },
1088
-
{ .compatible = "qcom,sdx55-ipa-virt" },
1089
-
{}
1090
-
};
1091
1095
1092
1096
for_each_available_child_of_node(np, child) {
1093
1097
if (of_property_read_bool(child, "#interconnect-cells") &&
+18
drivers/interconnect/qcom/Kconfig
+18
drivers/interconnect/qcom/Kconfig
···
92
92
config INTERCONNECT_QCOM_RPMH
93
93
tristate
94
94
95
+
config INTERCONNECT_QCOM_SA8775P
96
+
tristate "Qualcomm SA8775P interconnect driver"
97
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
98
+
select INTERCONNECT_QCOM_RPMH
99
+
select INTERCONNECT_QCOM_BCM_VOTER
100
+
help
101
+
This is a driver for the Qualcomm Network-on-Chip on sa8775p-based
102
+
platforms.
103
+
95
104
config INTERCONNECT_QCOM_SC7180
96
105
tristate "Qualcomm SC7180 interconnect driver"
97
106
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
···
144
135
select INTERCONNECT_QCOM_SMD_RPM
145
136
help
146
137
This is a driver for the Qualcomm Network-on-Chip on sdm660-based
138
+
platforms.
139
+
140
+
config INTERCONNECT_QCOM_SDM670
141
+
tristate "Qualcomm SDM670 interconnect driver"
142
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
143
+
select INTERCONNECT_QCOM_RPMH
144
+
select INTERCONNECT_QCOM_BCM_VOTER
145
+
help
146
+
This is a driver for the Qualcomm Network-on-Chip on sdm670-based
147
147
platforms.
148
148
149
149
config INTERCONNECT_QCOM_SDM845
+4
drivers/interconnect/qcom/Makefile
+4
drivers/interconnect/qcom/Makefile
···
13
13
qnoc-qcs404-objs := qcs404.o
14
14
qnoc-qdu1000-objs := qdu1000.o
15
15
icc-rpmh-obj := icc-rpmh.o
16
+
qnoc-sa8775p-objs := sa8775p.o
16
17
qnoc-sc7180-objs := sc7180.o
17
18
qnoc-sc7280-objs := sc7280.o
18
19
qnoc-sc8180x-objs := sc8180x.o
19
20
qnoc-sc8280xp-objs := sc8280xp.o
20
21
qnoc-sdm660-objs := sdm660.o
22
+
qnoc-sdm670-objs := sdm670.o
21
23
qnoc-sdm845-objs := sdm845.o
22
24
qnoc-sdx55-objs := sdx55.o
23
25
qnoc-sdx65-objs := sdx65.o
···
41
39
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
42
40
obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o
43
41
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
42
+
obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o
44
43
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
45
44
obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
46
45
obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
47
46
obj-$(CONFIG_INTERCONNECT_QCOM_SC8280XP) += qnoc-sc8280xp.o
48
47
obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
48
+
obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o
49
49
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
50
50
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
51
51
obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
+2541
drivers/interconnect/qcom/sa8775p.c
+2541
drivers/interconnect/qcom/sa8775p.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#include <linux/device.h>
8
+
#include <linux/interconnect.h>
9
+
#include <linux/interconnect-provider.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of_platform.h>
12
+
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
13
+
14
+
#include "bcm-voter.h"
15
+
#include "icc-rpmh.h"
16
+
17
+
#define SA8775P_MASTER_GPU_TCU 0
18
+
#define SA8775P_MASTER_PCIE_TCU 1
19
+
#define SA8775P_MASTER_SYS_TCU 2
20
+
#define SA8775P_MASTER_APPSS_PROC 3
21
+
#define SA8775P_MASTER_LLCC 4
22
+
#define SA8775P_MASTER_CNOC_LPASS_AG_NOC 5
23
+
#define SA8775P_MASTER_GIC_AHB 6
24
+
#define SA8775P_MASTER_CDSP_NOC_CFG 7
25
+
#define SA8775P_MASTER_CDSPB_NOC_CFG 8
26
+
#define SA8775P_MASTER_QDSS_BAM 9
27
+
#define SA8775P_MASTER_QUP_0 10
28
+
#define SA8775P_MASTER_QUP_1 11
29
+
#define SA8775P_MASTER_QUP_2 12
30
+
#define SA8775P_MASTER_A1NOC_SNOC 13
31
+
#define SA8775P_MASTER_A2NOC_SNOC 14
32
+
#define SA8775P_MASTER_CAMNOC_HF 15
33
+
#define SA8775P_MASTER_CAMNOC_ICP 16
34
+
#define SA8775P_MASTER_CAMNOC_SF 17
35
+
#define SA8775P_MASTER_COMPUTE_NOC 18
36
+
#define SA8775P_MASTER_COMPUTE_NOC_1 19
37
+
#define SA8775P_MASTER_CNOC_A2NOC 20
38
+
#define SA8775P_MASTER_CNOC_DC_NOC 21
39
+
#define SA8775P_MASTER_GEM_NOC_CFG 22
40
+
#define SA8775P_MASTER_GEM_NOC_CNOC 23
41
+
#define SA8775P_MASTER_GEM_NOC_PCIE_SNOC 24
42
+
#define SA8775P_MASTER_GPDSP_SAIL 25
43
+
#define SA8775P_MASTER_GFX3D 26
44
+
#define SA8775P_MASTER_LPASS_ANOC 27
45
+
#define SA8775P_MASTER_MDP0 28
46
+
#define SA8775P_MASTER_MDP1 29
47
+
#define SA8775P_MASTER_MDP_CORE1_0 30
48
+
#define SA8775P_MASTER_MDP_CORE1_1 31
49
+
#define SA8775P_MASTER_MNOC_HF_MEM_NOC 32
50
+
#define SA8775P_MASTER_CNOC_MNOC_HF_CFG 33
51
+
#define SA8775P_MASTER_MNOC_SF_MEM_NOC 34
52
+
#define SA8775P_MASTER_CNOC_MNOC_SF_CFG 35
53
+
#define SA8775P_MASTER_ANOC_PCIE_GEM_NOC 36
54
+
#define SA8775P_MASTER_SNOC_CFG 37
55
+
#define SA8775P_MASTER_SNOC_GC_MEM_NOC 38
56
+
#define SA8775P_MASTER_SNOC_SF_MEM_NOC 39
57
+
#define SA8775P_MASTER_VIDEO_P0 40
58
+
#define SA8775P_MASTER_VIDEO_P1 41
59
+
#define SA8775P_MASTER_VIDEO_PROC 42
60
+
#define SA8775P_MASTER_VIDEO_V_PROC 43
61
+
#define SA8775P_MASTER_QUP_CORE_0 44
62
+
#define SA8775P_MASTER_QUP_CORE_1 45
63
+
#define SA8775P_MASTER_QUP_CORE_2 46
64
+
#define SA8775P_MASTER_QUP_CORE_3 47
65
+
#define SA8775P_MASTER_CRYPTO_CORE0 48
66
+
#define SA8775P_MASTER_CRYPTO_CORE1 49
67
+
#define SA8775P_MASTER_DSP0 50
68
+
#define SA8775P_MASTER_DSP1 51
69
+
#define SA8775P_MASTER_IPA 52
70
+
#define SA8775P_MASTER_LPASS_PROC 53
71
+
#define SA8775P_MASTER_CDSP_PROC 54
72
+
#define SA8775P_MASTER_CDSP_PROC_B 55
73
+
#define SA8775P_MASTER_PIMEM 56
74
+
#define SA8775P_MASTER_QUP_3 57
75
+
#define SA8775P_MASTER_EMAC 58
76
+
#define SA8775P_MASTER_EMAC_1 59
77
+
#define SA8775P_MASTER_GIC 60
78
+
#define SA8775P_MASTER_PCIE_0 61
79
+
#define SA8775P_MASTER_PCIE_1 62
80
+
#define SA8775P_MASTER_QDSS_ETR_0 63
81
+
#define SA8775P_MASTER_QDSS_ETR_1 64
82
+
#define SA8775P_MASTER_SDC 65
83
+
#define SA8775P_MASTER_UFS_CARD 66
84
+
#define SA8775P_MASTER_UFS_MEM 67
85
+
#define SA8775P_MASTER_USB2 68
86
+
#define SA8775P_MASTER_USB3_0 69
87
+
#define SA8775P_MASTER_USB3_1 70
88
+
#define SA8775P_SLAVE_EBI1 512
89
+
#define SA8775P_SLAVE_AHB2PHY_0 513
90
+
#define SA8775P_SLAVE_AHB2PHY_1 514
91
+
#define SA8775P_SLAVE_AHB2PHY_2 515
92
+
#define SA8775P_SLAVE_AHB2PHY_3 516
93
+
#define SA8775P_SLAVE_ANOC_THROTTLE_CFG 517
94
+
#define SA8775P_SLAVE_AOSS 518
95
+
#define SA8775P_SLAVE_APPSS 519
96
+
#define SA8775P_SLAVE_BOOT_ROM 520
97
+
#define SA8775P_SLAVE_CAMERA_CFG 521
98
+
#define SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG 522
99
+
#define SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG 523
100
+
#define SA8775P_SLAVE_CLK_CTL 524
101
+
#define SA8775P_SLAVE_CDSP_CFG 525
102
+
#define SA8775P_SLAVE_CDSP1_CFG 526
103
+
#define SA8775P_SLAVE_RBCPR_CX_CFG 527
104
+
#define SA8775P_SLAVE_RBCPR_MMCX_CFG 528
105
+
#define SA8775P_SLAVE_RBCPR_MX_CFG 529
106
+
#define SA8775P_SLAVE_CPR_NSPCX 530
107
+
#define SA8775P_SLAVE_CRYPTO_0_CFG 531
108
+
#define SA8775P_SLAVE_CX_RDPM 532
109
+
#define SA8775P_SLAVE_DISPLAY_CFG 533
110
+
#define SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG 534
111
+
#define SA8775P_SLAVE_DISPLAY1_CFG 535
112
+
#define SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536
113
+
#define SA8775P_SLAVE_EMAC_CFG 537
114
+
#define SA8775P_SLAVE_EMAC1_CFG 538
115
+
#define SA8775P_SLAVE_GP_DSP0_CFG 539
116
+
#define SA8775P_SLAVE_GP_DSP1_CFG 540
117
+
#define SA8775P_SLAVE_GPDSP0_THROTTLE_CFG 541
118
+
#define SA8775P_SLAVE_GPDSP1_THROTTLE_CFG 542
119
+
#define SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG 543
120
+
#define SA8775P_SLAVE_GFX3D_CFG 544
121
+
#define SA8775P_SLAVE_HWKM 545
122
+
#define SA8775P_SLAVE_IMEM_CFG 546
123
+
#define SA8775P_SLAVE_IPA_CFG 547
124
+
#define SA8775P_SLAVE_IPC_ROUTER_CFG 548
125
+
#define SA8775P_SLAVE_LLCC_CFG 549
126
+
#define SA8775P_SLAVE_LPASS 550
127
+
#define SA8775P_SLAVE_LPASS_CORE_CFG 551
128
+
#define SA8775P_SLAVE_LPASS_LPI_CFG 552
129
+
#define SA8775P_SLAVE_LPASS_MPU_CFG 553
130
+
#define SA8775P_SLAVE_LPASS_THROTTLE_CFG 554
131
+
#define SA8775P_SLAVE_LPASS_TOP_CFG 555
132
+
#define SA8775P_SLAVE_MX_RDPM 556
133
+
#define SA8775P_SLAVE_MXC_RDPM 557
134
+
#define SA8775P_SLAVE_PCIE_0_CFG 558
135
+
#define SA8775P_SLAVE_PCIE_1_CFG 559
136
+
#define SA8775P_SLAVE_PCIE_RSC_CFG 560
137
+
#define SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG 561
138
+
#define SA8775P_SLAVE_PCIE_THROTTLE_CFG 562
139
+
#define SA8775P_SLAVE_PDM 563
140
+
#define SA8775P_SLAVE_PIMEM_CFG 564
141
+
#define SA8775P_SLAVE_PKA_WRAPPER_CFG 565
142
+
#define SA8775P_SLAVE_QDSS_CFG 566
143
+
#define SA8775P_SLAVE_QM_CFG 567
144
+
#define SA8775P_SLAVE_QM_MPU_CFG 568
145
+
#define SA8775P_SLAVE_QUP_0 569
146
+
#define SA8775P_SLAVE_QUP_1 570
147
+
#define SA8775P_SLAVE_QUP_2 571
148
+
#define SA8775P_SLAVE_QUP_3 572
149
+
#define SA8775P_SLAVE_SAIL_THROTTLE_CFG 573
150
+
#define SA8775P_SLAVE_SDC1 574
151
+
#define SA8775P_SLAVE_SECURITY 575
152
+
#define SA8775P_SLAVE_SNOC_THROTTLE_CFG 576
153
+
#define SA8775P_SLAVE_TCSR 577
154
+
#define SA8775P_SLAVE_TLMM 578
155
+
#define SA8775P_SLAVE_TSC_CFG 579
156
+
#define SA8775P_SLAVE_UFS_CARD_CFG 580
157
+
#define SA8775P_SLAVE_UFS_MEM_CFG 581
158
+
#define SA8775P_SLAVE_USB2 582
159
+
#define SA8775P_SLAVE_USB3_0 583
160
+
#define SA8775P_SLAVE_USB3_1 584
161
+
#define SA8775P_SLAVE_VENUS_CFG 585
162
+
#define SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG 586
163
+
#define SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587
164
+
#define SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588
165
+
#define SA8775P_SLAVE_A1NOC_SNOC 589
166
+
#define SA8775P_SLAVE_A2NOC_SNOC 590
167
+
#define SA8775P_SLAVE_DDRSS_CFG 591
168
+
#define SA8775P_SLAVE_GEM_NOC_CNOC 592
169
+
#define SA8775P_SLAVE_GEM_NOC_CFG 593
170
+
#define SA8775P_SLAVE_SNOC_GEM_NOC_GC 594
171
+
#define SA8775P_SLAVE_SNOC_GEM_NOC_SF 595
172
+
#define SA8775P_SLAVE_GP_DSP_SAIL_NOC 596
173
+
#define SA8775P_SLAVE_GPDSP_NOC_CFG 597
174
+
#define SA8775P_SLAVE_HCP_A 598
175
+
#define SA8775P_SLAVE_LLCC 599
176
+
#define SA8775P_SLAVE_MNOC_HF_MEM_NOC 600
177
+
#define SA8775P_SLAVE_MNOC_SF_MEM_NOC 601
178
+
#define SA8775P_SLAVE_CNOC_MNOC_HF_CFG 602
179
+
#define SA8775P_SLAVE_CNOC_MNOC_SF_CFG 603
180
+
#define SA8775P_SLAVE_CDSP_MEM_NOC 604
181
+
#define SA8775P_SLAVE_CDSPB_MEM_NOC 605
182
+
#define SA8775P_SLAVE_HCP_B 606
183
+
#define SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 607
184
+
#define SA8775P_SLAVE_PCIE_ANOC_CFG 608
185
+
#define SA8775P_SLAVE_ANOC_PCIE_GEM_NOC 609
186
+
#define SA8775P_SLAVE_SNOC_CFG 610
187
+
#define SA8775P_SLAVE_LPASS_SNOC 611
188
+
#define SA8775P_SLAVE_QUP_CORE_0 612
189
+
#define SA8775P_SLAVE_QUP_CORE_1 613
190
+
#define SA8775P_SLAVE_QUP_CORE_2 614
191
+
#define SA8775P_SLAVE_QUP_CORE_3 615
192
+
#define SA8775P_SLAVE_BOOT_IMEM 616
193
+
#define SA8775P_SLAVE_IMEM 617
194
+
#define SA8775P_SLAVE_PIMEM 618
195
+
#define SA8775P_SLAVE_SERVICE_NSP_NOC 619
196
+
#define SA8775P_SLAVE_SERVICE_NSPB_NOC 620
197
+
#define SA8775P_SLAVE_SERVICE_GEM_NOC_1 621
198
+
#define SA8775P_SLAVE_SERVICE_MNOC_HF 622
199
+
#define SA8775P_SLAVE_SERVICE_MNOC_SF 623
200
+
#define SA8775P_SLAVE_SERVICES_LPASS_AML_NOC 624
201
+
#define SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 625
202
+
#define SA8775P_SLAVE_SERVICE_GEM_NOC_2 626
203
+
#define SA8775P_SLAVE_SERVICE_SNOC 627
204
+
#define SA8775P_SLAVE_SERVICE_GEM_NOC 628
205
+
#define SA8775P_SLAVE_SERVICE_GEM_NOC2 629
206
+
#define SA8775P_SLAVE_PCIE_0 630
207
+
#define SA8775P_SLAVE_PCIE_1 631
208
+
#define SA8775P_SLAVE_QDSS_STM 632
209
+
#define SA8775P_SLAVE_TCU 633
210
+
211
+
static struct qcom_icc_node qxm_qup3 = {
212
+
.name = "qxm_qup3",
213
+
.id = SA8775P_MASTER_QUP_3,
214
+
.channels = 1,
215
+
.buswidth = 8,
216
+
.num_links = 1,
217
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
218
+
};
219
+
220
+
static struct qcom_icc_node xm_emac_0 = {
221
+
.name = "xm_emac_0",
222
+
.id = SA8775P_MASTER_EMAC,
223
+
.channels = 1,
224
+
.buswidth = 8,
225
+
.num_links = 1,
226
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
227
+
};
228
+
229
+
static struct qcom_icc_node xm_emac_1 = {
230
+
.name = "xm_emac_1",
231
+
.id = SA8775P_MASTER_EMAC_1,
232
+
.channels = 1,
233
+
.buswidth = 8,
234
+
.num_links = 1,
235
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
236
+
};
237
+
238
+
static struct qcom_icc_node xm_sdc1 = {
239
+
.name = "xm_sdc1",
240
+
.id = SA8775P_MASTER_SDC,
241
+
.channels = 1,
242
+
.buswidth = 8,
243
+
.num_links = 1,
244
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
245
+
};
246
+
247
+
static struct qcom_icc_node xm_ufs_mem = {
248
+
.name = "xm_ufs_mem",
249
+
.id = SA8775P_MASTER_UFS_MEM,
250
+
.channels = 1,
251
+
.buswidth = 8,
252
+
.num_links = 1,
253
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
254
+
};
255
+
256
+
static struct qcom_icc_node xm_usb2_2 = {
257
+
.name = "xm_usb2_2",
258
+
.id = SA8775P_MASTER_USB2,
259
+
.channels = 1,
260
+
.buswidth = 8,
261
+
.num_links = 1,
262
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
263
+
};
264
+
265
+
static struct qcom_icc_node xm_usb3_0 = {
266
+
.name = "xm_usb3_0",
267
+
.id = SA8775P_MASTER_USB3_0,
268
+
.channels = 1,
269
+
.buswidth = 8,
270
+
.num_links = 1,
271
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
272
+
};
273
+
274
+
static struct qcom_icc_node xm_usb3_1 = {
275
+
.name = "xm_usb3_1",
276
+
.id = SA8775P_MASTER_USB3_1,
277
+
.channels = 1,
278
+
.buswidth = 8,
279
+
.num_links = 1,
280
+
.links = { SA8775P_SLAVE_A1NOC_SNOC },
281
+
};
282
+
283
+
static struct qcom_icc_node qhm_qdss_bam = {
284
+
.name = "qhm_qdss_bam",
285
+
.id = SA8775P_MASTER_QDSS_BAM,
286
+
.channels = 1,
287
+
.buswidth = 4,
288
+
.num_links = 1,
289
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
290
+
};
291
+
292
+
static struct qcom_icc_node qhm_qup0 = {
293
+
.name = "qhm_qup0",
294
+
.id = SA8775P_MASTER_QUP_0,
295
+
.channels = 1,
296
+
.buswidth = 4,
297
+
.num_links = 1,
298
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
299
+
};
300
+
301
+
static struct qcom_icc_node qhm_qup1 = {
302
+
.name = "qhm_qup1",
303
+
.id = SA8775P_MASTER_QUP_1,
304
+
.channels = 1,
305
+
.buswidth = 4,
306
+
.num_links = 1,
307
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
308
+
};
309
+
310
+
static struct qcom_icc_node qhm_qup2 = {
311
+
.name = "qhm_qup2",
312
+
.id = SA8775P_MASTER_QUP_2,
313
+
.channels = 1,
314
+
.buswidth = 4,
315
+
.num_links = 1,
316
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
317
+
};
318
+
319
+
static struct qcom_icc_node qnm_cnoc_datapath = {
320
+
.name = "qnm_cnoc_datapath",
321
+
.id = SA8775P_MASTER_CNOC_A2NOC,
322
+
.channels = 1,
323
+
.buswidth = 8,
324
+
.num_links = 1,
325
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
326
+
};
327
+
328
+
static struct qcom_icc_node qxm_crypto_0 = {
329
+
.name = "qxm_crypto_0",
330
+
.id = SA8775P_MASTER_CRYPTO_CORE0,
331
+
.channels = 1,
332
+
.buswidth = 8,
333
+
.num_links = 1,
334
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
335
+
};
336
+
337
+
static struct qcom_icc_node qxm_crypto_1 = {
338
+
.name = "qxm_crypto_1",
339
+
.id = SA8775P_MASTER_CRYPTO_CORE1,
340
+
.channels = 1,
341
+
.buswidth = 8,
342
+
.num_links = 1,
343
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
344
+
};
345
+
346
+
static struct qcom_icc_node qxm_ipa = {
347
+
.name = "qxm_ipa",
348
+
.id = SA8775P_MASTER_IPA,
349
+
.channels = 1,
350
+
.buswidth = 8,
351
+
.num_links = 1,
352
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
353
+
};
354
+
355
+
static struct qcom_icc_node xm_qdss_etr_0 = {
356
+
.name = "xm_qdss_etr_0",
357
+
.id = SA8775P_MASTER_QDSS_ETR_0,
358
+
.channels = 1,
359
+
.buswidth = 8,
360
+
.num_links = 1,
361
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
362
+
};
363
+
364
+
static struct qcom_icc_node xm_qdss_etr_1 = {
365
+
.name = "xm_qdss_etr_1",
366
+
.id = SA8775P_MASTER_QDSS_ETR_1,
367
+
.channels = 1,
368
+
.buswidth = 8,
369
+
.num_links = 1,
370
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
371
+
};
372
+
373
+
static struct qcom_icc_node xm_ufs_card = {
374
+
.name = "xm_ufs_card",
375
+
.id = SA8775P_MASTER_UFS_CARD,
376
+
.channels = 1,
377
+
.buswidth = 8,
378
+
.num_links = 1,
379
+
.links = { SA8775P_SLAVE_A2NOC_SNOC },
380
+
};
381
+
382
+
static struct qcom_icc_node qup0_core_master = {
383
+
.name = "qup0_core_master",
384
+
.id = SA8775P_MASTER_QUP_CORE_0,
385
+
.channels = 1,
386
+
.buswidth = 4,
387
+
.num_links = 1,
388
+
.links = { SA8775P_SLAVE_QUP_CORE_0 },
389
+
};
390
+
391
+
static struct qcom_icc_node qup1_core_master = {
392
+
.name = "qup1_core_master",
393
+
.id = SA8775P_MASTER_QUP_CORE_1,
394
+
.channels = 1,
395
+
.buswidth = 4,
396
+
.num_links = 1,
397
+
.links = { SA8775P_SLAVE_QUP_CORE_1 },
398
+
};
399
+
400
+
static struct qcom_icc_node qup2_core_master = {
401
+
.name = "qup2_core_master",
402
+
.id = SA8775P_MASTER_QUP_CORE_2,
403
+
.channels = 1,
404
+
.buswidth = 4,
405
+
.num_links = 1,
406
+
.links = { SA8775P_SLAVE_QUP_CORE_2 },
407
+
};
408
+
409
+
static struct qcom_icc_node qup3_core_master = {
410
+
.name = "qup3_core_master",
411
+
.id = SA8775P_MASTER_QUP_CORE_3,
412
+
.channels = 1,
413
+
.buswidth = 4,
414
+
.num_links = 1,
415
+
.links = { SA8775P_SLAVE_QUP_CORE_3 },
416
+
};
417
+
418
+
static struct qcom_icc_node qnm_gemnoc_cnoc = {
419
+
.name = "qnm_gemnoc_cnoc",
420
+
.id = SA8775P_MASTER_GEM_NOC_CNOC,
421
+
.channels = 1,
422
+
.buswidth = 16,
423
+
.num_links = 82,
424
+
.links = { SA8775P_SLAVE_AHB2PHY_0,
425
+
SA8775P_SLAVE_AHB2PHY_1,
426
+
SA8775P_SLAVE_AHB2PHY_2,
427
+
SA8775P_SLAVE_AHB2PHY_3,
428
+
SA8775P_SLAVE_ANOC_THROTTLE_CFG,
429
+
SA8775P_SLAVE_AOSS,
430
+
SA8775P_SLAVE_APPSS,
431
+
SA8775P_SLAVE_BOOT_ROM,
432
+
SA8775P_SLAVE_CAMERA_CFG,
433
+
SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG,
434
+
SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG,
435
+
SA8775P_SLAVE_CLK_CTL,
436
+
SA8775P_SLAVE_CDSP_CFG,
437
+
SA8775P_SLAVE_CDSP1_CFG,
438
+
SA8775P_SLAVE_RBCPR_CX_CFG,
439
+
SA8775P_SLAVE_RBCPR_MMCX_CFG,
440
+
SA8775P_SLAVE_RBCPR_MX_CFG,
441
+
SA8775P_SLAVE_CPR_NSPCX,
442
+
SA8775P_SLAVE_CRYPTO_0_CFG,
443
+
SA8775P_SLAVE_CX_RDPM,
444
+
SA8775P_SLAVE_DISPLAY_CFG,
445
+
SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG,
446
+
SA8775P_SLAVE_DISPLAY1_CFG,
447
+
SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
448
+
SA8775P_SLAVE_EMAC_CFG,
449
+
SA8775P_SLAVE_EMAC1_CFG,
450
+
SA8775P_SLAVE_GP_DSP0_CFG,
451
+
SA8775P_SLAVE_GP_DSP1_CFG,
452
+
SA8775P_SLAVE_GPDSP0_THROTTLE_CFG,
453
+
SA8775P_SLAVE_GPDSP1_THROTTLE_CFG,
454
+
SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG,
455
+
SA8775P_SLAVE_GFX3D_CFG,
456
+
SA8775P_SLAVE_HWKM,
457
+
SA8775P_SLAVE_IMEM_CFG,
458
+
SA8775P_SLAVE_IPA_CFG,
459
+
SA8775P_SLAVE_IPC_ROUTER_CFG,
460
+
SA8775P_SLAVE_LPASS,
461
+
SA8775P_SLAVE_LPASS_THROTTLE_CFG,
462
+
SA8775P_SLAVE_MX_RDPM,
463
+
SA8775P_SLAVE_MXC_RDPM,
464
+
SA8775P_SLAVE_PCIE_0_CFG,
465
+
SA8775P_SLAVE_PCIE_1_CFG,
466
+
SA8775P_SLAVE_PCIE_RSC_CFG,
467
+
SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG,
468
+
SA8775P_SLAVE_PCIE_THROTTLE_CFG,
469
+
SA8775P_SLAVE_PDM,
470
+
SA8775P_SLAVE_PIMEM_CFG,
471
+
SA8775P_SLAVE_PKA_WRAPPER_CFG,
472
+
SA8775P_SLAVE_QDSS_CFG,
473
+
SA8775P_SLAVE_QM_CFG,
474
+
SA8775P_SLAVE_QM_MPU_CFG,
475
+
SA8775P_SLAVE_QUP_0,
476
+
SA8775P_SLAVE_QUP_1,
477
+
SA8775P_SLAVE_QUP_2,
478
+
SA8775P_SLAVE_QUP_3,
479
+
SA8775P_SLAVE_SAIL_THROTTLE_CFG,
480
+
SA8775P_SLAVE_SDC1,
481
+
SA8775P_SLAVE_SECURITY,
482
+
SA8775P_SLAVE_SNOC_THROTTLE_CFG,
483
+
SA8775P_SLAVE_TCSR,
484
+
SA8775P_SLAVE_TLMM,
485
+
SA8775P_SLAVE_TSC_CFG,
486
+
SA8775P_SLAVE_UFS_CARD_CFG,
487
+
SA8775P_SLAVE_UFS_MEM_CFG,
488
+
SA8775P_SLAVE_USB2,
489
+
SA8775P_SLAVE_USB3_0,
490
+
SA8775P_SLAVE_USB3_1,
491
+
SA8775P_SLAVE_VENUS_CFG,
492
+
SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG,
493
+
SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
494
+
SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
495
+
SA8775P_SLAVE_DDRSS_CFG,
496
+
SA8775P_SLAVE_GPDSP_NOC_CFG,
497
+
SA8775P_SLAVE_CNOC_MNOC_HF_CFG,
498
+
SA8775P_SLAVE_CNOC_MNOC_SF_CFG,
499
+
SA8775P_SLAVE_PCIE_ANOC_CFG,
500
+
SA8775P_SLAVE_SNOC_CFG,
501
+
SA8775P_SLAVE_BOOT_IMEM,
502
+
SA8775P_SLAVE_IMEM,
503
+
SA8775P_SLAVE_PIMEM,
504
+
SA8775P_SLAVE_QDSS_STM,
505
+
SA8775P_SLAVE_TCU
506
+
},
507
+
};
508
+
509
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
510
+
.name = "qnm_gemnoc_pcie",
511
+
.id = SA8775P_MASTER_GEM_NOC_PCIE_SNOC,
512
+
.channels = 1,
513
+
.buswidth = 16,
514
+
.num_links = 2,
515
+
.links = { SA8775P_SLAVE_PCIE_0,
516
+
SA8775P_SLAVE_PCIE_1
517
+
},
518
+
};
519
+
520
+
static struct qcom_icc_node qnm_cnoc_dc_noc = {
521
+
.name = "qnm_cnoc_dc_noc",
522
+
.id = SA8775P_MASTER_CNOC_DC_NOC,
523
+
.channels = 1,
524
+
.buswidth = 4,
525
+
.num_links = 2,
526
+
.links = { SA8775P_SLAVE_LLCC_CFG,
527
+
SA8775P_SLAVE_GEM_NOC_CFG
528
+
},
529
+
};
530
+
531
+
static struct qcom_icc_node alm_gpu_tcu = {
532
+
.name = "alm_gpu_tcu",
533
+
.id = SA8775P_MASTER_GPU_TCU,
534
+
.channels = 1,
535
+
.buswidth = 8,
536
+
.num_links = 2,
537
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
538
+
SA8775P_SLAVE_LLCC
539
+
},
540
+
};
541
+
542
+
static struct qcom_icc_node alm_pcie_tcu = {
543
+
.name = "alm_pcie_tcu",
544
+
.id = SA8775P_MASTER_PCIE_TCU,
545
+
.channels = 1,
546
+
.buswidth = 8,
547
+
.num_links = 2,
548
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
549
+
SA8775P_SLAVE_LLCC
550
+
},
551
+
};
552
+
553
+
static struct qcom_icc_node alm_sys_tcu = {
554
+
.name = "alm_sys_tcu",
555
+
.id = SA8775P_MASTER_SYS_TCU,
556
+
.channels = 1,
557
+
.buswidth = 8,
558
+
.num_links = 2,
559
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
560
+
SA8775P_SLAVE_LLCC
561
+
},
562
+
};
563
+
564
+
static struct qcom_icc_node chm_apps = {
565
+
.name = "chm_apps",
566
+
.id = SA8775P_MASTER_APPSS_PROC,
567
+
.channels = 4,
568
+
.buswidth = 32,
569
+
.num_links = 3,
570
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
571
+
SA8775P_SLAVE_LLCC,
572
+
SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
573
+
},
574
+
};
575
+
576
+
static struct qcom_icc_node qnm_cmpnoc0 = {
577
+
.name = "qnm_cmpnoc0",
578
+
.id = SA8775P_MASTER_COMPUTE_NOC,
579
+
.channels = 2,
580
+
.buswidth = 32,
581
+
.num_links = 2,
582
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
583
+
SA8775P_SLAVE_LLCC
584
+
},
585
+
};
586
+
587
+
static struct qcom_icc_node qnm_cmpnoc1 = {
588
+
.name = "qnm_cmpnoc1",
589
+
.id = SA8775P_MASTER_COMPUTE_NOC_1,
590
+
.channels = 2,
591
+
.buswidth = 32,
592
+
.num_links = 2,
593
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
594
+
SA8775P_SLAVE_LLCC
595
+
},
596
+
};
597
+
598
+
static struct qcom_icc_node qnm_gemnoc_cfg = {
599
+
.name = "qnm_gemnoc_cfg",
600
+
.id = SA8775P_MASTER_GEM_NOC_CFG,
601
+
.channels = 1,
602
+
.buswidth = 4,
603
+
.num_links = 4,
604
+
.links = { SA8775P_SLAVE_SERVICE_GEM_NOC_1,
605
+
SA8775P_SLAVE_SERVICE_GEM_NOC_2,
606
+
SA8775P_SLAVE_SERVICE_GEM_NOC,
607
+
SA8775P_SLAVE_SERVICE_GEM_NOC2
608
+
},
609
+
};
610
+
611
+
static struct qcom_icc_node qnm_gpdsp_sail = {
612
+
.name = "qnm_gpdsp_sail",
613
+
.id = SA8775P_MASTER_GPDSP_SAIL,
614
+
.channels = 1,
615
+
.buswidth = 16,
616
+
.num_links = 2,
617
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
618
+
SA8775P_SLAVE_LLCC
619
+
},
620
+
};
621
+
622
+
static struct qcom_icc_node qnm_gpu = {
623
+
.name = "qnm_gpu",
624
+
.id = SA8775P_MASTER_GFX3D,
625
+
.channels = 2,
626
+
.buswidth = 32,
627
+
.num_links = 2,
628
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
629
+
SA8775P_SLAVE_LLCC
630
+
},
631
+
};
632
+
633
+
static struct qcom_icc_node qnm_mnoc_hf = {
634
+
.name = "qnm_mnoc_hf",
635
+
.id = SA8775P_MASTER_MNOC_HF_MEM_NOC,
636
+
.channels = 2,
637
+
.buswidth = 32,
638
+
.num_links = 2,
639
+
.links = { SA8775P_SLAVE_LLCC,
640
+
SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
641
+
},
642
+
};
643
+
644
+
static struct qcom_icc_node qnm_mnoc_sf = {
645
+
.name = "qnm_mnoc_sf",
646
+
.id = SA8775P_MASTER_MNOC_SF_MEM_NOC,
647
+
.channels = 2,
648
+
.buswidth = 32,
649
+
.num_links = 3,
650
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
651
+
SA8775P_SLAVE_LLCC,
652
+
SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
653
+
},
654
+
};
655
+
656
+
static struct qcom_icc_node qnm_pcie = {
657
+
.name = "qnm_pcie",
658
+
.id = SA8775P_MASTER_ANOC_PCIE_GEM_NOC,
659
+
.channels = 1,
660
+
.buswidth = 32,
661
+
.num_links = 2,
662
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
663
+
SA8775P_SLAVE_LLCC
664
+
},
665
+
};
666
+
667
+
static struct qcom_icc_node qnm_snoc_gc = {
668
+
.name = "qnm_snoc_gc",
669
+
.id = SA8775P_MASTER_SNOC_GC_MEM_NOC,
670
+
.channels = 1,
671
+
.buswidth = 8,
672
+
.num_links = 1,
673
+
.links = { SA8775P_SLAVE_LLCC },
674
+
};
675
+
676
+
static struct qcom_icc_node qnm_snoc_sf = {
677
+
.name = "qnm_snoc_sf",
678
+
.id = SA8775P_MASTER_SNOC_SF_MEM_NOC,
679
+
.channels = 1,
680
+
.buswidth = 16,
681
+
.num_links = 3,
682
+
.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
683
+
SA8775P_SLAVE_LLCC,
684
+
SA8775P_SLAVE_GEM_NOC_PCIE_CNOC },
685
+
};
686
+
687
+
static struct qcom_icc_node qxm_dsp0 = {
688
+
.name = "qxm_dsp0",
689
+
.id = SA8775P_MASTER_DSP0,
690
+
.channels = 1,
691
+
.buswidth = 16,
692
+
.num_links = 1,
693
+
.links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC },
694
+
};
695
+
696
+
static struct qcom_icc_node qxm_dsp1 = {
697
+
.name = "qxm_dsp1",
698
+
.id = SA8775P_MASTER_DSP1,
699
+
.channels = 1,
700
+
.buswidth = 16,
701
+
.num_links = 1,
702
+
.links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC },
703
+
};
704
+
705
+
static struct qcom_icc_node qhm_config_noc = {
706
+
.name = "qhm_config_noc",
707
+
.id = SA8775P_MASTER_CNOC_LPASS_AG_NOC,
708
+
.channels = 1,
709
+
.buswidth = 4,
710
+
.num_links = 6,
711
+
.links = { SA8775P_SLAVE_LPASS_CORE_CFG,
712
+
SA8775P_SLAVE_LPASS_LPI_CFG,
713
+
SA8775P_SLAVE_LPASS_MPU_CFG,
714
+
SA8775P_SLAVE_LPASS_TOP_CFG,
715
+
SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
716
+
SA8775P_SLAVE_SERVICE_LPASS_AG_NOC
717
+
},
718
+
};
719
+
720
+
static struct qcom_icc_node qxm_lpass_dsp = {
721
+
.name = "qxm_lpass_dsp",
722
+
.id = SA8775P_MASTER_LPASS_PROC,
723
+
.channels = 1,
724
+
.buswidth = 8,
725
+
.num_links = 4,
726
+
.links = { SA8775P_SLAVE_LPASS_TOP_CFG,
727
+
SA8775P_SLAVE_LPASS_SNOC,
728
+
SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
729
+
SA8775P_SLAVE_SERVICE_LPASS_AG_NOC
730
+
},
731
+
};
732
+
733
+
static struct qcom_icc_node llcc_mc = {
734
+
.name = "llcc_mc",
735
+
.id = SA8775P_MASTER_LLCC,
736
+
.channels = 8,
737
+
.buswidth = 4,
738
+
.num_links = 1,
739
+
.links = { SA8775P_SLAVE_EBI1 },
740
+
};
741
+
742
+
static struct qcom_icc_node qnm_camnoc_hf = {
743
+
.name = "qnm_camnoc_hf",
744
+
.id = SA8775P_MASTER_CAMNOC_HF,
745
+
.channels = 1,
746
+
.buswidth = 32,
747
+
.num_links = 1,
748
+
.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
749
+
};
750
+
751
+
static struct qcom_icc_node qnm_camnoc_icp = {
752
+
.name = "qnm_camnoc_icp",
753
+
.id = SA8775P_MASTER_CAMNOC_ICP,
754
+
.channels = 1,
755
+
.buswidth = 8,
756
+
.num_links = 1,
757
+
.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
758
+
};
759
+
760
+
static struct qcom_icc_node qnm_camnoc_sf = {
761
+
.name = "qnm_camnoc_sf",
762
+
.id = SA8775P_MASTER_CAMNOC_SF,
763
+
.channels = 1,
764
+
.buswidth = 32,
765
+
.num_links = 1,
766
+
.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
767
+
};
768
+
769
+
static struct qcom_icc_node qnm_mdp0_0 = {
770
+
.name = "qnm_mdp0_0",
771
+
.id = SA8775P_MASTER_MDP0,
772
+
.channels = 1,
773
+
.buswidth = 32,
774
+
.num_links = 1,
775
+
.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
776
+
};
777
+
778
+
static struct qcom_icc_node qnm_mdp0_1 = {
779
+
.name = "qnm_mdp0_1",
780
+
.id = SA8775P_MASTER_MDP1,
781
+
.channels = 1,
782
+
.buswidth = 32,
783
+
.num_links = 1,
784
+
.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
785
+
};
786
+
787
+
static struct qcom_icc_node qnm_mdp1_0 = {
788
+
.name = "qnm_mdp1_0",
789
+
.id = SA8775P_MASTER_MDP_CORE1_0,
790
+
.channels = 1,
791
+
.buswidth = 32,
792
+
.num_links = 1,
793
+
.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
794
+
};
795
+
796
+
static struct qcom_icc_node qnm_mdp1_1 = {
797
+
.name = "qnm_mdp1_1",
798
+
.id = SA8775P_MASTER_MDP_CORE1_1,
799
+
.channels = 1,
800
+
.buswidth = 32,
801
+
.num_links = 1,
802
+
.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
803
+
};
804
+
805
+
static struct qcom_icc_node qnm_mnoc_hf_cfg = {
806
+
.name = "qnm_mnoc_hf_cfg",
807
+
.id = SA8775P_MASTER_CNOC_MNOC_HF_CFG,
808
+
.channels = 1,
809
+
.buswidth = 4,
810
+
.num_links = 1,
811
+
.links = { SA8775P_SLAVE_SERVICE_MNOC_HF },
812
+
};
813
+
814
+
static struct qcom_icc_node qnm_mnoc_sf_cfg = {
815
+
.name = "qnm_mnoc_sf_cfg",
816
+
.id = SA8775P_MASTER_CNOC_MNOC_SF_CFG,
817
+
.channels = 1,
818
+
.buswidth = 4,
819
+
.num_links = 1,
820
+
.links = { SA8775P_SLAVE_SERVICE_MNOC_SF },
821
+
};
822
+
823
+
static struct qcom_icc_node qnm_video0 = {
824
+
.name = "qnm_video0",
825
+
.id = SA8775P_MASTER_VIDEO_P0,
826
+
.channels = 1,
827
+
.buswidth = 32,
828
+
.num_links = 1,
829
+
.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
830
+
};
831
+
832
+
static struct qcom_icc_node qnm_video1 = {
833
+
.name = "qnm_video1",
834
+
.id = SA8775P_MASTER_VIDEO_P1,
835
+
.channels = 1,
836
+
.buswidth = 32,
837
+
.num_links = 1,
838
+
.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
839
+
};
840
+
841
+
static struct qcom_icc_node qnm_video_cvp = {
842
+
.name = "qnm_video_cvp",
843
+
.id = SA8775P_MASTER_VIDEO_PROC,
844
+
.channels = 1,
845
+
.buswidth = 32,
846
+
.num_links = 1,
847
+
.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
848
+
};
849
+
850
+
static struct qcom_icc_node qnm_video_v_cpu = {
851
+
.name = "qnm_video_v_cpu",
852
+
.id = SA8775P_MASTER_VIDEO_V_PROC,
853
+
.channels = 1,
854
+
.buswidth = 8,
855
+
.num_links = 1,
856
+
.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
857
+
};
858
+
859
+
static struct qcom_icc_node qhm_nsp_noc_config = {
860
+
.name = "qhm_nsp_noc_config",
861
+
.id = SA8775P_MASTER_CDSP_NOC_CFG,
862
+
.channels = 1,
863
+
.buswidth = 4,
864
+
.num_links = 1,
865
+
.links = { SA8775P_SLAVE_SERVICE_NSP_NOC },
866
+
};
867
+
868
+
static struct qcom_icc_node qxm_nsp = {
869
+
.name = "qxm_nsp",
870
+
.id = SA8775P_MASTER_CDSP_PROC,
871
+
.channels = 2,
872
+
.buswidth = 32,
873
+
.num_links = 2,
874
+
.links = { SA8775P_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC },
875
+
};
876
+
877
+
static struct qcom_icc_node qhm_nspb_noc_config = {
878
+
.name = "qhm_nspb_noc_config",
879
+
.id = SA8775P_MASTER_CDSPB_NOC_CFG,
880
+
.channels = 1,
881
+
.buswidth = 4,
882
+
.num_links = 1,
883
+
.links = { SA8775P_SLAVE_SERVICE_NSPB_NOC },
884
+
};
885
+
886
+
static struct qcom_icc_node qxm_nspb = {
887
+
.name = "qxm_nspb",
888
+
.id = SA8775P_MASTER_CDSP_PROC_B,
889
+
.channels = 2,
890
+
.buswidth = 32,
891
+
.num_links = 2,
892
+
.links = { SA8775P_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC },
893
+
};
894
+
895
+
static struct qcom_icc_node xm_pcie3_0 = {
896
+
.name = "xm_pcie3_0",
897
+
.id = SA8775P_MASTER_PCIE_0,
898
+
.channels = 1,
899
+
.buswidth = 16,
900
+
.num_links = 1,
901
+
.links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC },
902
+
};
903
+
904
+
static struct qcom_icc_node xm_pcie3_1 = {
905
+
.name = "xm_pcie3_1",
906
+
.id = SA8775P_MASTER_PCIE_1,
907
+
.channels = 1,
908
+
.buswidth = 32,
909
+
.num_links = 1,
910
+
.links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC },
911
+
};
912
+
913
+
static struct qcom_icc_node qhm_gic = {
914
+
.name = "qhm_gic",
915
+
.id = SA8775P_MASTER_GIC_AHB,
916
+
.channels = 1,
917
+
.buswidth = 4,
918
+
.num_links = 1,
919
+
.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
920
+
};
921
+
922
+
static struct qcom_icc_node qnm_aggre1_noc = {
923
+
.name = "qnm_aggre1_noc",
924
+
.id = SA8775P_MASTER_A1NOC_SNOC,
925
+
.channels = 1,
926
+
.buswidth = 32,
927
+
.num_links = 1,
928
+
.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
929
+
};
930
+
931
+
static struct qcom_icc_node qnm_aggre2_noc = {
932
+
.name = "qnm_aggre2_noc",
933
+
.id = SA8775P_MASTER_A2NOC_SNOC,
934
+
.channels = 1,
935
+
.buswidth = 16,
936
+
.num_links = 1,
937
+
.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
938
+
};
939
+
940
+
static struct qcom_icc_node qnm_lpass_noc = {
941
+
.name = "qnm_lpass_noc",
942
+
.id = SA8775P_MASTER_LPASS_ANOC,
943
+
.channels = 1,
944
+
.buswidth = 16,
945
+
.num_links = 1,
946
+
.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
947
+
};
948
+
949
+
static struct qcom_icc_node qnm_snoc_cfg = {
950
+
.name = "qnm_snoc_cfg",
951
+
.id = SA8775P_MASTER_SNOC_CFG,
952
+
.channels = 1,
953
+
.buswidth = 4,
954
+
.num_links = 1,
955
+
.links = { SA8775P_SLAVE_SERVICE_SNOC },
956
+
};
957
+
958
+
static struct qcom_icc_node qxm_pimem = {
959
+
.name = "qxm_pimem",
960
+
.id = SA8775P_MASTER_PIMEM,
961
+
.channels = 1,
962
+
.buswidth = 8,
963
+
.num_links = 1,
964
+
.links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC },
965
+
};
966
+
967
+
static struct qcom_icc_node xm_gic = {
968
+
.name = "xm_gic",
969
+
.id = SA8775P_MASTER_GIC,
970
+
.channels = 1,
971
+
.buswidth = 8,
972
+
.num_links = 1,
973
+
.links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC },
974
+
};
975
+
976
+
static struct qcom_icc_node qns_a1noc_snoc = {
977
+
.name = "qns_a1noc_snoc",
978
+
.id = SA8775P_SLAVE_A1NOC_SNOC,
979
+
.channels = 1,
980
+
.buswidth = 32,
981
+
.num_links = 1,
982
+
.links = { SA8775P_MASTER_A1NOC_SNOC },
983
+
};
984
+
985
+
static struct qcom_icc_node qns_a2noc_snoc = {
986
+
.name = "qns_a2noc_snoc",
987
+
.id = SA8775P_SLAVE_A2NOC_SNOC,
988
+
.channels = 1,
989
+
.buswidth = 16,
990
+
.num_links = 1,
991
+
.links = { SA8775P_MASTER_A2NOC_SNOC },
992
+
};
993
+
994
+
static struct qcom_icc_node qup0_core_slave = {
995
+
.name = "qup0_core_slave",
996
+
.id = SA8775P_SLAVE_QUP_CORE_0,
997
+
.channels = 1,
998
+
.buswidth = 4,
999
+
};
1000
+
1001
+
static struct qcom_icc_node qup1_core_slave = {
1002
+
.name = "qup1_core_slave",
1003
+
.id = SA8775P_SLAVE_QUP_CORE_1,
1004
+
.channels = 1,
1005
+
.buswidth = 4,
1006
+
};
1007
+
1008
+
static struct qcom_icc_node qup2_core_slave = {
1009
+
.name = "qup2_core_slave",
1010
+
.id = SA8775P_SLAVE_QUP_CORE_2,
1011
+
.channels = 1,
1012
+
.buswidth = 4,
1013
+
};
1014
+
1015
+
static struct qcom_icc_node qup3_core_slave = {
1016
+
.name = "qup3_core_slave",
1017
+
.id = SA8775P_SLAVE_QUP_CORE_3,
1018
+
.channels = 1,
1019
+
.buswidth = 4,
1020
+
};
1021
+
1022
+
static struct qcom_icc_node qhs_ahb2phy0 = {
1023
+
.name = "qhs_ahb2phy0",
1024
+
.id = SA8775P_SLAVE_AHB2PHY_0,
1025
+
.channels = 1,
1026
+
.buswidth = 4,
1027
+
};
1028
+
1029
+
static struct qcom_icc_node qhs_ahb2phy1 = {
1030
+
.name = "qhs_ahb2phy1",
1031
+
.id = SA8775P_SLAVE_AHB2PHY_1,
1032
+
.channels = 1,
1033
+
.buswidth = 4,
1034
+
};
1035
+
1036
+
static struct qcom_icc_node qhs_ahb2phy2 = {
1037
+
.name = "qhs_ahb2phy2",
1038
+
.id = SA8775P_SLAVE_AHB2PHY_2,
1039
+
.channels = 1,
1040
+
.buswidth = 4,
1041
+
};
1042
+
1043
+
static struct qcom_icc_node qhs_ahb2phy3 = {
1044
+
.name = "qhs_ahb2phy3",
1045
+
.id = SA8775P_SLAVE_AHB2PHY_3,
1046
+
.channels = 1,
1047
+
.buswidth = 4,
1048
+
};
1049
+
1050
+
static struct qcom_icc_node qhs_anoc_throttle_cfg = {
1051
+
.name = "qhs_anoc_throttle_cfg",
1052
+
.id = SA8775P_SLAVE_ANOC_THROTTLE_CFG,
1053
+
.channels = 1,
1054
+
.buswidth = 4,
1055
+
};
1056
+
1057
+
static struct qcom_icc_node qhs_aoss = {
1058
+
.name = "qhs_aoss",
1059
+
.id = SA8775P_SLAVE_AOSS,
1060
+
.channels = 1,
1061
+
.buswidth = 4,
1062
+
};
1063
+
1064
+
static struct qcom_icc_node qhs_apss = {
1065
+
.name = "qhs_apss",
1066
+
.id = SA8775P_SLAVE_APPSS,
1067
+
.channels = 1,
1068
+
.buswidth = 8,
1069
+
};
1070
+
1071
+
static struct qcom_icc_node qhs_boot_rom = {
1072
+
.name = "qhs_boot_rom",
1073
+
.id = SA8775P_SLAVE_BOOT_ROM,
1074
+
.channels = 1,
1075
+
.buswidth = 4,
1076
+
};
1077
+
1078
+
static struct qcom_icc_node qhs_camera_cfg = {
1079
+
.name = "qhs_camera_cfg",
1080
+
.id = SA8775P_SLAVE_CAMERA_CFG,
1081
+
.channels = 1,
1082
+
.buswidth = 4,
1083
+
};
1084
+
1085
+
static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
1086
+
.name = "qhs_camera_nrt_throttle_cfg",
1087
+
.id = SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG,
1088
+
.channels = 1,
1089
+
.buswidth = 4,
1090
+
};
1091
+
1092
+
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
1093
+
.name = "qhs_camera_rt_throttle_cfg",
1094
+
.id = SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG,
1095
+
.channels = 1,
1096
+
.buswidth = 4,
1097
+
};
1098
+
1099
+
static struct qcom_icc_node qhs_clk_ctl = {
1100
+
.name = "qhs_clk_ctl",
1101
+
.id = SA8775P_SLAVE_CLK_CTL,
1102
+
.channels = 1,
1103
+
.buswidth = 4,
1104
+
};
1105
+
1106
+
static struct qcom_icc_node qhs_compute0_cfg = {
1107
+
.name = "qhs_compute0_cfg",
1108
+
.id = SA8775P_SLAVE_CDSP_CFG,
1109
+
.channels = 1,
1110
+
.buswidth = 4,
1111
+
.num_links = 1,
1112
+
.links = { SA8775P_MASTER_CDSP_NOC_CFG },
1113
+
};
1114
+
1115
+
static struct qcom_icc_node qhs_compute1_cfg = {
1116
+
.name = "qhs_compute1_cfg",
1117
+
.id = SA8775P_SLAVE_CDSP1_CFG,
1118
+
.channels = 1,
1119
+
.buswidth = 4,
1120
+
.num_links = 1,
1121
+
.links = { SA8775P_MASTER_CDSPB_NOC_CFG },
1122
+
};
1123
+
1124
+
static struct qcom_icc_node qhs_cpr_cx = {
1125
+
.name = "qhs_cpr_cx",
1126
+
.id = SA8775P_SLAVE_RBCPR_CX_CFG,
1127
+
.channels = 1,
1128
+
.buswidth = 4,
1129
+
};
1130
+
1131
+
static struct qcom_icc_node qhs_cpr_mmcx = {
1132
+
.name = "qhs_cpr_mmcx",
1133
+
.id = SA8775P_SLAVE_RBCPR_MMCX_CFG,
1134
+
.channels = 1,
1135
+
.buswidth = 4,
1136
+
};
1137
+
1138
+
static struct qcom_icc_node qhs_cpr_mx = {
1139
+
.name = "qhs_cpr_mx",
1140
+
.id = SA8775P_SLAVE_RBCPR_MX_CFG,
1141
+
.channels = 1,
1142
+
.buswidth = 4,
1143
+
};
1144
+
1145
+
static struct qcom_icc_node qhs_cpr_nspcx = {
1146
+
.name = "qhs_cpr_nspcx",
1147
+
.id = SA8775P_SLAVE_CPR_NSPCX,
1148
+
.channels = 1,
1149
+
.buswidth = 4,
1150
+
};
1151
+
1152
+
static struct qcom_icc_node qhs_crypto0_cfg = {
1153
+
.name = "qhs_crypto0_cfg",
1154
+
.id = SA8775P_SLAVE_CRYPTO_0_CFG,
1155
+
.channels = 1,
1156
+
.buswidth = 4,
1157
+
};
1158
+
1159
+
static struct qcom_icc_node qhs_cx_rdpm = {
1160
+
.name = "qhs_cx_rdpm",
1161
+
.id = SA8775P_SLAVE_CX_RDPM,
1162
+
.channels = 1,
1163
+
.buswidth = 4,
1164
+
};
1165
+
1166
+
static struct qcom_icc_node qhs_display0_cfg = {
1167
+
.name = "qhs_display0_cfg",
1168
+
.id = SA8775P_SLAVE_DISPLAY_CFG,
1169
+
.channels = 1,
1170
+
.buswidth = 4,
1171
+
};
1172
+
1173
+
static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
1174
+
.name = "qhs_display0_rt_throttle_cfg",
1175
+
.id = SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG,
1176
+
.channels = 1,
1177
+
.buswidth = 4,
1178
+
};
1179
+
1180
+
static struct qcom_icc_node qhs_display1_cfg = {
1181
+
.name = "qhs_display1_cfg",
1182
+
.id = SA8775P_SLAVE_DISPLAY1_CFG,
1183
+
.channels = 1,
1184
+
.buswidth = 4,
1185
+
};
1186
+
1187
+
static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
1188
+
.name = "qhs_display1_rt_throttle_cfg",
1189
+
.id = SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
1190
+
.channels = 1,
1191
+
.buswidth = 4,
1192
+
};
1193
+
1194
+
static struct qcom_icc_node qhs_emac0_cfg = {
1195
+
.name = "qhs_emac0_cfg",
1196
+
.id = SA8775P_SLAVE_EMAC_CFG,
1197
+
.channels = 1,
1198
+
.buswidth = 4,
1199
+
};
1200
+
1201
+
static struct qcom_icc_node qhs_emac1_cfg = {
1202
+
.name = "qhs_emac1_cfg",
1203
+
.id = SA8775P_SLAVE_EMAC1_CFG,
1204
+
.channels = 1,
1205
+
.buswidth = 4,
1206
+
};
1207
+
1208
+
static struct qcom_icc_node qhs_gp_dsp0_cfg = {
1209
+
.name = "qhs_gp_dsp0_cfg",
1210
+
.id = SA8775P_SLAVE_GP_DSP0_CFG,
1211
+
.channels = 1,
1212
+
.buswidth = 4,
1213
+
};
1214
+
1215
+
static struct qcom_icc_node qhs_gp_dsp1_cfg = {
1216
+
.name = "qhs_gp_dsp1_cfg",
1217
+
.id = SA8775P_SLAVE_GP_DSP1_CFG,
1218
+
.channels = 1,
1219
+
.buswidth = 4,
1220
+
};
1221
+
1222
+
static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
1223
+
.name = "qhs_gpdsp0_throttle_cfg",
1224
+
.id = SA8775P_SLAVE_GPDSP0_THROTTLE_CFG,
1225
+
.channels = 1,
1226
+
.buswidth = 4,
1227
+
};
1228
+
1229
+
static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
1230
+
.name = "qhs_gpdsp1_throttle_cfg",
1231
+
.id = SA8775P_SLAVE_GPDSP1_THROTTLE_CFG,
1232
+
.channels = 1,
1233
+
.buswidth = 4,
1234
+
};
1235
+
1236
+
static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
1237
+
.name = "qhs_gpu_tcu_throttle_cfg",
1238
+
.id = SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG,
1239
+
.channels = 1,
1240
+
.buswidth = 4,
1241
+
};
1242
+
1243
+
static struct qcom_icc_node qhs_gpuss_cfg = {
1244
+
.name = "qhs_gpuss_cfg",
1245
+
.id = SA8775P_SLAVE_GFX3D_CFG,
1246
+
.channels = 1,
1247
+
.buswidth = 8,
1248
+
};
1249
+
1250
+
static struct qcom_icc_node qhs_hwkm = {
1251
+
.name = "qhs_hwkm",
1252
+
.id = SA8775P_SLAVE_HWKM,
1253
+
.channels = 1,
1254
+
.buswidth = 4,
1255
+
};
1256
+
1257
+
static struct qcom_icc_node qhs_imem_cfg = {
1258
+
.name = "qhs_imem_cfg",
1259
+
.id = SA8775P_SLAVE_IMEM_CFG,
1260
+
.channels = 1,
1261
+
.buswidth = 4,
1262
+
};
1263
+
1264
+
static struct qcom_icc_node qhs_ipa = {
1265
+
.name = "qhs_ipa",
1266
+
.id = SA8775P_SLAVE_IPA_CFG,
1267
+
.channels = 1,
1268
+
.buswidth = 4,
1269
+
};
1270
+
1271
+
static struct qcom_icc_node qhs_ipc_router = {
1272
+
.name = "qhs_ipc_router",
1273
+
.id = SA8775P_SLAVE_IPC_ROUTER_CFG,
1274
+
.channels = 1,
1275
+
.buswidth = 4,
1276
+
};
1277
+
1278
+
static struct qcom_icc_node qhs_lpass_cfg = {
1279
+
.name = "qhs_lpass_cfg",
1280
+
.id = SA8775P_SLAVE_LPASS,
1281
+
.channels = 1,
1282
+
.buswidth = 4,
1283
+
.num_links = 1,
1284
+
.links = { SA8775P_MASTER_CNOC_LPASS_AG_NOC },
1285
+
};
1286
+
1287
+
static struct qcom_icc_node qhs_lpass_throttle_cfg = {
1288
+
.name = "qhs_lpass_throttle_cfg",
1289
+
.id = SA8775P_SLAVE_LPASS_THROTTLE_CFG,
1290
+
.channels = 1,
1291
+
.buswidth = 4,
1292
+
};
1293
+
1294
+
static struct qcom_icc_node qhs_mx_rdpm = {
1295
+
.name = "qhs_mx_rdpm",
1296
+
.id = SA8775P_SLAVE_MX_RDPM,
1297
+
.channels = 1,
1298
+
.buswidth = 4,
1299
+
};
1300
+
1301
+
static struct qcom_icc_node qhs_mxc_rdpm = {
1302
+
.name = "qhs_mxc_rdpm",
1303
+
.id = SA8775P_SLAVE_MXC_RDPM,
1304
+
.channels = 1,
1305
+
.buswidth = 4,
1306
+
};
1307
+
1308
+
static struct qcom_icc_node qhs_pcie0_cfg = {
1309
+
.name = "qhs_pcie0_cfg",
1310
+
.id = SA8775P_SLAVE_PCIE_0_CFG,
1311
+
.channels = 1,
1312
+
.buswidth = 4,
1313
+
};
1314
+
1315
+
static struct qcom_icc_node qhs_pcie1_cfg = {
1316
+
.name = "qhs_pcie1_cfg",
1317
+
.id = SA8775P_SLAVE_PCIE_1_CFG,
1318
+
.channels = 1,
1319
+
.buswidth = 4,
1320
+
};
1321
+
1322
+
static struct qcom_icc_node qhs_pcie_rsc_cfg = {
1323
+
.name = "qhs_pcie_rsc_cfg",
1324
+
.id = SA8775P_SLAVE_PCIE_RSC_CFG,
1325
+
.channels = 1,
1326
+
.buswidth = 4,
1327
+
};
1328
+
1329
+
static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
1330
+
.name = "qhs_pcie_tcu_throttle_cfg",
1331
+
.id = SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG,
1332
+
.channels = 1,
1333
+
.buswidth = 4,
1334
+
};
1335
+
1336
+
static struct qcom_icc_node qhs_pcie_throttle_cfg = {
1337
+
.name = "qhs_pcie_throttle_cfg",
1338
+
.id = SA8775P_SLAVE_PCIE_THROTTLE_CFG,
1339
+
.channels = 1,
1340
+
.buswidth = 4,
1341
+
};
1342
+
1343
+
static struct qcom_icc_node qhs_pdm = {
1344
+
.name = "qhs_pdm",
1345
+
.id = SA8775P_SLAVE_PDM,
1346
+
.channels = 1,
1347
+
.buswidth = 4,
1348
+
};
1349
+
1350
+
static struct qcom_icc_node qhs_pimem_cfg = {
1351
+
.name = "qhs_pimem_cfg",
1352
+
.id = SA8775P_SLAVE_PIMEM_CFG,
1353
+
.channels = 1,
1354
+
.buswidth = 4,
1355
+
};
1356
+
1357
+
static struct qcom_icc_node qhs_pke_wrapper_cfg = {
1358
+
.name = "qhs_pke_wrapper_cfg",
1359
+
.id = SA8775P_SLAVE_PKA_WRAPPER_CFG,
1360
+
.channels = 1,
1361
+
.buswidth = 4,
1362
+
};
1363
+
1364
+
static struct qcom_icc_node qhs_qdss_cfg = {
1365
+
.name = "qhs_qdss_cfg",
1366
+
.id = SA8775P_SLAVE_QDSS_CFG,
1367
+
.channels = 1,
1368
+
.buswidth = 4,
1369
+
};
1370
+
1371
+
static struct qcom_icc_node qhs_qm_cfg = {
1372
+
.name = "qhs_qm_cfg",
1373
+
.id = SA8775P_SLAVE_QM_CFG,
1374
+
.channels = 1,
1375
+
.buswidth = 4,
1376
+
};
1377
+
1378
+
static struct qcom_icc_node qhs_qm_mpu_cfg = {
1379
+
.name = "qhs_qm_mpu_cfg",
1380
+
.id = SA8775P_SLAVE_QM_MPU_CFG,
1381
+
.channels = 1,
1382
+
.buswidth = 4,
1383
+
};
1384
+
1385
+
static struct qcom_icc_node qhs_qup0 = {
1386
+
.name = "qhs_qup0",
1387
+
.id = SA8775P_SLAVE_QUP_0,
1388
+
.channels = 1,
1389
+
.buswidth = 4,
1390
+
};
1391
+
1392
+
static struct qcom_icc_node qhs_qup1 = {
1393
+
.name = "qhs_qup1",
1394
+
.id = SA8775P_SLAVE_QUP_1,
1395
+
.channels = 1,
1396
+
.buswidth = 4,
1397
+
};
1398
+
1399
+
static struct qcom_icc_node qhs_qup2 = {
1400
+
.name = "qhs_qup2",
1401
+
.id = SA8775P_SLAVE_QUP_2,
1402
+
.channels = 1,
1403
+
.buswidth = 4,
1404
+
};
1405
+
1406
+
static struct qcom_icc_node qhs_qup3 = {
1407
+
.name = "qhs_qup3",
1408
+
.id = SA8775P_SLAVE_QUP_3,
1409
+
.channels = 1,
1410
+
.buswidth = 4,
1411
+
};
1412
+
1413
+
static struct qcom_icc_node qhs_sail_throttle_cfg = {
1414
+
.name = "qhs_sail_throttle_cfg",
1415
+
.id = SA8775P_SLAVE_SAIL_THROTTLE_CFG,
1416
+
.channels = 1,
1417
+
.buswidth = 4,
1418
+
};
1419
+
1420
+
static struct qcom_icc_node qhs_sdc1 = {
1421
+
.name = "qhs_sdc1",
1422
+
.id = SA8775P_SLAVE_SDC1,
1423
+
.channels = 1,
1424
+
.buswidth = 4,
1425
+
};
1426
+
1427
+
static struct qcom_icc_node qhs_security = {
1428
+
.name = "qhs_security",
1429
+
.id = SA8775P_SLAVE_SECURITY,
1430
+
.channels = 1,
1431
+
.buswidth = 4,
1432
+
};
1433
+
1434
+
static struct qcom_icc_node qhs_snoc_throttle_cfg = {
1435
+
.name = "qhs_snoc_throttle_cfg",
1436
+
.id = SA8775P_SLAVE_SNOC_THROTTLE_CFG,
1437
+
.channels = 1,
1438
+
.buswidth = 4,
1439
+
};
1440
+
1441
+
static struct qcom_icc_node qhs_tcsr = {
1442
+
.name = "qhs_tcsr",
1443
+
.id = SA8775P_SLAVE_TCSR,
1444
+
.channels = 1,
1445
+
.buswidth = 4,
1446
+
};
1447
+
1448
+
static struct qcom_icc_node qhs_tlmm = {
1449
+
.name = "qhs_tlmm",
1450
+
.id = SA8775P_SLAVE_TLMM,
1451
+
.channels = 1,
1452
+
.buswidth = 4,
1453
+
};
1454
+
1455
+
static struct qcom_icc_node qhs_tsc_cfg = {
1456
+
.name = "qhs_tsc_cfg",
1457
+
.id = SA8775P_SLAVE_TSC_CFG,
1458
+
.channels = 1,
1459
+
.buswidth = 4,
1460
+
};
1461
+
1462
+
static struct qcom_icc_node qhs_ufs_card_cfg = {
1463
+
.name = "qhs_ufs_card_cfg",
1464
+
.id = SA8775P_SLAVE_UFS_CARD_CFG,
1465
+
.channels = 1,
1466
+
.buswidth = 4,
1467
+
};
1468
+
1469
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1470
+
.name = "qhs_ufs_mem_cfg",
1471
+
.id = SA8775P_SLAVE_UFS_MEM_CFG,
1472
+
.channels = 1,
1473
+
.buswidth = 4,
1474
+
};
1475
+
1476
+
static struct qcom_icc_node qhs_usb2_0 = {
1477
+
.name = "qhs_usb2_0",
1478
+
.id = SA8775P_SLAVE_USB2,
1479
+
.channels = 1,
1480
+
.buswidth = 4,
1481
+
};
1482
+
1483
+
static struct qcom_icc_node qhs_usb3_0 = {
1484
+
.name = "qhs_usb3_0",
1485
+
.id = SA8775P_SLAVE_USB3_0,
1486
+
.channels = 1,
1487
+
.buswidth = 4,
1488
+
};
1489
+
1490
+
static struct qcom_icc_node qhs_usb3_1 = {
1491
+
.name = "qhs_usb3_1",
1492
+
.id = SA8775P_SLAVE_USB3_1,
1493
+
.channels = 1,
1494
+
.buswidth = 4,
1495
+
};
1496
+
1497
+
static struct qcom_icc_node qhs_venus_cfg = {
1498
+
.name = "qhs_venus_cfg",
1499
+
.id = SA8775P_SLAVE_VENUS_CFG,
1500
+
.channels = 1,
1501
+
.buswidth = 4,
1502
+
};
1503
+
1504
+
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1505
+
.name = "qhs_venus_cvp_throttle_cfg",
1506
+
.id = SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG,
1507
+
.channels = 1,
1508
+
.buswidth = 4,
1509
+
};
1510
+
1511
+
static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
1512
+
.name = "qhs_venus_v_cpu_throttle_cfg",
1513
+
.id = SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
1514
+
.channels = 1,
1515
+
.buswidth = 4,
1516
+
};
1517
+
1518
+
static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
1519
+
.name = "qhs_venus_vcodec_throttle_cfg",
1520
+
.id = SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
1521
+
.channels = 1,
1522
+
.buswidth = 4,
1523
+
};
1524
+
1525
+
static struct qcom_icc_node qns_ddrss_cfg = {
1526
+
.name = "qns_ddrss_cfg",
1527
+
.id = SA8775P_SLAVE_DDRSS_CFG,
1528
+
.channels = 1,
1529
+
.buswidth = 4,
1530
+
.num_links = 1,
1531
+
.links = { SA8775P_MASTER_CNOC_DC_NOC },
1532
+
};
1533
+
1534
+
static struct qcom_icc_node qns_gpdsp_noc_cfg = {
1535
+
.name = "qns_gpdsp_noc_cfg",
1536
+
.id = SA8775P_SLAVE_GPDSP_NOC_CFG,
1537
+
.channels = 1,
1538
+
.buswidth = 4,
1539
+
};
1540
+
1541
+
static struct qcom_icc_node qns_mnoc_hf_cfg = {
1542
+
.name = "qns_mnoc_hf_cfg",
1543
+
.id = SA8775P_SLAVE_CNOC_MNOC_HF_CFG,
1544
+
.channels = 1,
1545
+
.buswidth = 4,
1546
+
.num_links = 1,
1547
+
.links = { SA8775P_MASTER_CNOC_MNOC_HF_CFG },
1548
+
};
1549
+
1550
+
static struct qcom_icc_node qns_mnoc_sf_cfg = {
1551
+
.name = "qns_mnoc_sf_cfg",
1552
+
.id = SA8775P_SLAVE_CNOC_MNOC_SF_CFG,
1553
+
.channels = 1,
1554
+
.buswidth = 4,
1555
+
.num_links = 1,
1556
+
.links = { SA8775P_MASTER_CNOC_MNOC_SF_CFG },
1557
+
};
1558
+
1559
+
static struct qcom_icc_node qns_pcie_anoc_cfg = {
1560
+
.name = "qns_pcie_anoc_cfg",
1561
+
.id = SA8775P_SLAVE_PCIE_ANOC_CFG,
1562
+
.channels = 1,
1563
+
.buswidth = 4,
1564
+
};
1565
+
1566
+
static struct qcom_icc_node qns_snoc_cfg = {
1567
+
.name = "qns_snoc_cfg",
1568
+
.id = SA8775P_SLAVE_SNOC_CFG,
1569
+
.channels = 1,
1570
+
.buswidth = 4,
1571
+
.num_links = 1,
1572
+
.links = { SA8775P_MASTER_SNOC_CFG },
1573
+
};
1574
+
1575
+
static struct qcom_icc_node qxs_boot_imem = {
1576
+
.name = "qxs_boot_imem",
1577
+
.id = SA8775P_SLAVE_BOOT_IMEM,
1578
+
.channels = 1,
1579
+
.buswidth = 16,
1580
+
};
1581
+
1582
+
static struct qcom_icc_node qxs_imem = {
1583
+
.name = "qxs_imem",
1584
+
.id = SA8775P_SLAVE_IMEM,
1585
+
.channels = 1,
1586
+
.buswidth = 8,
1587
+
};
1588
+
1589
+
static struct qcom_icc_node qxs_pimem = {
1590
+
.name = "qxs_pimem",
1591
+
.id = SA8775P_SLAVE_PIMEM,
1592
+
.channels = 1,
1593
+
.buswidth = 8,
1594
+
};
1595
+
1596
+
static struct qcom_icc_node xs_pcie_0 = {
1597
+
.name = "xs_pcie_0",
1598
+
.id = SA8775P_SLAVE_PCIE_0,
1599
+
.channels = 1,
1600
+
.buswidth = 16,
1601
+
};
1602
+
1603
+
static struct qcom_icc_node xs_pcie_1 = {
1604
+
.name = "xs_pcie_1",
1605
+
.id = SA8775P_SLAVE_PCIE_1,
1606
+
.channels = 1,
1607
+
.buswidth = 32,
1608
+
};
1609
+
1610
+
static struct qcom_icc_node xs_qdss_stm = {
1611
+
.name = "xs_qdss_stm",
1612
+
.id = SA8775P_SLAVE_QDSS_STM,
1613
+
.channels = 1,
1614
+
.buswidth = 4,
1615
+
};
1616
+
1617
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1618
+
.name = "xs_sys_tcu_cfg",
1619
+
.id = SA8775P_SLAVE_TCU,
1620
+
.channels = 1,
1621
+
.buswidth = 8,
1622
+
};
1623
+
1624
+
static struct qcom_icc_node qhs_llcc = {
1625
+
.name = "qhs_llcc",
1626
+
.id = SA8775P_SLAVE_LLCC_CFG,
1627
+
.channels = 1,
1628
+
.buswidth = 4,
1629
+
};
1630
+
1631
+
static struct qcom_icc_node qns_gemnoc = {
1632
+
.name = "qns_gemnoc",
1633
+
.id = SA8775P_SLAVE_GEM_NOC_CFG,
1634
+
.channels = 1,
1635
+
.buswidth = 4,
1636
+
.num_links = 1,
1637
+
.links = { SA8775P_MASTER_GEM_NOC_CFG },
1638
+
};
1639
+
1640
+
static struct qcom_icc_node qns_gem_noc_cnoc = {
1641
+
.name = "qns_gem_noc_cnoc",
1642
+
.id = SA8775P_SLAVE_GEM_NOC_CNOC,
1643
+
.channels = 1,
1644
+
.buswidth = 16,
1645
+
.num_links = 1,
1646
+
.links = { SA8775P_MASTER_GEM_NOC_CNOC },
1647
+
};
1648
+
1649
+
static struct qcom_icc_node qns_llcc = {
1650
+
.name = "qns_llcc",
1651
+
.id = SA8775P_SLAVE_LLCC,
1652
+
.channels = 6,
1653
+
.buswidth = 16,
1654
+
.num_links = 1,
1655
+
.links = { SA8775P_MASTER_LLCC },
1656
+
};
1657
+
1658
+
static struct qcom_icc_node qns_pcie = {
1659
+
.name = "qns_pcie",
1660
+
.id = SA8775P_SLAVE_GEM_NOC_PCIE_CNOC,
1661
+
.channels = 1,
1662
+
.buswidth = 16,
1663
+
.num_links = 1,
1664
+
.links = { SA8775P_MASTER_GEM_NOC_PCIE_SNOC },
1665
+
};
1666
+
1667
+
static struct qcom_icc_node srvc_even_gemnoc = {
1668
+
.name = "srvc_even_gemnoc",
1669
+
.id = SA8775P_SLAVE_SERVICE_GEM_NOC_1,
1670
+
.channels = 1,
1671
+
.buswidth = 4,
1672
+
};
1673
+
1674
+
static struct qcom_icc_node srvc_odd_gemnoc = {
1675
+
.name = "srvc_odd_gemnoc",
1676
+
.id = SA8775P_SLAVE_SERVICE_GEM_NOC_2,
1677
+
.channels = 1,
1678
+
.buswidth = 4,
1679
+
};
1680
+
1681
+
static struct qcom_icc_node srvc_sys_gemnoc = {
1682
+
.name = "srvc_sys_gemnoc",
1683
+
.id = SA8775P_SLAVE_SERVICE_GEM_NOC,
1684
+
.channels = 1,
1685
+
.buswidth = 4,
1686
+
};
1687
+
1688
+
static struct qcom_icc_node srvc_sys_gemnoc_2 = {
1689
+
.name = "srvc_sys_gemnoc_2",
1690
+
.id = SA8775P_SLAVE_SERVICE_GEM_NOC2,
1691
+
.channels = 1,
1692
+
.buswidth = 4,
1693
+
};
1694
+
1695
+
static struct qcom_icc_node qns_gp_dsp_sail_noc = {
1696
+
.name = "qns_gp_dsp_sail_noc",
1697
+
.id = SA8775P_SLAVE_GP_DSP_SAIL_NOC,
1698
+
.channels = 1,
1699
+
.buswidth = 16,
1700
+
.num_links = 1,
1701
+
.links = { SA8775P_MASTER_GPDSP_SAIL },
1702
+
};
1703
+
1704
+
static struct qcom_icc_node qhs_lpass_core = {
1705
+
.name = "qhs_lpass_core",
1706
+
.id = SA8775P_SLAVE_LPASS_CORE_CFG,
1707
+
.channels = 1,
1708
+
.buswidth = 4,
1709
+
};
1710
+
1711
+
static struct qcom_icc_node qhs_lpass_lpi = {
1712
+
.name = "qhs_lpass_lpi",
1713
+
.id = SA8775P_SLAVE_LPASS_LPI_CFG,
1714
+
.channels = 1,
1715
+
.buswidth = 4,
1716
+
};
1717
+
1718
+
static struct qcom_icc_node qhs_lpass_mpu = {
1719
+
.name = "qhs_lpass_mpu",
1720
+
.id = SA8775P_SLAVE_LPASS_MPU_CFG,
1721
+
.channels = 1,
1722
+
.buswidth = 4,
1723
+
};
1724
+
1725
+
static struct qcom_icc_node qhs_lpass_top = {
1726
+
.name = "qhs_lpass_top",
1727
+
.id = SA8775P_SLAVE_LPASS_TOP_CFG,
1728
+
.channels = 1,
1729
+
.buswidth = 4,
1730
+
};
1731
+
1732
+
static struct qcom_icc_node qns_sysnoc = {
1733
+
.name = "qns_sysnoc",
1734
+
.id = SA8775P_SLAVE_LPASS_SNOC,
1735
+
.channels = 1,
1736
+
.buswidth = 16,
1737
+
.num_links = 1,
1738
+
.links = { SA8775P_MASTER_LPASS_ANOC },
1739
+
};
1740
+
1741
+
static struct qcom_icc_node srvc_niu_aml_noc = {
1742
+
.name = "srvc_niu_aml_noc",
1743
+
.id = SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
1744
+
.channels = 1,
1745
+
.buswidth = 4,
1746
+
};
1747
+
1748
+
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1749
+
.name = "srvc_niu_lpass_agnoc",
1750
+
.id = SA8775P_SLAVE_SERVICE_LPASS_AG_NOC,
1751
+
.channels = 1,
1752
+
.buswidth = 4,
1753
+
};
1754
+
1755
+
static struct qcom_icc_node ebi = {
1756
+
.name = "ebi",
1757
+
.id = SA8775P_SLAVE_EBI1,
1758
+
.channels = 8,
1759
+
.buswidth = 4,
1760
+
};
1761
+
1762
+
static struct qcom_icc_node qns_mem_noc_hf = {
1763
+
.name = "qns_mem_noc_hf",
1764
+
.id = SA8775P_SLAVE_MNOC_HF_MEM_NOC,
1765
+
.channels = 2,
1766
+
.buswidth = 32,
1767
+
.num_links = 1,
1768
+
.links = { SA8775P_MASTER_MNOC_HF_MEM_NOC },
1769
+
};
1770
+
1771
+
static struct qcom_icc_node qns_mem_noc_sf = {
1772
+
.name = "qns_mem_noc_sf",
1773
+
.id = SA8775P_SLAVE_MNOC_SF_MEM_NOC,
1774
+
.channels = 2,
1775
+
.buswidth = 32,
1776
+
.num_links = 1,
1777
+
.links = { SA8775P_MASTER_MNOC_SF_MEM_NOC },
1778
+
};
1779
+
1780
+
static struct qcom_icc_node srvc_mnoc_hf = {
1781
+
.name = "srvc_mnoc_hf",
1782
+
.id = SA8775P_SLAVE_SERVICE_MNOC_HF,
1783
+
.channels = 1,
1784
+
.buswidth = 4,
1785
+
};
1786
+
1787
+
static struct qcom_icc_node srvc_mnoc_sf = {
1788
+
.name = "srvc_mnoc_sf",
1789
+
.id = SA8775P_SLAVE_SERVICE_MNOC_SF,
1790
+
.channels = 1,
1791
+
.buswidth = 4,
1792
+
};
1793
+
1794
+
static struct qcom_icc_node qns_hcp = {
1795
+
.name = "qns_hcp",
1796
+
.id = SA8775P_SLAVE_HCP_A,
1797
+
.channels = 2,
1798
+
.buswidth = 32,
1799
+
};
1800
+
1801
+
static struct qcom_icc_node qns_nsp_gemnoc = {
1802
+
.name = "qns_nsp_gemnoc",
1803
+
.id = SA8775P_SLAVE_CDSP_MEM_NOC,
1804
+
.channels = 2,
1805
+
.buswidth = 32,
1806
+
.num_links = 1,
1807
+
.links = { SA8775P_MASTER_COMPUTE_NOC },
1808
+
};
1809
+
1810
+
static struct qcom_icc_node service_nsp_noc = {
1811
+
.name = "service_nsp_noc",
1812
+
.id = SA8775P_SLAVE_SERVICE_NSP_NOC,
1813
+
.channels = 1,
1814
+
.buswidth = 4,
1815
+
};
1816
+
1817
+
static struct qcom_icc_node qns_nspb_gemnoc = {
1818
+
.name = "qns_nspb_gemnoc",
1819
+
.id = SA8775P_SLAVE_CDSPB_MEM_NOC,
1820
+
.channels = 2,
1821
+
.buswidth = 32,
1822
+
.num_links = 1,
1823
+
.links = { SA8775P_MASTER_COMPUTE_NOC_1 },
1824
+
};
1825
+
1826
+
static struct qcom_icc_node qns_nspb_hcp = {
1827
+
.name = "qns_nspb_hcp",
1828
+
.id = SA8775P_SLAVE_HCP_B,
1829
+
.channels = 2,
1830
+
.buswidth = 32,
1831
+
};
1832
+
1833
+
static struct qcom_icc_node service_nspb_noc = {
1834
+
.name = "service_nspb_noc",
1835
+
.id = SA8775P_SLAVE_SERVICE_NSPB_NOC,
1836
+
.channels = 1,
1837
+
.buswidth = 4,
1838
+
};
1839
+
1840
+
static struct qcom_icc_node qns_pcie_mem_noc = {
1841
+
.name = "qns_pcie_mem_noc",
1842
+
.id = SA8775P_SLAVE_ANOC_PCIE_GEM_NOC,
1843
+
.channels = 1,
1844
+
.buswidth = 32,
1845
+
.num_links = 1,
1846
+
.links = { SA8775P_MASTER_ANOC_PCIE_GEM_NOC },
1847
+
};
1848
+
1849
+
static struct qcom_icc_node qns_gemnoc_gc = {
1850
+
.name = "qns_gemnoc_gc",
1851
+
.id = SA8775P_SLAVE_SNOC_GEM_NOC_GC,
1852
+
.channels = 1,
1853
+
.buswidth = 8,
1854
+
.num_links = 1,
1855
+
.links = { SA8775P_MASTER_SNOC_GC_MEM_NOC },
1856
+
};
1857
+
1858
+
static struct qcom_icc_node qns_gemnoc_sf = {
1859
+
.name = "qns_gemnoc_sf",
1860
+
.id = SA8775P_SLAVE_SNOC_GEM_NOC_SF,
1861
+
.channels = 1,
1862
+
.buswidth = 16,
1863
+
.num_links = 1,
1864
+
.links = { SA8775P_MASTER_SNOC_SF_MEM_NOC },
1865
+
};
1866
+
1867
+
static struct qcom_icc_node srvc_snoc = {
1868
+
.name = "srvc_snoc",
1869
+
.id = SA8775P_SLAVE_SERVICE_SNOC,
1870
+
.channels = 1,
1871
+
.buswidth = 4,
1872
+
};
1873
+
1874
+
static struct qcom_icc_bcm bcm_acv = {
1875
+
.name = "ACV",
1876
+
.num_nodes = 1,
1877
+
.nodes = { &ebi },
1878
+
};
1879
+
1880
+
static struct qcom_icc_bcm bcm_ce0 = {
1881
+
.name = "CE0",
1882
+
.num_nodes = 2,
1883
+
.nodes = { &qxm_crypto_0, &qxm_crypto_1 },
1884
+
};
1885
+
1886
+
static struct qcom_icc_bcm bcm_cn0 = {
1887
+
.name = "CN0",
1888
+
.keepalive = true,
1889
+
.num_nodes = 2,
1890
+
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1891
+
};
1892
+
1893
+
static struct qcom_icc_bcm bcm_cn1 = {
1894
+
.name = "CN1",
1895
+
.num_nodes = 76,
1896
+
.nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
1897
+
&qhs_ahb2phy2, &qhs_ahb2phy3,
1898
+
&qhs_anoc_throttle_cfg, &qhs_aoss,
1899
+
&qhs_apss, &qhs_boot_rom,
1900
+
&qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
1901
+
&qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
1902
+
&qhs_compute0_cfg, &qhs_compute1_cfg,
1903
+
&qhs_cpr_cx, &qhs_cpr_mmcx,
1904
+
&qhs_cpr_mx, &qhs_cpr_nspcx,
1905
+
&qhs_crypto0_cfg, &qhs_cx_rdpm,
1906
+
&qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
1907
+
&qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
1908
+
&qhs_emac0_cfg, &qhs_emac1_cfg,
1909
+
&qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
1910
+
&qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
1911
+
&qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
1912
+
&qhs_hwkm, &qhs_imem_cfg,
1913
+
&qhs_ipa, &qhs_ipc_router,
1914
+
&qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
1915
+
&qhs_mx_rdpm, &qhs_mxc_rdpm,
1916
+
&qhs_pcie0_cfg, &qhs_pcie1_cfg,
1917
+
&qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
1918
+
&qhs_pcie_throttle_cfg, &qhs_pdm,
1919
+
&qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
1920
+
&qhs_qdss_cfg, &qhs_qm_cfg,
1921
+
&qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
1922
+
&qhs_sdc1, &qhs_security,
1923
+
&qhs_snoc_throttle_cfg, &qhs_tcsr,
1924
+
&qhs_tlmm, &qhs_tsc_cfg,
1925
+
&qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
1926
+
&qhs_usb2_0, &qhs_usb3_0,
1927
+
&qhs_usb3_1, &qhs_venus_cfg,
1928
+
&qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
1929
+
&qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
1930
+
&qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
1931
+
&qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
1932
+
&qns_snoc_cfg, &qxs_boot_imem,
1933
+
&qxs_imem, &xs_sys_tcu_cfg },
1934
+
};
1935
+
1936
+
static struct qcom_icc_bcm bcm_cn2 = {
1937
+
.name = "CN2",
1938
+
.num_nodes = 4,
1939
+
.nodes = { &qhs_qup0, &qhs_qup1,
1940
+
&qhs_qup2, &qhs_qup3 },
1941
+
};
1942
+
1943
+
static struct qcom_icc_bcm bcm_cn3 = {
1944
+
.name = "CN3",
1945
+
.num_nodes = 2,
1946
+
.nodes = { &xs_pcie_0, &xs_pcie_1 },
1947
+
};
1948
+
1949
+
static struct qcom_icc_bcm bcm_gna0 = {
1950
+
.name = "GNA0",
1951
+
.num_nodes = 1,
1952
+
.nodes = { &qxm_dsp0 },
1953
+
};
1954
+
1955
+
static struct qcom_icc_bcm bcm_gnb0 = {
1956
+
.name = "GNB0",
1957
+
.num_nodes = 1,
1958
+
.nodes = { &qxm_dsp1 },
1959
+
};
1960
+
1961
+
static struct qcom_icc_bcm bcm_mc0 = {
1962
+
.name = "MC0",
1963
+
.keepalive = true,
1964
+
.num_nodes = 1,
1965
+
.nodes = { &ebi },
1966
+
};
1967
+
1968
+
static struct qcom_icc_bcm bcm_mm0 = {
1969
+
.name = "MM0",
1970
+
.keepalive = true,
1971
+
.num_nodes = 5,
1972
+
.nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
1973
+
&qnm_mdp0_1, &qnm_mdp1_0,
1974
+
&qns_mem_noc_hf },
1975
+
};
1976
+
1977
+
static struct qcom_icc_bcm bcm_mm1 = {
1978
+
.name = "MM1",
1979
+
.num_nodes = 7,
1980
+
.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
1981
+
&qnm_video0, &qnm_video1,
1982
+
&qnm_video_cvp, &qnm_video_v_cpu,
1983
+
&qns_mem_noc_sf },
1984
+
};
1985
+
1986
+
static struct qcom_icc_bcm bcm_nsa0 = {
1987
+
.name = "NSA0",
1988
+
.num_nodes = 2,
1989
+
.nodes = { &qns_hcp, &qns_nsp_gemnoc },
1990
+
};
1991
+
1992
+
static struct qcom_icc_bcm bcm_nsa1 = {
1993
+
.name = "NSA1",
1994
+
.num_nodes = 1,
1995
+
.nodes = { &qxm_nsp },
1996
+
};
1997
+
1998
+
static struct qcom_icc_bcm bcm_nsb0 = {
1999
+
.name = "NSB0",
2000
+
.num_nodes = 2,
2001
+
.nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
2002
+
};
2003
+
2004
+
static struct qcom_icc_bcm bcm_nsb1 = {
2005
+
.name = "NSB1",
2006
+
.num_nodes = 1,
2007
+
.nodes = { &qxm_nspb },
2008
+
};
2009
+
2010
+
static struct qcom_icc_bcm bcm_pci0 = {
2011
+
.name = "PCI0",
2012
+
.num_nodes = 1,
2013
+
.nodes = { &qns_pcie_mem_noc },
2014
+
};
2015
+
2016
+
static struct qcom_icc_bcm bcm_qup0 = {
2017
+
.name = "QUP0",
2018
+
.vote_scale = 1,
2019
+
.num_nodes = 1,
2020
+
.nodes = { &qup0_core_slave },
2021
+
};
2022
+
2023
+
static struct qcom_icc_bcm bcm_qup1 = {
2024
+
.name = "QUP1",
2025
+
.vote_scale = 1,
2026
+
.num_nodes = 1,
2027
+
.nodes = { &qup1_core_slave },
2028
+
};
2029
+
2030
+
static struct qcom_icc_bcm bcm_qup2 = {
2031
+
.name = "QUP2",
2032
+
.vote_scale = 1,
2033
+
.num_nodes = 2,
2034
+
.nodes = { &qup2_core_slave, &qup3_core_slave },
2035
+
};
2036
+
2037
+
static struct qcom_icc_bcm bcm_sh0 = {
2038
+
.name = "SH0",
2039
+
.keepalive = true,
2040
+
.num_nodes = 1,
2041
+
.nodes = { &qns_llcc },
2042
+
};
2043
+
2044
+
static struct qcom_icc_bcm bcm_sh2 = {
2045
+
.name = "SH2",
2046
+
.num_nodes = 1,
2047
+
.nodes = { &chm_apps },
2048
+
};
2049
+
2050
+
static struct qcom_icc_bcm bcm_sn0 = {
2051
+
.name = "SN0",
2052
+
.keepalive = true,
2053
+
.num_nodes = 1,
2054
+
.nodes = { &qns_gemnoc_sf },
2055
+
};
2056
+
2057
+
static struct qcom_icc_bcm bcm_sn1 = {
2058
+
.name = "SN1",
2059
+
.num_nodes = 1,
2060
+
.nodes = { &qns_gemnoc_gc },
2061
+
};
2062
+
2063
+
static struct qcom_icc_bcm bcm_sn2 = {
2064
+
.name = "SN2",
2065
+
.num_nodes = 1,
2066
+
.nodes = { &qxs_pimem },
2067
+
};
2068
+
2069
+
static struct qcom_icc_bcm bcm_sn3 = {
2070
+
.name = "SN3",
2071
+
.num_nodes = 2,
2072
+
.nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
2073
+
};
2074
+
2075
+
static struct qcom_icc_bcm bcm_sn4 = {
2076
+
.name = "SN4",
2077
+
.num_nodes = 2,
2078
+
.nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
2079
+
};
2080
+
2081
+
static struct qcom_icc_bcm bcm_sn9 = {
2082
+
.name = "SN9",
2083
+
.num_nodes = 2,
2084
+
.nodes = { &qns_sysnoc, &qnm_lpass_noc },
2085
+
};
2086
+
2087
+
static struct qcom_icc_bcm bcm_sn10 = {
2088
+
.name = "SN10",
2089
+
.num_nodes = 1,
2090
+
.nodes = { &xs_qdss_stm },
2091
+
};
2092
+
2093
+
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
2094
+
&bcm_sn3,
2095
+
};
2096
+
2097
+
static struct qcom_icc_node *aggre1_noc_nodes[] = {
2098
+
[MASTER_QUP_3] = &qxm_qup3,
2099
+
[MASTER_EMAC] = &xm_emac_0,
2100
+
[MASTER_EMAC_1] = &xm_emac_1,
2101
+
[MASTER_SDC] = &xm_sdc1,
2102
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
2103
+
[MASTER_USB2] = &xm_usb2_2,
2104
+
[MASTER_USB3_0] = &xm_usb3_0,
2105
+
[MASTER_USB3_1] = &xm_usb3_1,
2106
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
2107
+
};
2108
+
2109
+
static const struct qcom_icc_desc sa8775p_aggre1_noc = {
2110
+
.nodes = aggre1_noc_nodes,
2111
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
2112
+
.bcms = aggre1_noc_bcms,
2113
+
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
2114
+
};
2115
+
2116
+
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
2117
+
&bcm_ce0,
2118
+
&bcm_sn4,
2119
+
};
2120
+
2121
+
static struct qcom_icc_node *aggre2_noc_nodes[] = {
2122
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
2123
+
[MASTER_QUP_0] = &qhm_qup0,
2124
+
[MASTER_QUP_1] = &qhm_qup1,
2125
+
[MASTER_QUP_2] = &qhm_qup2,
2126
+
[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
2127
+
[MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
2128
+
[MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
2129
+
[MASTER_IPA] = &qxm_ipa,
2130
+
[MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
2131
+
[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
2132
+
[MASTER_UFS_CARD] = &xm_ufs_card,
2133
+
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
2134
+
};
2135
+
2136
+
static const struct qcom_icc_desc sa8775p_aggre2_noc = {
2137
+
.nodes = aggre2_noc_nodes,
2138
+
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
2139
+
.bcms = aggre2_noc_bcms,
2140
+
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
2141
+
};
2142
+
2143
+
static struct qcom_icc_bcm *clk_virt_bcms[] = {
2144
+
&bcm_qup0,
2145
+
&bcm_qup1,
2146
+
&bcm_qup2,
2147
+
};
2148
+
2149
+
static struct qcom_icc_node *clk_virt_nodes[] = {
2150
+
[MASTER_QUP_CORE_0] = &qup0_core_master,
2151
+
[MASTER_QUP_CORE_1] = &qup1_core_master,
2152
+
[MASTER_QUP_CORE_2] = &qup2_core_master,
2153
+
[MASTER_QUP_CORE_3] = &qup3_core_master,
2154
+
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
2155
+
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
2156
+
[SLAVE_QUP_CORE_2] = &qup2_core_slave,
2157
+
[SLAVE_QUP_CORE_3] = &qup3_core_slave,
2158
+
};
2159
+
2160
+
static const struct qcom_icc_desc sa8775p_clk_virt = {
2161
+
.nodes = clk_virt_nodes,
2162
+
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
2163
+
.bcms = clk_virt_bcms,
2164
+
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
2165
+
};
2166
+
2167
+
static struct qcom_icc_bcm *config_noc_bcms[] = {
2168
+
&bcm_cn0,
2169
+
&bcm_cn1,
2170
+
&bcm_cn2,
2171
+
&bcm_cn3,
2172
+
&bcm_sn2,
2173
+
&bcm_sn10,
2174
+
};
2175
+
2176
+
static struct qcom_icc_node *config_noc_nodes[] = {
2177
+
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
2178
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
2179
+
[SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
2180
+
[SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
2181
+
[SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
2182
+
[SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
2183
+
[SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
2184
+
[SLAVE_AOSS] = &qhs_aoss,
2185
+
[SLAVE_APPSS] = &qhs_apss,
2186
+
[SLAVE_BOOT_ROM] = &qhs_boot_rom,
2187
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
2188
+
[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
2189
+
[SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
2190
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
2191
+
[SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
2192
+
[SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
2193
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
2194
+
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
2195
+
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
2196
+
[SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
2197
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
2198
+
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
2199
+
[SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
2200
+
[SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
2201
+
[SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
2202
+
[SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg,
2203
+
[SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
2204
+
[SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
2205
+
[SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
2206
+
[SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg,
2207
+
[SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
2208
+
[SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg,
2209
+
[SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
2210
+
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
2211
+
[SLAVE_HWKM] = &qhs_hwkm,
2212
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
2213
+
[SLAVE_IPA_CFG] = &qhs_ipa,
2214
+
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
2215
+
[SLAVE_LPASS] = &qhs_lpass_cfg,
2216
+
[SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
2217
+
[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
2218
+
[SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
2219
+
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
2220
+
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
2221
+
[SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
2222
+
[SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
2223
+
[SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
2224
+
[SLAVE_PDM] = &qhs_pdm,
2225
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
2226
+
[SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
2227
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
2228
+
[SLAVE_QM_CFG] = &qhs_qm_cfg,
2229
+
[SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
2230
+
[SLAVE_QUP_0] = &qhs_qup0,
2231
+
[SLAVE_QUP_1] = &qhs_qup1,
2232
+
[SLAVE_QUP_2] = &qhs_qup2,
2233
+
[SLAVE_QUP_3] = &qhs_qup3,
2234
+
[SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
2235
+
[SLAVE_SDC1] = &qhs_sdc1,
2236
+
[SLAVE_SECURITY] = &qhs_security,
2237
+
[SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
2238
+
[SLAVE_TCSR] = &qhs_tcsr,
2239
+
[SLAVE_TLMM] = &qhs_tlmm,
2240
+
[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
2241
+
[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
2242
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
2243
+
[SLAVE_USB2] = &qhs_usb2_0,
2244
+
[SLAVE_USB3_0] = &qhs_usb3_0,
2245
+
[SLAVE_USB3_1] = &qhs_usb3_1,
2246
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
2247
+
[SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
2248
+
[SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
2249
+
[SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
2250
+
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
2251
+
[SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
2252
+
[SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
2253
+
[SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
2254
+
[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
2255
+
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
2256
+
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
2257
+
[SLAVE_IMEM] = &qxs_imem,
2258
+
[SLAVE_PIMEM] = &qxs_pimem,
2259
+
[SLAVE_PCIE_0] = &xs_pcie_0,
2260
+
[SLAVE_PCIE_1] = &xs_pcie_1,
2261
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
2262
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
2263
+
};
2264
+
2265
+
static const struct qcom_icc_desc sa8775p_config_noc = {
2266
+
.nodes = config_noc_nodes,
2267
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
2268
+
.bcms = config_noc_bcms,
2269
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
2270
+
};
2271
+
2272
+
static struct qcom_icc_bcm *dc_noc_bcms[] = {
2273
+
};
2274
+
2275
+
static struct qcom_icc_node *dc_noc_nodes[] = {
2276
+
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2277
+
[SLAVE_LLCC_CFG] = &qhs_llcc,
2278
+
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
2279
+
};
2280
+
2281
+
static const struct qcom_icc_desc sa8775p_dc_noc = {
2282
+
.nodes = dc_noc_nodes,
2283
+
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
2284
+
.bcms = dc_noc_bcms,
2285
+
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
2286
+
};
2287
+
2288
+
static struct qcom_icc_bcm *gem_noc_bcms[] = {
2289
+
&bcm_sh0,
2290
+
&bcm_sh2,
2291
+
};
2292
+
2293
+
static struct qcom_icc_node *gem_noc_nodes[] = {
2294
+
[MASTER_GPU_TCU] = &alm_gpu_tcu,
2295
+
[MASTER_PCIE_TCU] = &alm_pcie_tcu,
2296
+
[MASTER_SYS_TCU] = &alm_sys_tcu,
2297
+
[MASTER_APPSS_PROC] = &chm_apps,
2298
+
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
2299
+
[MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
2300
+
[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
2301
+
[MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
2302
+
[MASTER_GFX3D] = &qnm_gpu,
2303
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
2304
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
2305
+
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
2306
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
2307
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
2308
+
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
2309
+
[SLAVE_LLCC] = &qns_llcc,
2310
+
[SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
2311
+
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
2312
+
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
2313
+
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
2314
+
[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
2315
+
};
2316
+
2317
+
static const struct qcom_icc_desc sa8775p_gem_noc = {
2318
+
.nodes = gem_noc_nodes,
2319
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
2320
+
.bcms = gem_noc_bcms,
2321
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
2322
+
};
2323
+
2324
+
static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
2325
+
&bcm_gna0,
2326
+
&bcm_gnb0,
2327
+
};
2328
+
2329
+
static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
2330
+
[MASTER_DSP0] = &qxm_dsp0,
2331
+
[MASTER_DSP1] = &qxm_dsp1,
2332
+
[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
2333
+
};
2334
+
2335
+
static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
2336
+
.nodes = gpdsp_anoc_nodes,
2337
+
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
2338
+
.bcms = gpdsp_anoc_bcms,
2339
+
.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
2340
+
};
2341
+
2342
+
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
2343
+
&bcm_sn9,
2344
+
};
2345
+
2346
+
static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
2347
+
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2348
+
[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2349
+
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
2350
+
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
2351
+
[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
2352
+
[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
2353
+
[SLAVE_LPASS_SNOC] = &qns_sysnoc,
2354
+
[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
2355
+
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
2356
+
};
2357
+
2358
+
static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
2359
+
.nodes = lpass_ag_noc_nodes,
2360
+
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2361
+
.bcms = lpass_ag_noc_bcms,
2362
+
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2363
+
};
2364
+
2365
+
static struct qcom_icc_bcm *mc_virt_bcms[] = {
2366
+
&bcm_acv,
2367
+
&bcm_mc0,
2368
+
};
2369
+
2370
+
static struct qcom_icc_node *mc_virt_nodes[] = {
2371
+
[MASTER_LLCC] = &llcc_mc,
2372
+
[SLAVE_EBI1] = &ebi,
2373
+
};
2374
+
2375
+
static const struct qcom_icc_desc sa8775p_mc_virt = {
2376
+
.nodes = mc_virt_nodes,
2377
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
2378
+
.bcms = mc_virt_bcms,
2379
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
2380
+
};
2381
+
2382
+
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
2383
+
&bcm_mm0,
2384
+
&bcm_mm1,
2385
+
};
2386
+
2387
+
static struct qcom_icc_node *mmss_noc_nodes[] = {
2388
+
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2389
+
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2390
+
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2391
+
[MASTER_MDP0] = &qnm_mdp0_0,
2392
+
[MASTER_MDP1] = &qnm_mdp0_1,
2393
+
[MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
2394
+
[MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
2395
+
[MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
2396
+
[MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
2397
+
[MASTER_VIDEO_P0] = &qnm_video0,
2398
+
[MASTER_VIDEO_P1] = &qnm_video1,
2399
+
[MASTER_VIDEO_PROC] = &qnm_video_cvp,
2400
+
[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2401
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2402
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2403
+
[SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
2404
+
[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
2405
+
};
2406
+
2407
+
static const struct qcom_icc_desc sa8775p_mmss_noc = {
2408
+
.nodes = mmss_noc_nodes,
2409
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2410
+
.bcms = mmss_noc_bcms,
2411
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2412
+
};
2413
+
2414
+
static struct qcom_icc_bcm *nspa_noc_bcms[] = {
2415
+
&bcm_nsa0,
2416
+
&bcm_nsa1,
2417
+
};
2418
+
2419
+
static struct qcom_icc_node *nspa_noc_nodes[] = {
2420
+
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2421
+
[MASTER_CDSP_PROC] = &qxm_nsp,
2422
+
[SLAVE_HCP_A] = &qns_hcp,
2423
+
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2424
+
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2425
+
};
2426
+
2427
+
static const struct qcom_icc_desc sa8775p_nspa_noc = {
2428
+
.nodes = nspa_noc_nodes,
2429
+
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2430
+
.bcms = nspa_noc_bcms,
2431
+
.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2432
+
};
2433
+
2434
+
static struct qcom_icc_bcm *nspb_noc_bcms[] = {
2435
+
&bcm_nsb0,
2436
+
&bcm_nsb1,
2437
+
};
2438
+
2439
+
static struct qcom_icc_node *nspb_noc_nodes[] = {
2440
+
[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
2441
+
[MASTER_CDSP_PROC_B] = &qxm_nspb,
2442
+
[SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
2443
+
[SLAVE_HCP_B] = &qns_nspb_hcp,
2444
+
[SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
2445
+
};
2446
+
2447
+
static const struct qcom_icc_desc sa8775p_nspb_noc = {
2448
+
.nodes = nspb_noc_nodes,
2449
+
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
2450
+
.bcms = nspb_noc_bcms,
2451
+
.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
2452
+
};
2453
+
2454
+
static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
2455
+
&bcm_pci0,
2456
+
};
2457
+
2458
+
static struct qcom_icc_node *pcie_anoc_nodes[] = {
2459
+
[MASTER_PCIE_0] = &xm_pcie3_0,
2460
+
[MASTER_PCIE_1] = &xm_pcie3_1,
2461
+
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2462
+
};
2463
+
2464
+
static const struct qcom_icc_desc sa8775p_pcie_anoc = {
2465
+
.nodes = pcie_anoc_nodes,
2466
+
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2467
+
.bcms = pcie_anoc_bcms,
2468
+
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2469
+
};
2470
+
2471
+
static struct qcom_icc_bcm *system_noc_bcms[] = {
2472
+
&bcm_sn0,
2473
+
&bcm_sn1,
2474
+
&bcm_sn3,
2475
+
&bcm_sn4,
2476
+
&bcm_sn9,
2477
+
};
2478
+
2479
+
static struct qcom_icc_node *system_noc_nodes[] = {
2480
+
[MASTER_GIC_AHB] = &qhm_gic,
2481
+
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2482
+
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2483
+
[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2484
+
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2485
+
[MASTER_PIMEM] = &qxm_pimem,
2486
+
[MASTER_GIC] = &xm_gic,
2487
+
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2488
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2489
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
2490
+
};
2491
+
2492
+
static const struct qcom_icc_desc sa8775p_system_noc = {
2493
+
.nodes = system_noc_nodes,
2494
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
2495
+
.bcms = system_noc_bcms,
2496
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
2497
+
};
2498
+
2499
+
static const struct of_device_id qnoc_of_match[] = {
2500
+
{ .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, },
2501
+
{ .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, },
2502
+
{ .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, },
2503
+
{ .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, },
2504
+
{ .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, },
2505
+
{ .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, },
2506
+
{ .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, },
2507
+
{ .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, },
2508
+
{ .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, },
2509
+
{ .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, },
2510
+
{ .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, },
2511
+
{ .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, },
2512
+
{ .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, },
2513
+
{ .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, },
2514
+
{ }
2515
+
};
2516
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
2517
+
2518
+
static struct platform_driver qnoc_driver = {
2519
+
.probe = qcom_icc_rpmh_probe,
2520
+
.remove = qcom_icc_rpmh_remove,
2521
+
.driver = {
2522
+
.name = "qnoc-sa8775p",
2523
+
.of_match_table = qnoc_of_match,
2524
+
.sync_state = icc_sync_state,
2525
+
},
2526
+
};
2527
+
2528
+
static int __init qnoc_driver_init(void)
2529
+
{
2530
+
return platform_driver_register(&qnoc_driver);
2531
+
}
2532
+
core_initcall(qnoc_driver_init);
2533
+
2534
+
static void __exit qnoc_driver_exit(void)
2535
+
{
2536
+
platform_driver_unregister(&qnoc_driver);
2537
+
}
2538
+
module_exit(qnoc_driver_exit);
2539
+
2540
+
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver");
2541
+
MODULE_LICENSE("GPL");
+2
-2
drivers/interconnect/qcom/sc7180.h
+2
-2
drivers/interconnect/qcom/sc7180.h
···
11
11
#define SC7180_MASTER_APPSS_PROC 0
12
12
#define SC7180_MASTER_SYS_TCU 1
13
13
#define SC7180_MASTER_NPU_SYS 2
14
-
#define SC7180_MASTER_IPA_CORE 3
14
+
/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */
15
15
#define SC7180_MASTER_LLCC 4
16
16
#define SC7180_MASTER_A1NOC_CFG 5
17
17
#define SC7180_MASTER_A2NOC_CFG 6
···
58
58
#define SC7180_MASTER_USB3 47
59
59
#define SC7180_MASTER_EMMC 48
60
60
#define SC7180_SLAVE_EBI1 49
61
-
#define SC7180_SLAVE_IPA_CORE 50
61
+
/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
62
62
#define SC7180_SLAVE_A1NOC_CFG 51
63
63
#define SC7180_SLAVE_A2NOC_CFG 52
64
64
#define SC7180_SLAVE_AHB2PHY_SOUTH 53
-38
drivers/interconnect/qcom/sc8180x.c
-38
drivers/interconnect/qcom/sc8180x.c
···
469
469
.links = { SC8180X_SLAVE_LLCC }
470
470
};
471
471
472
-
static struct qcom_icc_node mas_ipa_core_master = {
473
-
.name = "mas_ipa_core_master",
474
-
.id = SC8180X_MASTER_IPA_CORE,
475
-
.channels = 1,
476
-
.buswidth = 8,
477
-
.num_links = 1,
478
-
.links = { SC8180X_SLAVE_IPA_CORE }
479
-
};
480
-
481
472
static struct qcom_icc_node mas_llcc_mc = {
482
473
.name = "mas_llcc_mc",
483
474
.id = SC8180X_MASTER_LLCC,
···
1192
1201
.buswidth = 4
1193
1202
};
1194
1203
1195
-
static struct qcom_icc_node slv_ipa_core_slave = {
1196
-
.name = "slv_ipa_core_slave",
1197
-
.id = SC8180X_SLAVE_IPA_CORE,
1198
-
.channels = 1,
1199
-
.buswidth = 8
1200
-
};
1201
-
1202
1204
static struct qcom_icc_node slv_ebi = {
1203
1205
.name = "slv_ebi",
1204
1206
.id = SC8180X_SLAVE_EBI_CH0,
···
1508
1524
.nodes = { &mas_qnm_npu }
1509
1525
};
1510
1526
1511
-
static struct qcom_icc_bcm bcm_ip0 = {
1512
-
.name = "IP0",
1513
-
.nodes = { &slv_ipa_core_slave }
1514
-
};
1515
-
1516
1527
static struct qcom_icc_bcm bcm_sn3 = {
1517
1528
.name = "SN3",
1518
1529
.keepalive = true,
···
1581
1602
&bcm_sh0,
1582
1603
&bcm_sh2,
1583
1604
&bcm_sh3,
1584
-
};
1585
-
1586
-
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
1587
-
&bcm_ip0,
1588
1605
};
1589
1606
1590
1607
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
···
1741
1766
[SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
1742
1767
};
1743
1768
1744
-
static struct qcom_icc_node * const ipa_virt_nodes[] = {
1745
-
[MASTER_IPA_CORE] = &mas_ipa_core_master,
1746
-
[SLAVE_IPA_CORE] = &slv_ipa_core_slave,
1747
-
};
1748
-
1749
1769
static struct qcom_icc_node * const mc_virt_nodes[] = {
1750
1770
[MASTER_LLCC] = &mas_llcc_mc,
1751
1771
[SLAVE_EBI_CH0] = &slv_ebi,
···
1827
1857
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1828
1858
};
1829
1859
1830
-
static const struct qcom_icc_desc sc8180x_ipa_virt = {
1831
-
.nodes = ipa_virt_nodes,
1832
-
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
1833
-
.bcms = ipa_virt_bcms,
1834
-
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
1835
-
};
1836
-
1837
1860
static const struct qcom_icc_desc sc8180x_mc_virt = {
1838
1861
.nodes = mc_virt_nodes,
1839
1862
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
···
1876
1913
{ .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
1877
1914
{ .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
1878
1915
{ .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
1879
-
{ .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt },
1880
1916
{ .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
1881
1917
{ .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
1882
1918
{ .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt },
+2
-2
drivers/interconnect/qcom/sc8180x.h
+2
-2
drivers/interconnect/qcom/sc8180x.h
···
51
51
#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
52
52
#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
53
53
#define SC8180X_MASTER_ECC 43
54
-
#define SC8180X_MASTER_IPA_CORE 44
54
+
/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */
55
55
#define SC8180X_MASTER_LLCC 45
56
56
#define SC8180X_MASTER_CNOC_MNOC_CFG 46
57
57
#define SC8180X_MASTER_CAMNOC_HF0 47
···
146
146
#define SC8180X_SLAVE_LLCC 136
147
147
#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
148
148
#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
149
-
#define SC8180X_SLAVE_IPA_CORE 139
149
+
/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
150
150
#define SC8180X_SLAVE_EBI_CH0 140
151
151
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
152
152
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
-25
drivers/interconnect/qcom/sc8280xp.c
-25
drivers/interconnect/qcom/sc8280xp.c
···
284
284
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
285
285
};
286
286
287
-
static struct qcom_icc_node ipa_core_master = {
288
-
.name = "ipa_core_master",
289
-
.id = SC8280XP_MASTER_IPA_CORE,
290
-
.channels = 1,
291
-
.buswidth = 8,
292
-
.num_links = 1,
293
-
.links = { SC8280XP_SLAVE_IPA_CORE },
294
-
};
295
-
296
287
static struct qcom_icc_node qup0_core_master = {
297
288
.name = "qup0_core_master",
298
289
.id = SC8280XP_MASTER_QUP_CORE_0,
···
871
880
.id = SC8280XP_SLAVE_SERVICE_A2NOC,
872
881
.channels = 1,
873
882
.buswidth = 4,
874
-
};
875
-
876
-
static struct qcom_icc_node ipa_core_slave = {
877
-
.name = "ipa_core_slave",
878
-
.id = SC8280XP_SLAVE_IPA_CORE,
879
-
.channels = 1,
880
-
.buswidth = 8,
881
883
};
882
884
883
885
static struct qcom_icc_node qup0_core_slave = {
···
1829
1845
},
1830
1846
};
1831
1847
1832
-
static struct qcom_icc_bcm bcm_ip0 = {
1833
-
.name = "IP0",
1834
-
.num_nodes = 1,
1835
-
.nodes = { &ipa_core_slave },
1836
-
};
1837
-
1838
1848
static struct qcom_icc_bcm bcm_mc0 = {
1839
1849
.name = "MC0",
1840
1850
.keepalive = true,
···
2055
2077
};
2056
2078
2057
2079
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
2058
-
&bcm_ip0,
2059
2080
&bcm_qup0,
2060
2081
&bcm_qup1,
2061
2082
&bcm_qup2,
2062
2083
};
2063
2084
2064
2085
static struct qcom_icc_node * const clk_virt_nodes[] = {
2065
-
[MASTER_IPA_CORE] = &ipa_core_master,
2066
2086
[MASTER_QUP_CORE_0] = &qup0_core_master,
2067
2087
[MASTER_QUP_CORE_1] = &qup1_core_master,
2068
2088
[MASTER_QUP_CORE_2] = &qup2_core_master,
2069
-
[SLAVE_IPA_CORE] = &ipa_core_slave,
2070
2089
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
2071
2090
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
2072
2091
[SLAVE_QUP_CORE_2] = &qup2_core_slave,
+2
-2
drivers/interconnect/qcom/sc8280xp.h
+2
-2
drivers/interconnect/qcom/sc8280xp.h
···
10
10
#define SC8280XP_MASTER_PCIE_TCU 1
11
11
#define SC8280XP_MASTER_SYS_TCU 2
12
12
#define SC8280XP_MASTER_APPSS_PROC 3
13
-
#define SC8280XP_MASTER_IPA_CORE 4
13
+
/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
14
14
#define SC8280XP_MASTER_LLCC 5
15
15
#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
16
16
#define SC8280XP_MASTER_CDSP_NOC_CFG 7
···
84
84
#define SC8280XP_MASTER_USB4_0 75
85
85
#define SC8280XP_MASTER_USB4_1 76
86
86
#define SC8280XP_SLAVE_EBI1 512
87
-
#define SC8280XP_SLAVE_IPA_CORE 513
87
+
/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
88
88
#define SC8280XP_SLAVE_AHB2PHY_0 514
89
89
#define SC8280XP_SLAVE_AHB2PHY_1 515
90
90
#define SC8280XP_SLAVE_AHB2PHY_2 516
+440
drivers/interconnect/qcom/sdm670.c
+440
drivers/interconnect/qcom/sdm670.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/device.h>
7
+
#include <linux/interconnect.h>
8
+
#include <linux/interconnect-provider.h>
9
+
#include <linux/module.h>
10
+
#include <linux/of_platform.h>
11
+
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
12
+
13
+
#include "bcm-voter.h"
14
+
#include "icc-rpmh.h"
15
+
#include "sdm670.h"
16
+
17
+
DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A1NOC);
18
+
DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC);
19
+
DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC);
20
+
DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
21
+
DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
22
+
DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
23
+
DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
24
+
DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A2NOC);
25
+
DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NOC_SNOC);
26
+
DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC);
27
+
DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
28
+
DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
29
+
DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
30
+
DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
31
+
DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
32
+
DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
33
+
DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
34
+
DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
35
+
DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC);
36
+
DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SOUTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670_SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DISPLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS, SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SDM670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAVE_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC_CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, SDM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM670_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM670_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG);
37
+
DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_NOC_CFG, SDM670_SLAVE_LLCC_CFG);
38
+
DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_GNOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC);
39
+
DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_GNOC);
40
+
DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0);
41
+
DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
42
+
DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG);
43
+
DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC);
44
+
DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC);
45
+
DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
46
+
DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAVE_LLCC);
47
+
DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC);
48
+
DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
49
+
DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MNOC);
50
+
DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
51
+
DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
52
+
DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
53
+
DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
54
+
DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
55
+
DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
56
+
DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
57
+
DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
58
+
DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_MNOC_SF_MEM_NOC);
59
+
DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_SNOC);
60
+
DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM);
61
+
DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM);
62
+
DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLAVE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM);
63
+
DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM);
64
+
DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC);
65
+
DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC);
66
+
DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER_A1NOC_SNOC);
67
+
DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4);
68
+
DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER_A2NOC_SNOC);
69
+
DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4);
70
+
DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32);
71
+
DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A1NOC_CFG);
72
+
DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A2NOC_CFG);
73
+
DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4);
74
+
DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4);
75
+
DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4);
76
+
DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4);
77
+
DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4);
78
+
DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4);
79
+
DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4);
80
+
DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_DC_NOC);
81
+
DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4);
82
+
DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4);
83
+
DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4);
84
+
DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4);
85
+
DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8);
86
+
DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4);
87
+
DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4);
88
+
DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER_CNOC_MNOC_CFG);
89
+
DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4);
90
+
DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4);
91
+
DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4);
92
+
DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4);
93
+
DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4);
94
+
DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4);
95
+
DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4);
96
+
DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4);
97
+
DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4);
98
+
DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC_CFG);
99
+
DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4);
100
+
DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4);
101
+
DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4);
102
+
DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4);
103
+
DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4);
104
+
DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4);
105
+
DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4);
106
+
DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4);
107
+
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4);
108
+
DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_CNOC_A2NOC);
109
+
DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4);
110
+
DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4);
111
+
DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM_NOC_CFG);
112
+
DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MASTER_GNOC_SNOC);
113
+
DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MASTER_GNOC_MEM_NOC);
114
+
DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4);
115
+
DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4);
116
+
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
117
+
DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32);
118
+
DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC);
119
+
DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MASTER_MEM_NOC_SNOC);
120
+
DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4);
121
+
DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MASTER_MNOC_SF_MEM_NOC);
122
+
DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_MASTER_MNOC_HF_MEM_NOC);
123
+
DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4);
124
+
DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8);
125
+
DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CNOC);
126
+
DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MASTER_SNOC_GC_MEM_NOC);
127
+
DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MASTER_SNOC_SF_MEM_NOC);
128
+
DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8);
129
+
DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8);
130
+
DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4);
131
+
DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4);
132
+
DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8);
133
+
134
+
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
135
+
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
136
+
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
137
+
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
138
+
DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
139
+
DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
140
+
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
141
+
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
142
+
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
143
+
DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
144
+
DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
145
+
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
146
+
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
147
+
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
148
+
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
149
+
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
150
+
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
151
+
DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
152
+
DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem);
153
+
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
154
+
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc);
155
+
DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc);
156
+
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic);
157
+
DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc);
158
+
159
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
160
+
&bcm_qup0,
161
+
&bcm_sn8,
162
+
};
163
+
164
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
165
+
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
166
+
[MASTER_BLSP_1] = &qhm_qup1,
167
+
[MASTER_TSIF] = &qhm_tsif,
168
+
[MASTER_EMMC] = &xm_emmc,
169
+
[MASTER_SDCC_2] = &xm_sdc2,
170
+
[MASTER_SDCC_4] = &xm_sdc4,
171
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
172
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
173
+
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
174
+
};
175
+
176
+
static const struct qcom_icc_desc sdm670_aggre1_noc = {
177
+
.nodes = aggre1_noc_nodes,
178
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
179
+
.bcms = aggre1_noc_bcms,
180
+
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
181
+
};
182
+
183
+
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
184
+
&bcm_ce0,
185
+
&bcm_qup0,
186
+
&bcm_sn10,
187
+
};
188
+
189
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
190
+
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
191
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
192
+
[MASTER_BLSP_2] = &qhm_qup2,
193
+
[MASTER_CNOC_A2NOC] = &qnm_cnoc,
194
+
[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
195
+
[MASTER_IPA] = &qxm_ipa,
196
+
[MASTER_QDSS_ETR] = &xm_qdss_etr,
197
+
[MASTER_USB3] = &xm_usb3_0,
198
+
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
199
+
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
200
+
};
201
+
202
+
static const struct qcom_icc_desc sdm670_aggre2_noc = {
203
+
.nodes = aggre2_noc_nodes,
204
+
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
205
+
.bcms = aggre2_noc_bcms,
206
+
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
207
+
};
208
+
209
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
210
+
&bcm_cn0,
211
+
};
212
+
213
+
static struct qcom_icc_node * const config_noc_nodes[] = {
214
+
[MASTER_SPDM] = &qhm_spdm,
215
+
[MASTER_SNOC_CNOC] = &qnm_snoc,
216
+
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
217
+
[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
218
+
[SLAVE_AOP] = &qhs_aop,
219
+
[SLAVE_AOSS] = &qhs_aoss,
220
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
221
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
222
+
[SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
223
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
224
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
225
+
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
226
+
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
227
+
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
228
+
[SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
229
+
[SLAVE_GLM] = &qhs_glm,
230
+
[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
231
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
232
+
[SLAVE_IPA_CFG] = &qhs_ipa,
233
+
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
234
+
[SLAVE_PDM] = &qhs_pdm,
235
+
[SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
236
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
237
+
[SLAVE_PRNG] = &qhs_prng,
238
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
239
+
[SLAVE_BLSP_2] = &qhs_qupv3_north,
240
+
[SLAVE_BLSP_1] = &qhs_qupv3_south,
241
+
[SLAVE_SDCC_2] = &qhs_sdc2,
242
+
[SLAVE_SDCC_4] = &qhs_sdc4,
243
+
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
244
+
[SLAVE_SPDM_WRAPPER] = &qhs_spdm,
245
+
[SLAVE_TCSR] = &qhs_tcsr,
246
+
[SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
247
+
[SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
248
+
[SLAVE_TSIF] = &qhs_tsif,
249
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
250
+
[SLAVE_USB3] = &qhs_usb3_0,
251
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
252
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
253
+
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
254
+
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
255
+
};
256
+
257
+
static const struct qcom_icc_desc sdm670_config_noc = {
258
+
.nodes = config_noc_nodes,
259
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
260
+
.bcms = config_noc_bcms,
261
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
262
+
};
263
+
264
+
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
265
+
};
266
+
267
+
static struct qcom_icc_node * const dc_noc_nodes[] = {
268
+
[MASTER_CNOC_DC_NOC] = &qhm_cnoc,
269
+
[SLAVE_LLCC_CFG] = &qhs_llcc,
270
+
[SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
271
+
};
272
+
273
+
static const struct qcom_icc_desc sdm670_dc_noc = {
274
+
.nodes = dc_noc_nodes,
275
+
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
276
+
.bcms = dc_noc_bcms,
277
+
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
278
+
};
279
+
280
+
static struct qcom_icc_bcm * const gladiator_noc_bcms[] = {
281
+
};
282
+
283
+
static struct qcom_icc_node * const gladiator_noc_nodes[] = {
284
+
[MASTER_AMPSS_M0] = &acm_l3,
285
+
[MASTER_GNOC_CFG] = &pm_gnoc_cfg,
286
+
[SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
287
+
[SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
288
+
[SLAVE_SERVICE_GNOC] = &srvc_gnoc,
289
+
};
290
+
291
+
static const struct qcom_icc_desc sdm670_gladiator_noc = {
292
+
.nodes = gladiator_noc_nodes,
293
+
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
294
+
.bcms = gladiator_noc_bcms,
295
+
.num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
296
+
};
297
+
298
+
static struct qcom_icc_bcm * const mem_noc_bcms[] = {
299
+
&bcm_acv,
300
+
&bcm_mc0,
301
+
&bcm_sh0,
302
+
&bcm_sh1,
303
+
&bcm_sh2,
304
+
&bcm_sh3,
305
+
&bcm_sh5,
306
+
};
307
+
308
+
static struct qcom_icc_node * const mem_noc_nodes[] = {
309
+
[MASTER_TCU_0] = &acm_tcu,
310
+
[MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
311
+
[MASTER_GNOC_MEM_NOC] = &qnm_apps,
312
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
313
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
314
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
315
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
316
+
[MASTER_GRAPHICS_3D] = &qxm_gpu,
317
+
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
318
+
[SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
319
+
[SLAVE_LLCC] = &qns_llcc,
320
+
[SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
321
+
[SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
322
+
[MASTER_LLCC] = &llcc_mc,
323
+
[SLAVE_EBI_CH0] = &ebi,
324
+
};
325
+
326
+
static const struct qcom_icc_desc sdm670_mem_noc = {
327
+
.nodes = mem_noc_nodes,
328
+
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
329
+
.bcms = mem_noc_bcms,
330
+
.num_bcms = ARRAY_SIZE(mem_noc_bcms),
331
+
};
332
+
333
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
334
+
&bcm_mm0,
335
+
&bcm_mm1,
336
+
&bcm_mm2,
337
+
&bcm_mm3,
338
+
};
339
+
340
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
341
+
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
342
+
[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
343
+
[MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
344
+
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
345
+
[MASTER_MDP_PORT0] = &qxm_mdp0,
346
+
[MASTER_MDP_PORT1] = &qxm_mdp1,
347
+
[MASTER_ROTATOR] = &qxm_rot,
348
+
[MASTER_VIDEO_P0] = &qxm_venus0,
349
+
[MASTER_VIDEO_P1] = &qxm_venus1,
350
+
[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
351
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
352
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
353
+
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
354
+
};
355
+
356
+
static const struct qcom_icc_desc sdm670_mmss_noc = {
357
+
.nodes = mmss_noc_nodes,
358
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
359
+
.bcms = mmss_noc_bcms,
360
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
361
+
};
362
+
363
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
364
+
&bcm_mm1,
365
+
&bcm_sn0,
366
+
&bcm_sn1,
367
+
&bcm_sn10,
368
+
&bcm_sn11,
369
+
&bcm_sn13,
370
+
&bcm_sn2,
371
+
&bcm_sn3,
372
+
&bcm_sn4,
373
+
&bcm_sn5,
374
+
&bcm_sn8,
375
+
};
376
+
377
+
static struct qcom_icc_node * const system_noc_nodes[] = {
378
+
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
379
+
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
380
+
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
381
+
[MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
382
+
[MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
383
+
[MASTER_PIMEM] = &qxm_pimem,
384
+
[MASTER_GIC] = &xm_gic,
385
+
[SLAVE_APPSS] = &qhs_apss,
386
+
[SLAVE_SNOC_CNOC] = &qns_cnoc,
387
+
[SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
388
+
[SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
389
+
[SLAVE_OCIMEM] = &qxs_imem,
390
+
[SLAVE_PIMEM] = &qxs_pimem,
391
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
392
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
393
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
394
+
[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
395
+
[MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
396
+
[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
397
+
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
398
+
};
399
+
400
+
static const struct qcom_icc_desc sdm670_system_noc = {
401
+
.nodes = system_noc_nodes,
402
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
403
+
.bcms = system_noc_bcms,
404
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
405
+
};
406
+
407
+
static const struct of_device_id qnoc_of_match[] = {
408
+
{ .compatible = "qcom,sdm670-aggre1-noc",
409
+
.data = &sdm670_aggre1_noc},
410
+
{ .compatible = "qcom,sdm670-aggre2-noc",
411
+
.data = &sdm670_aggre2_noc},
412
+
{ .compatible = "qcom,sdm670-config-noc",
413
+
.data = &sdm670_config_noc},
414
+
{ .compatible = "qcom,sdm670-dc-noc",
415
+
.data = &sdm670_dc_noc},
416
+
{ .compatible = "qcom,sdm670-gladiator-noc",
417
+
.data = &sdm670_gladiator_noc},
418
+
{ .compatible = "qcom,sdm670-mem-noc",
419
+
.data = &sdm670_mem_noc},
420
+
{ .compatible = "qcom,sdm670-mmss-noc",
421
+
.data = &sdm670_mmss_noc},
422
+
{ .compatible = "qcom,sdm670-system-noc",
423
+
.data = &sdm670_system_noc},
424
+
{ }
425
+
};
426
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
427
+
428
+
static struct platform_driver qnoc_driver = {
429
+
.probe = qcom_icc_rpmh_probe,
430
+
.remove = qcom_icc_rpmh_remove,
431
+
.driver = {
432
+
.name = "qnoc-sdm670",
433
+
.of_match_table = qnoc_of_match,
434
+
.sync_state = icc_sync_state,
435
+
},
436
+
};
437
+
module_platform_driver(qnoc_driver);
438
+
439
+
MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver");
440
+
MODULE_LICENSE("GPL");
+128
drivers/interconnect/qcom/sdm670.h
+128
drivers/interconnect/qcom/sdm670.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Qualcomm #define SDM670 interconnect IDs
4
+
*
5
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
6
+
*/
7
+
8
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H
9
+
#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H
10
+
11
+
#define SDM670_MASTER_A1NOC_CFG 0
12
+
#define SDM670_MASTER_A1NOC_SNOC 1
13
+
#define SDM670_MASTER_A2NOC_CFG 2
14
+
#define SDM670_MASTER_A2NOC_SNOC 3
15
+
#define SDM670_MASTER_AMPSS_M0 4
16
+
#define SDM670_MASTER_BLSP_1 5
17
+
#define SDM670_MASTER_BLSP_2 6
18
+
#define SDM670_MASTER_CAMNOC_HF0 7
19
+
#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8
20
+
#define SDM670_MASTER_CAMNOC_HF1 9
21
+
#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10
22
+
#define SDM670_MASTER_CAMNOC_SF 11
23
+
#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12
24
+
#define SDM670_MASTER_CNOC_A2NOC 13
25
+
#define SDM670_MASTER_CNOC_DC_NOC 14
26
+
#define SDM670_MASTER_CNOC_MNOC_CFG 15
27
+
#define SDM670_MASTER_CRYPTO_CORE_0 16
28
+
#define SDM670_MASTER_EMMC 17
29
+
#define SDM670_MASTER_GIC 18
30
+
#define SDM670_MASTER_GNOC_CFG 19
31
+
#define SDM670_MASTER_GNOC_MEM_NOC 20
32
+
#define SDM670_MASTER_GNOC_SNOC 21
33
+
#define SDM670_MASTER_GRAPHICS_3D 22
34
+
#define SDM670_MASTER_IPA 23
35
+
#define SDM670_MASTER_LLCC 24
36
+
#define SDM670_MASTER_MDP_PORT0 25
37
+
#define SDM670_MASTER_MDP_PORT1 26
38
+
#define SDM670_MASTER_MEM_NOC_CFG 27
39
+
#define SDM670_MASTER_MEM_NOC_SNOC 28
40
+
#define SDM670_MASTER_MNOC_HF_MEM_NOC 29
41
+
#define SDM670_MASTER_MNOC_SF_MEM_NOC 30
42
+
#define SDM670_MASTER_PIMEM 31
43
+
#define SDM670_MASTER_QDSS_BAM 32
44
+
#define SDM670_MASTER_QDSS_ETR 33
45
+
#define SDM670_MASTER_ROTATOR 34
46
+
#define SDM670_MASTER_SDCC_2 35
47
+
#define SDM670_MASTER_SDCC_4 36
48
+
#define SDM670_MASTER_SNOC_CFG 37
49
+
#define SDM670_MASTER_SNOC_CNOC 38
50
+
#define SDM670_MASTER_SNOC_GC_MEM_NOC 39
51
+
#define SDM670_MASTER_SNOC_SF_MEM_NOC 40
52
+
#define SDM670_MASTER_SPDM 41
53
+
#define SDM670_MASTER_TCU_0 42
54
+
#define SDM670_MASTER_TSIF 43
55
+
#define SDM670_MASTER_UFS_MEM 44
56
+
#define SDM670_MASTER_USB3 45
57
+
#define SDM670_MASTER_VIDEO_P0 46
58
+
#define SDM670_MASTER_VIDEO_P1 47
59
+
#define SDM670_MASTER_VIDEO_PROC 48
60
+
#define SDM670_SLAVE_A1NOC_CFG 49
61
+
#define SDM670_SLAVE_A1NOC_SNOC 50
62
+
#define SDM670_SLAVE_A2NOC_CFG 51
63
+
#define SDM670_SLAVE_A2NOC_SNOC 52
64
+
#define SDM670_SLAVE_AOP 53
65
+
#define SDM670_SLAVE_AOSS 54
66
+
#define SDM670_SLAVE_APPSS 55
67
+
#define SDM670_SLAVE_BLSP_1 56
68
+
#define SDM670_SLAVE_BLSP_2 57
69
+
#define SDM670_SLAVE_CAMERA_CFG 58
70
+
#define SDM670_SLAVE_CAMNOC_UNCOMP 59
71
+
#define SDM670_SLAVE_CDSP_CFG 60
72
+
#define SDM670_SLAVE_CLK_CTL 61
73
+
#define SDM670_SLAVE_CNOC_A2NOC 62
74
+
#define SDM670_SLAVE_CNOC_DDRSS 63
75
+
#define SDM670_SLAVE_CNOC_MNOC_CFG 64
76
+
#define SDM670_SLAVE_CRYPTO_0_CFG 65
77
+
#define SDM670_SLAVE_DCC_CFG 66
78
+
#define SDM670_SLAVE_DISPLAY_CFG 67
79
+
#define SDM670_SLAVE_EBI_CH0 68
80
+
#define SDM670_SLAVE_EMMC_CFG 69
81
+
#define SDM670_SLAVE_GLM 70
82
+
#define SDM670_SLAVE_GNOC_MEM_NOC 71
83
+
#define SDM670_SLAVE_GNOC_SNOC 72
84
+
#define SDM670_SLAVE_GRAPHICS_3D_CFG 73
85
+
#define SDM670_SLAVE_IMEM_CFG 74
86
+
#define SDM670_SLAVE_IPA_CFG 75
87
+
#define SDM670_SLAVE_LLCC 76
88
+
#define SDM670_SLAVE_LLCC_CFG 77
89
+
#define SDM670_SLAVE_MEM_NOC_CFG 78
90
+
#define SDM670_SLAVE_MEM_NOC_GNOC 79
91
+
#define SDM670_SLAVE_MEM_NOC_SNOC 80
92
+
#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81
93
+
#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82
94
+
#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83
95
+
#define SDM670_SLAVE_OCIMEM 84
96
+
#define SDM670_SLAVE_PDM 85
97
+
#define SDM670_SLAVE_PIMEM 86
98
+
#define SDM670_SLAVE_PIMEM_CFG 87
99
+
#define SDM670_SLAVE_PRNG 88
100
+
#define SDM670_SLAVE_QDSS_CFG 89
101
+
#define SDM670_SLAVE_QDSS_STM 90
102
+
#define SDM670_SLAVE_RBCPR_CX_CFG 91
103
+
#define SDM670_SLAVE_SDCC_2 92
104
+
#define SDM670_SLAVE_SDCC_4 93
105
+
#define SDM670_SLAVE_SERVICE_A1NOC 94
106
+
#define SDM670_SLAVE_SERVICE_A2NOC 95
107
+
#define SDM670_SLAVE_SERVICE_CNOC 96
108
+
#define SDM670_SLAVE_SERVICE_GNOC 97
109
+
#define SDM670_SLAVE_SERVICE_MEM_NOC 98
110
+
#define SDM670_SLAVE_SERVICE_MNOC 99
111
+
#define SDM670_SLAVE_SERVICE_SNOC 100
112
+
#define SDM670_SLAVE_SNOC_CFG 101
113
+
#define SDM670_SLAVE_SNOC_CNOC 102
114
+
#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103
115
+
#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104
116
+
#define SDM670_SLAVE_SOUTH_PHY_CFG 105
117
+
#define SDM670_SLAVE_SPDM_WRAPPER 106
118
+
#define SDM670_SLAVE_TCSR 107
119
+
#define SDM670_SLAVE_TCU 108
120
+
#define SDM670_SLAVE_TLMM_NORTH 109
121
+
#define SDM670_SLAVE_TLMM_SOUTH 110
122
+
#define SDM670_SLAVE_TSIF 111
123
+
#define SDM670_SLAVE_UFS_MEM_CFG 112
124
+
#define SDM670_SLAVE_USB3 113
125
+
#define SDM670_SLAVE_VENUS_CFG 114
126
+
#define SDM670_SLAVE_VSENSE_CTRL_CFG 115
127
+
128
+
#endif
+2
-2
drivers/interconnect/qcom/sdx55.h
+2
-2
drivers/interconnect/qcom/sdx55.h
···
6
6
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H
7
7
#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H
8
8
9
-
#define SDX55_MASTER_IPA_CORE 0
9
+
/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
10
10
#define SDX55_MASTER_LLCC 1
11
11
#define SDX55_MASTER_TCU_0 2
12
12
#define SDX55_MASTER_SNOC_GC_MEM_NOC 3
···
28
28
#define SDX55_MASTER_QDSS_ETR 19
29
29
#define SDX55_MASTER_SDCC_1 20
30
30
#define SDX55_MASTER_USB3 21
31
-
#define SDX55_SLAVE_IPA_CORE 22
31
+
/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
32
32
#define SDX55_SLAVE_EBI_CH0 23
33
33
#define SDX55_SLAVE_LLCC 24
34
34
#define SDX55_SLAVE_MEM_NOC_SNOC 25
-21
drivers/interconnect/qcom/sm8150.c
-21
drivers/interconnect/qcom/sm8150.c
···
56
56
DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
57
57
DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
58
58
DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
59
-
DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
60
59
DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
61
60
DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
62
61
DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
···
138
139
DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
139
140
DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
140
141
DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
141
-
DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
142
142
DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
143
143
DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
144
144
DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
···
170
172
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
171
173
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
172
174
DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
173
-
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
174
175
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
175
176
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
176
177
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
···
395
398
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
396
399
};
397
400
398
-
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
399
-
&bcm_ip0,
400
-
};
401
-
402
-
static struct qcom_icc_node * const ipa_virt_nodes[] = {
403
-
[MASTER_IPA_CORE] = &ipa_core_master,
404
-
[SLAVE_IPA_CORE] = &ipa_core_slave,
405
-
};
406
-
407
-
static const struct qcom_icc_desc sm8150_ipa_virt = {
408
-
.nodes = ipa_virt_nodes,
409
-
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
410
-
.bcms = ipa_virt_bcms,
411
-
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
412
-
};
413
-
414
401
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
415
402
&bcm_acv,
416
403
&bcm_mc0,
···
498
517
.data = &sm8150_dc_noc},
499
518
{ .compatible = "qcom,sm8150-gem-noc",
500
519
.data = &sm8150_gem_noc},
501
-
{ .compatible = "qcom,sm8150-ipa-virt",
502
-
.data = &sm8150_ipa_virt},
503
520
{ .compatible = "qcom,sm8150-mc-virt",
504
521
.data = &sm8150_mc_virt},
505
522
{ .compatible = "qcom,sm8150-mmss-noc",
+2
-2
drivers/interconnect/qcom/sm8150.h
+2
-2
drivers/interconnect/qcom/sm8150.h
···
35
35
#define SM8150_MASTER_GPU_TCU 24
36
36
#define SM8150_MASTER_GRAPHICS_3D 25
37
37
#define SM8150_MASTER_IPA 26
38
-
#define SM8150_MASTER_IPA_CORE 27
38
+
/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
39
39
#define SM8150_MASTER_LLCC 28
40
40
#define SM8150_MASTER_MDP_PORT0 29
41
41
#define SM8150_MASTER_MDP_PORT1 30
···
94
94
#define SM8150_SLAVE_GRAPHICS_3D_CFG 83
95
95
#define SM8150_SLAVE_IMEM_CFG 84
96
96
#define SM8150_SLAVE_IPA_CFG 85
97
-
#define SM8150_SLAVE_IPA_CORE 86
97
+
/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
98
98
#define SM8150_SLAVE_LLCC 87
99
99
#define SM8150_SLAVE_LLCC_CFG 88
100
100
#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89
-21
drivers/interconnect/qcom/sm8250.c
-21
drivers/interconnect/qcom/sm8250.c
···
51
51
DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
52
52
DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
53
53
DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
54
-
DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
55
54
DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
56
55
DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
57
56
DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
···
137
138
DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
138
139
DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
139
140
DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
140
-
DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
141
141
DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
142
142
DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
143
143
DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
···
169
171
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
170
172
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
171
173
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
172
-
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
173
174
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
174
175
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
175
176
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
···
383
386
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
384
387
};
385
388
386
-
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
387
-
&bcm_ip0,
388
-
};
389
-
390
-
static struct qcom_icc_node * const ipa_virt_nodes[] = {
391
-
[MASTER_IPA_CORE] = &ipa_core_master,
392
-
[SLAVE_IPA_CORE] = &ipa_core_slave,
393
-
};
394
-
395
-
static const struct qcom_icc_desc sm8250_ipa_virt = {
396
-
.nodes = ipa_virt_nodes,
397
-
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
398
-
.bcms = ipa_virt_bcms,
399
-
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
400
-
};
401
-
402
389
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
403
390
&bcm_acv,
404
391
&bcm_mc0,
···
512
531
.data = &sm8250_dc_noc},
513
532
{ .compatible = "qcom,sm8250-gem-noc",
514
533
.data = &sm8250_gem_noc},
515
-
{ .compatible = "qcom,sm8250-ipa-virt",
516
-
.data = &sm8250_ipa_virt},
517
534
{ .compatible = "qcom,sm8250-mc-virt",
518
535
.data = &sm8250_mc_virt},
519
536
{ .compatible = "qcom,sm8250-mmss-noc",
+2
-2
drivers/interconnect/qcom/sm8250.h
+2
-2
drivers/interconnect/qcom/sm8250.h
···
31
31
#define SM8250_MASTER_GPU_TCU 20
32
32
#define SM8250_MASTER_GRAPHICS_3D 21
33
33
#define SM8250_MASTER_IPA 22
34
-
#define SM8250_MASTER_IPA_CORE 23
34
+
/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */
35
35
#define SM8250_MASTER_LLCC 24
36
36
#define SM8250_MASTER_MDP_PORT0 25
37
37
#define SM8250_MASTER_MDP_PORT1 26
···
92
92
#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
93
93
#define SM8250_SLAVE_IMEM_CFG 82
94
94
#define SM8250_SLAVE_IPA_CFG 83
95
-
#define SM8250_SLAVE_IPA_CORE 84
95
+
/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
96
96
#define SM8250_SLAVE_IPC_ROUTER_CFG 85
97
97
#define SM8250_SLAVE_ISENSE_CFG 86
98
98
#define SM8250_SLAVE_LLCC 87
+1
-1
drivers/ipack/devices/ipoctal.c
+1
-1
drivers/ipack/devices/ipoctal.c
+20
drivers/misc/Kconfig
+20
drivers/misc/Kconfig
···
518
518
519
519
If you do not intend to run this kernel as a guest, say N.
520
520
521
+
config TMR_MANAGER
522
+
tristate "Select TMR Manager"
523
+
depends on MICROBLAZE && MB_MANAGER
524
+
help
525
+
This option enables the driver developed for TMR Manager.
526
+
The Triple Modular Redundancy(TMR) manager provides support for
527
+
fault detection.
528
+
529
+
Say N here unless you know what you are doing.
530
+
531
+
config TMR_INJECT
532
+
tristate "Select TMR Inject"
533
+
depends on TMR_MANAGER && FAULT_INJECTION_DEBUG_FS
534
+
help
535
+
This option enables the driver developed for TMR Inject.
536
+
The Triple Modular Redundancy(TMR) Inject provides
537
+
fault injection.
538
+
539
+
Say N here unless you know what you are doing.
540
+
521
541
source "drivers/misc/c2port/Kconfig"
522
542
source "drivers/misc/eeprom/Kconfig"
523
543
source "drivers/misc/cb710/Kconfig"
+2
drivers/misc/Makefile
+2
drivers/misc/Makefile
+2
-6
drivers/misc/eeprom/at25.c
+2
-6
drivers/misc/eeprom/at25.c
···
437
437
struct spi_eeprom *pdata;
438
438
bool is_fram;
439
439
440
-
err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25");
441
-
if (err >= 0)
442
-
is_fram = true;
443
-
else
444
-
is_fram = false;
445
-
446
440
/*
447
441
* Ping the chip ... the status register is pretty portable,
448
442
* unlike probing manufacturer IDs. We do expect that system
···
455
461
mutex_init(&at25->lock);
456
462
at25->spi = spi;
457
463
spi_set_drvdata(spi, at25);
464
+
465
+
is_fram = fwnode_device_is_compatible(dev_fwnode(&spi->dev), "cypress,fm25");
458
466
459
467
/* Chip description */
460
468
pdata = dev_get_platdata(&spi->dev);
+9
-1
drivers/misc/eeprom/idt_89hpesx.c
+9
-1
drivers/misc/eeprom/idt_89hpesx.c
···
1566
1566
*/
1567
1567
static int __init idt_init(void)
1568
1568
{
1569
+
int ret;
1570
+
1569
1571
/* Create Debugfs directory first */
1570
1572
if (debugfs_initialized())
1571
1573
csr_dbgdir = debugfs_create_dir("idt_csr", NULL);
1572
1574
1573
1575
/* Add new i2c-device driver */
1574
-
return i2c_add_driver(&idt_driver);
1576
+
ret = i2c_add_driver(&idt_driver);
1577
+
if (ret) {
1578
+
debugfs_remove_recursive(csr_dbgdir);
1579
+
return ret;
1580
+
}
1581
+
1582
+
return 0;
1575
1583
}
1576
1584
module_init(idt_init);
1577
1585
+1
-1
drivers/misc/enclosure.c
+1
-1
drivers/misc/enclosure.c
···
32
32
* found. @start can be used as a starting point to obtain multiple
33
33
* enclosures per parent (should begin with NULL and then be set to
34
34
* each returned enclosure device). Obtains a reference to the
35
-
* enclosure class device which must be released with device_put().
35
+
* enclosure class device which must be released with put_device().
36
36
* If @start is not NULL, a reference must be taken on it which is
37
37
* released before returning (this allows a loop through all
38
38
* enclosures to exit with only the reference on the enclosure of
+12
-1
drivers/misc/fastrpc.c
+12
-1
drivers/misc/fastrpc.c
···
2315
2315
data->domain_id = domain_id;
2316
2316
data->rpdev = rpdev;
2317
2317
2318
-
return of_platform_populate(rdev->of_node, NULL, NULL, rdev);
2318
+
err = of_platform_populate(rdev->of_node, NULL, NULL, rdev);
2319
+
if (err)
2320
+
goto populate_error;
2321
+
2322
+
return 0;
2323
+
2324
+
populate_error:
2325
+
if (data->fdevice)
2326
+
misc_deregister(&data->fdevice->miscdev);
2327
+
if (data->secure_fdevice)
2328
+
misc_deregister(&data->secure_fdevice->miscdev);
2329
+
2319
2330
fdev_error:
2320
2331
kfree(data);
2321
2332
return err;
+3
-3
drivers/misc/genwqe/card_utils.c
+3
-3
drivers/misc/genwqe/card_utils.c
···
151
151
return i;
152
152
}
153
153
154
+
#define CRC32_POLYNOMIAL 0x20044009
155
+
static u32 crc32_tab[256]; /* crc32 lookup table */
156
+
154
157
/**
155
158
* genwqe_init_crc32() - Prepare a lookup table for fast crc32 calculations
156
159
*
···
162
159
*
163
160
* Genwqe's Polynomial = 0x20044009
164
161
*/
165
-
#define CRC32_POLYNOMIAL 0x20044009
166
-
static u32 crc32_tab[256]; /* crc32 lookup table */
167
-
168
162
void genwqe_init_crc32(void)
169
163
{
170
164
int i, j;
+5
-5
drivers/misc/isl29003.c
+5
-5
drivers/misc/isl29003.c
···
186
186
{
187
187
struct i2c_client *client = to_i2c_client(dev);
188
188
189
-
return sprintf(buf, "%i\n", isl29003_get_range(client));
189
+
return sysfs_emit(buf, "%i\n", isl29003_get_range(client));
190
190
}
191
191
192
192
static ssize_t isl29003_store_range(struct device *dev,
···
222
222
{
223
223
struct i2c_client *client = to_i2c_client(dev);
224
224
225
-
return sprintf(buf, "%d\n", isl29003_get_resolution(client));
225
+
return sysfs_emit(buf, "%d\n", isl29003_get_resolution(client));
226
226
}
227
227
228
228
static ssize_t isl29003_store_resolution(struct device *dev,
···
256
256
{
257
257
struct i2c_client *client = to_i2c_client(dev);
258
258
259
-
return sprintf(buf, "%d\n", isl29003_get_mode(client));
259
+
return sysfs_emit(buf, "%d\n", isl29003_get_mode(client));
260
260
}
261
261
262
262
static ssize_t isl29003_store_mode(struct device *dev,
···
291
291
{
292
292
struct i2c_client *client = to_i2c_client(dev);
293
293
294
-
return sprintf(buf, "%d\n", isl29003_get_power_state(client));
294
+
return sysfs_emit(buf, "%d\n", isl29003_get_power_state(client));
295
295
}
296
296
297
297
static ssize_t isl29003_store_power_state(struct device *dev,
···
327
327
if (!isl29003_get_power_state(client))
328
328
return -EBUSY;
329
329
330
-
return sprintf(buf, "%d\n", isl29003_get_adc_value(client));
330
+
return sysfs_emit(buf, "%d\n", isl29003_get_adc_value(client));
331
331
}
332
332
333
333
static DEVICE_ATTR(lux, S_IRUGO, isl29003_show_lux, NULL);
+13
-13
drivers/misc/mei/bus-fixup.c
+13
-13
drivers/misc/mei/bus-fixup.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
-
* Copyright (c) 2013-2022, Intel Corporation. All rights reserved.
3
+
* Copyright (c) 2013-2023, Intel Corporation. All rights reserved.
4
4
* Intel Management Engine Interface (Intel MEI) Linux driver
5
5
*/
6
6
···
151
151
ret = __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0,
152
152
MEI_CL_IO_TX_BLOCKING);
153
153
if (ret < 0) {
154
-
dev_err(&cldev->dev, "Could not send ReqFWVersion cmd\n");
154
+
dev_info(&cldev->dev, "Could not send ReqFWVersion cmd ret = %d\n", ret);
155
155
return ret;
156
156
}
157
157
···
163
163
* Should be at least one version block,
164
164
* error out if nothing found
165
165
*/
166
-
dev_err(&cldev->dev, "Could not read FW version\n");
166
+
dev_info(&cldev->dev, "Could not read FW version ret = %d\n", bytes_recv);
167
167
return -EIO;
168
168
}
169
169
···
220
220
if (cldev->bus->fw_f_fw_ver_supported) {
221
221
ret = mei_fwver(cldev);
222
222
if (ret < 0)
223
-
dev_err(&cldev->dev, "FW version command failed %d\n",
224
-
ret);
223
+
dev_info(&cldev->dev, "FW version command failed %d\n",
224
+
ret);
225
225
}
226
226
227
227
if (cldev->bus->hbm_f_os_supported) {
228
228
ret = mei_osver(cldev);
229
229
if (ret < 0)
230
-
dev_err(&cldev->dev, "OS version command failed %d\n",
231
-
ret);
230
+
dev_info(&cldev->dev, "OS version command failed %d\n",
231
+
ret);
232
232
}
233
233
mei_cldev_disable(cldev);
234
234
}
···
247
247
248
248
ret = mei_fwver(cldev);
249
249
if (ret < 0)
250
-
dev_err(&cldev->dev, "FW version command failed %d\n", ret);
250
+
dev_info(&cldev->dev, "FW version command failed %d\n", ret);
251
251
mei_cldev_disable(cldev);
252
252
}
253
253
···
278
278
279
279
ret = mei_fwver(cldev);
280
280
if (ret < 0)
281
-
dev_err(&cldev->dev, "FW version command failed %d\n",
282
-
ret);
281
+
dev_info(&cldev->dev, "FW version command failed %d\n",
282
+
ret);
283
283
out:
284
284
mei_cldev_disable(cldev);
285
285
}
···
380
380
ret = __mei_cl_send(cl, (u8 *)&cmd, sizeof(cmd), 0,
381
381
MEI_CL_IO_TX_BLOCKING);
382
382
if (ret < 0) {
383
-
dev_err(bus->dev, "Could not send IF version cmd\n");
383
+
dev_err(bus->dev, "Could not send IF version cmd ret = %d\n", ret);
384
384
return ret;
385
385
}
386
386
···
395
395
bytes_recv = __mei_cl_recv(cl, (u8 *)reply, if_version_length, &vtag,
396
396
0, 0);
397
397
if (bytes_recv < 0 || (size_t)bytes_recv < if_version_length) {
398
-
dev_err(bus->dev, "Could not read IF version\n");
398
+
dev_err(bus->dev, "Could not read IF version ret = %d\n", bytes_recv);
399
399
ret = -EIO;
400
400
goto err;
401
401
}
···
403
403
memcpy(ver, reply->data, sizeof(*ver));
404
404
405
405
dev_info(bus->dev, "NFC MEI VERSION: IVN 0x%x Vendor ID 0x%x Type 0x%x\n",
406
-
ver->fw_ivn, ver->vendor_id, ver->radio_type);
406
+
ver->fw_ivn, ver->vendor_id, ver->radio_type);
407
407
408
408
err:
409
409
kfree(reply);
+2
-1
drivers/misc/mei/bus.c
+2
-1
drivers/misc/mei/bus.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
-
* Copyright (c) 2012-2019, Intel Corporation. All rights reserved.
3
+
* Copyright (c) 2012-2023, Intel Corporation. All rights reserved.
4
4
* Intel Management Engine Interface (Intel MEI) Linux driver
5
5
*/
6
6
···
1392
1392
*/
1393
1393
static void mei_cl_bus_dev_stop(struct mei_cl_device *cldev)
1394
1394
{
1395
+
cldev->do_match = 0;
1395
1396
if (cldev->is_added)
1396
1397
device_release_driver(&cldev->dev);
1397
1398
}
+2
-2
drivers/misc/mei/hdcp/mei_hdcp.c
+2
-2
drivers/misc/mei/hdcp/mei_hdcp.c
···
859
859
dev_warn(&cldev->dev, "mei_cldev_disable() failed\n");
860
860
}
861
861
862
-
#define MEI_UUID_HDCP GUID_INIT(0xB638AB7E, 0x94E2, 0x4EA2, 0xA5, \
863
-
0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
862
+
#define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, 0xA5, \
863
+
0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
864
864
865
865
static const struct mei_cl_device_id mei_hdcp_tbl[] = {
866
866
{ .uuid = MEI_UUID_HDCP, .version = MEI_CL_VERSION_ANY },
+5
drivers/misc/mei/mei_dev.h
+5
drivers/misc/mei/mei_dev.h
+2
-2
drivers/misc/mei/pxp/mei_pxp.c
+2
-2
drivers/misc/mei/pxp/mei_pxp.c
···
238
238
}
239
239
240
240
/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
241
-
#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
242
-
0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
241
+
#define MEI_GUID_PXP UUID_LE(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
242
+
0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
243
243
244
244
static struct mei_cl_device_id mei_pxp_tbl[] = {
245
245
{ .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+4
-4
drivers/misc/sgi-gru/grukservices.c
+4
-4
drivers/misc/sgi-gru/grukservices.c
···
425
425
static char *gru_get_cb_exception_detail_str(int ret, void *cb,
426
426
char *buf, int size)
427
427
{
428
-
struct gru_control_block_status *gen = (void *)cb;
428
+
struct gru_control_block_status *gen = cb;
429
429
struct control_block_extended_exc_detail excdet;
430
430
431
431
if (ret > 0 && gen->istatus == CBS_EXCEPTION) {
···
452
452
453
453
static int gru_retry_exception(void *cb)
454
454
{
455
-
struct gru_control_block_status *gen = (void *)cb;
455
+
struct gru_control_block_status *gen = cb;
456
456
struct control_block_extended_exc_detail excdet;
457
457
int retry = EXCEPTION_RETRY_LIMIT;
458
458
···
475
475
476
476
int gru_check_status_proc(void *cb)
477
477
{
478
-
struct gru_control_block_status *gen = (void *)cb;
478
+
struct gru_control_block_status *gen = cb;
479
479
int ret;
480
480
481
481
ret = gen->istatus;
···
488
488
489
489
int gru_wait_proc(void *cb)
490
490
{
491
-
struct gru_control_block_status *gen = (void *)cb;
491
+
struct gru_control_block_status *gen = cb;
492
492
int ret;
493
493
494
494
ret = gru_wait_idle_or_exception(gen);
+1
-1
drivers/misc/ti-st/st_core.c
+1
-1
drivers/misc/ti-st/st_core.c
+50
drivers/misc/uacce/uacce.c
+50
drivers/misc/uacce/uacce.c
···
363
363
uacce->qf_pg_num[UACCE_QFRT_DUS] << PAGE_SHIFT);
364
364
}
365
365
366
+
static ssize_t isolate_show(struct device *dev,
367
+
struct device_attribute *attr, char *buf)
368
+
{
369
+
struct uacce_device *uacce = to_uacce_device(dev);
370
+
371
+
return sysfs_emit(buf, "%d\n", uacce->ops->get_isolate_state(uacce));
372
+
}
373
+
374
+
static ssize_t isolate_strategy_show(struct device *dev, struct device_attribute *attr, char *buf)
375
+
{
376
+
struct uacce_device *uacce = to_uacce_device(dev);
377
+
u32 val;
378
+
379
+
val = uacce->ops->isolate_err_threshold_read(uacce);
380
+
381
+
return sysfs_emit(buf, "%u\n", val);
382
+
}
383
+
384
+
static ssize_t isolate_strategy_store(struct device *dev, struct device_attribute *attr,
385
+
const char *buf, size_t count)
386
+
{
387
+
struct uacce_device *uacce = to_uacce_device(dev);
388
+
unsigned long val;
389
+
int ret;
390
+
391
+
if (kstrtoul(buf, 0, &val) < 0)
392
+
return -EINVAL;
393
+
394
+
if (val > UACCE_MAX_ERR_THRESHOLD)
395
+
return -EINVAL;
396
+
397
+
ret = uacce->ops->isolate_err_threshold_write(uacce, val);
398
+
if (ret)
399
+
return ret;
400
+
401
+
return count;
402
+
}
403
+
366
404
static DEVICE_ATTR_RO(api);
367
405
static DEVICE_ATTR_RO(flags);
368
406
static DEVICE_ATTR_RO(available_instances);
369
407
static DEVICE_ATTR_RO(algorithms);
370
408
static DEVICE_ATTR_RO(region_mmio_size);
371
409
static DEVICE_ATTR_RO(region_dus_size);
410
+
static DEVICE_ATTR_RO(isolate);
411
+
static DEVICE_ATTR_RW(isolate_strategy);
372
412
373
413
static struct attribute *uacce_dev_attrs[] = {
374
414
&dev_attr_api.attr,
···
417
377
&dev_attr_algorithms.attr,
418
378
&dev_attr_region_mmio_size.attr,
419
379
&dev_attr_region_dus_size.attr,
380
+
&dev_attr_isolate.attr,
381
+
&dev_attr_isolate_strategy.attr,
420
382
NULL,
421
383
};
422
384
···
432
390
(!uacce->qf_pg_num[UACCE_QFRT_MMIO])) ||
433
391
((attr == &dev_attr_region_dus_size.attr) &&
434
392
(!uacce->qf_pg_num[UACCE_QFRT_DUS])))
393
+
return 0;
394
+
395
+
if (attr == &dev_attr_isolate_strategy.attr &&
396
+
(!uacce->ops->isolate_err_threshold_read &&
397
+
!uacce->ops->isolate_err_threshold_write))
398
+
return 0;
399
+
400
+
if (attr == &dev_attr_isolate.attr && !uacce->ops->get_isolate_state)
435
401
return 0;
436
402
437
403
return attr->mode;
+1
-1
drivers/misc/vmw_balloon.c
+1
-1
drivers/misc/vmw_balloon.c
···
1709
1709
static void __exit vmballoon_debugfs_exit(struct vmballoon *b)
1710
1710
{
1711
1711
static_key_disable(&balloon_stat_enabled.key);
1712
-
debugfs_remove(debugfs_lookup("vmmemctl", NULL));
1712
+
debugfs_lookup_and_remove("vmmemctl", NULL);
1713
1713
kfree(b->stats);
1714
1714
b->stats = NULL;
1715
1715
}
+2
drivers/misc/vmw_vmci/vmci_host.c
+2
drivers/misc/vmw_vmci/vmci_host.c
+171
drivers/misc/xilinx_tmr_inject.c
+171
drivers/misc/xilinx_tmr_inject.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Driver for Xilinx TMR Inject IP.
4
+
*
5
+
* Copyright (C) 2022 Advanced Micro Devices, Inc.
6
+
*
7
+
* Description:
8
+
* This driver is developed for TMR Inject IP,The Triple Modular Redundancy(TMR)
9
+
* Inject provides fault injection.
10
+
*/
11
+
12
+
#include <asm/xilinx_mb_manager.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/fault-inject.h>
16
+
17
+
/* TMR Inject Register offsets */
18
+
#define XTMR_INJECT_CR_OFFSET 0x0
19
+
#define XTMR_INJECT_AIR_OFFSET 0x4
20
+
#define XTMR_INJECT_IIR_OFFSET 0xC
21
+
#define XTMR_INJECT_EAIR_OFFSET 0x10
22
+
#define XTMR_INJECT_ERR_OFFSET 0x204
23
+
24
+
/* Register Bitmasks/shifts */
25
+
#define XTMR_INJECT_CR_CPUID_SHIFT 8
26
+
#define XTMR_INJECT_CR_IE_SHIFT 10
27
+
#define XTMR_INJECT_IIR_ADDR_MASK GENMASK(31, 16)
28
+
29
+
#define XTMR_INJECT_MAGIC_MAX_VAL 255
30
+
31
+
/**
32
+
* struct xtmr_inject_dev - Driver data for TMR Inject
33
+
* @regs: device physical base address
34
+
* @magic: Magic hardware configuration value
35
+
*/
36
+
struct xtmr_inject_dev {
37
+
void __iomem *regs;
38
+
u32 magic;
39
+
};
40
+
41
+
static DECLARE_FAULT_ATTR(inject_fault);
42
+
static char *inject_request;
43
+
module_param(inject_request, charp, 0);
44
+
MODULE_PARM_DESC(inject_request, "default fault injection attributes");
45
+
static struct dentry *dbgfs_root;
46
+
47
+
/* IO accessors */
48
+
static inline void xtmr_inject_write(struct xtmr_inject_dev *xtmr_inject,
49
+
u32 addr, u32 value)
50
+
{
51
+
iowrite32(value, xtmr_inject->regs + addr);
52
+
}
53
+
54
+
static inline u32 xtmr_inject_read(struct xtmr_inject_dev *xtmr_inject,
55
+
u32 addr)
56
+
{
57
+
return ioread32(xtmr_inject->regs + addr);
58
+
}
59
+
60
+
static int xtmr_inject_set(void *data, u64 val)
61
+
{
62
+
if (val != 1)
63
+
return -EINVAL;
64
+
65
+
xmb_inject_err();
66
+
return 0;
67
+
}
68
+
DEFINE_DEBUGFS_ATTRIBUTE(xtmr_inject_fops, NULL, xtmr_inject_set, "%llu\n");
69
+
70
+
static void xtmr_init_debugfs(struct xtmr_inject_dev *xtmr_inject)
71
+
{
72
+
struct dentry *dir;
73
+
74
+
dbgfs_root = debugfs_create_dir("xtmr_inject", NULL);
75
+
dir = fault_create_debugfs_attr("inject_fault", dbgfs_root,
76
+
&inject_fault);
77
+
debugfs_create_file("inject_fault", 0200, dir, NULL,
78
+
&xtmr_inject_fops);
79
+
}
80
+
81
+
static void xtmr_inject_init(struct xtmr_inject_dev *xtmr_inject)
82
+
{
83
+
u32 cr_val;
84
+
85
+
if (inject_request)
86
+
setup_fault_attr(&inject_fault, inject_request);
87
+
/* Allow fault injection */
88
+
cr_val = xtmr_inject->magic |
89
+
(1 << XTMR_INJECT_CR_IE_SHIFT) |
90
+
(1 << XTMR_INJECT_CR_CPUID_SHIFT);
91
+
xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET,
92
+
cr_val);
93
+
/* Initialize the address inject and instruction inject registers */
94
+
xtmr_inject_write(xtmr_inject, XTMR_INJECT_AIR_OFFSET,
95
+
XMB_INJECT_ERR_OFFSET);
96
+
xtmr_inject_write(xtmr_inject, XTMR_INJECT_IIR_OFFSET,
97
+
XMB_INJECT_ERR_OFFSET & XTMR_INJECT_IIR_ADDR_MASK);
98
+
}
99
+
100
+
/**
101
+
* xtmr_inject_probe - Driver probe function
102
+
* @pdev: Pointer to the platform_device structure
103
+
*
104
+
* This is the driver probe routine. It does all the memory
105
+
* allocation for the device.
106
+
*
107
+
* Return: 0 on success and failure value on error
108
+
*/
109
+
static int xtmr_inject_probe(struct platform_device *pdev)
110
+
{
111
+
struct xtmr_inject_dev *xtmr_inject;
112
+
int err;
113
+
114
+
xtmr_inject = devm_kzalloc(&pdev->dev, sizeof(*xtmr_inject),
115
+
GFP_KERNEL);
116
+
if (!xtmr_inject)
117
+
return -ENOMEM;
118
+
119
+
xtmr_inject->regs = devm_platform_ioremap_resource(pdev, 0);
120
+
if (IS_ERR(xtmr_inject->regs))
121
+
return PTR_ERR(xtmr_inject->regs);
122
+
123
+
err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic",
124
+
&xtmr_inject->magic);
125
+
if (err < 0) {
126
+
dev_err(&pdev->dev, "unable to read xlnx,magic property");
127
+
return err;
128
+
}
129
+
130
+
if (xtmr_inject->magic > XTMR_INJECT_MAGIC_MAX_VAL) {
131
+
dev_err(&pdev->dev, "invalid xlnx,magic property value");
132
+
return -EINVAL;
133
+
}
134
+
135
+
/* Initialize TMR Inject */
136
+
xtmr_inject_init(xtmr_inject);
137
+
138
+
xtmr_init_debugfs(xtmr_inject);
139
+
140
+
platform_set_drvdata(pdev, xtmr_inject);
141
+
142
+
return 0;
143
+
}
144
+
145
+
static int xtmr_inject_remove(struct platform_device *pdev)
146
+
{
147
+
debugfs_remove_recursive(dbgfs_root);
148
+
dbgfs_root = NULL;
149
+
return 0;
150
+
}
151
+
152
+
static const struct of_device_id xtmr_inject_of_match[] = {
153
+
{
154
+
.compatible = "xlnx,tmr-inject-1.0",
155
+
},
156
+
{ /* end of table */ }
157
+
};
158
+
MODULE_DEVICE_TABLE(of, xtmr_inject_of_match);
159
+
160
+
static struct platform_driver xtmr_inject_driver = {
161
+
.driver = {
162
+
.name = "xilinx-tmr_inject",
163
+
.of_match_table = xtmr_inject_of_match,
164
+
},
165
+
.probe = xtmr_inject_probe,
166
+
.remove = xtmr_inject_remove,
167
+
};
168
+
module_platform_driver(xtmr_inject_driver);
169
+
MODULE_AUTHOR("Advanced Micro Devices, Inc");
170
+
MODULE_DESCRIPTION("Xilinx TMR Inject Driver");
171
+
MODULE_LICENSE("GPL");
+220
drivers/misc/xilinx_tmr_manager.c
+220
drivers/misc/xilinx_tmr_manager.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Driver for Xilinx TMR Manager IP.
4
+
*
5
+
* Copyright (C) 2022 Advanced Micro Devices, Inc.
6
+
*
7
+
* Description:
8
+
* This driver is developed for TMR Manager,The Triple Modular Redundancy(TMR)
9
+
* Manager is responsible for handling the TMR subsystem state, including
10
+
* fault detection and error recovery. The core is triplicated in each of
11
+
* the sub-blocks in the TMR subsystem, and provides majority voting of
12
+
* its internal state provides soft error detection, correction and
13
+
* recovery.
14
+
*/
15
+
16
+
#include <asm/xilinx_mb_manager.h>
17
+
#include <linux/module.h>
18
+
#include <linux/of_device.h>
19
+
20
+
/* TMR Manager Register offsets */
21
+
#define XTMR_MANAGER_CR_OFFSET 0x0
22
+
#define XTMR_MANAGER_FFR_OFFSET 0x4
23
+
#define XTMR_MANAGER_CMR0_OFFSET 0x8
24
+
#define XTMR_MANAGER_CMR1_OFFSET 0xC
25
+
#define XTMR_MANAGER_BDIR_OFFSET 0x10
26
+
#define XTMR_MANAGER_SEMIMR_OFFSET 0x1C
27
+
28
+
/* Register Bitmasks/shifts */
29
+
#define XTMR_MANAGER_CR_MAGIC1_MASK GENMASK(7, 0)
30
+
#define XTMR_MANAGER_CR_MAGIC2_MASK GENMASK(15, 8)
31
+
#define XTMR_MANAGER_CR_RIR_MASK BIT(16)
32
+
#define XTMR_MANAGER_FFR_LM12_MASK BIT(0)
33
+
#define XTMR_MANAGER_FFR_LM13_MASK BIT(1)
34
+
#define XTMR_MANAGER_FFR_LM23_MASK BIT(2)
35
+
36
+
#define XTMR_MANAGER_CR_MAGIC2_SHIFT 4
37
+
#define XTMR_MANAGER_CR_RIR_SHIFT 16
38
+
#define XTMR_MANAGER_CR_BB_SHIFT 18
39
+
40
+
#define XTMR_MANAGER_MAGIC1_MAX_VAL 255
41
+
42
+
/**
43
+
* struct xtmr_manager_dev - Driver data for TMR Manager
44
+
* @regs: device physical base address
45
+
* @cr_val: control register value
46
+
* @magic1: Magic 1 hardware configuration value
47
+
* @err_cnt: error statistics count
48
+
* @phys_baseaddr: Physical base address
49
+
*/
50
+
struct xtmr_manager_dev {
51
+
void __iomem *regs;
52
+
u32 cr_val;
53
+
u32 magic1;
54
+
u32 err_cnt;
55
+
resource_size_t phys_baseaddr;
56
+
};
57
+
58
+
/* IO accessors */
59
+
static inline void xtmr_manager_write(struct xtmr_manager_dev *xtmr_manager,
60
+
u32 addr, u32 value)
61
+
{
62
+
iowrite32(value, xtmr_manager->regs + addr);
63
+
}
64
+
65
+
static inline u32 xtmr_manager_read(struct xtmr_manager_dev *xtmr_manager,
66
+
u32 addr)
67
+
{
68
+
return ioread32(xtmr_manager->regs + addr);
69
+
}
70
+
71
+
static void xmb_manager_reset_handler(struct xtmr_manager_dev *xtmr_manager)
72
+
{
73
+
/* Clear the FFR Register contents as a part of recovery process. */
74
+
xtmr_manager_write(xtmr_manager, XTMR_MANAGER_FFR_OFFSET, 0);
75
+
}
76
+
77
+
static void xmb_manager_update_errcnt(struct xtmr_manager_dev *xtmr_manager)
78
+
{
79
+
xtmr_manager->err_cnt++;
80
+
}
81
+
82
+
static ssize_t errcnt_show(struct device *dev, struct device_attribute *attr,
83
+
char *buf)
84
+
{
85
+
struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev);
86
+
87
+
return sysfs_emit(buf, "%x\n", xtmr_manager->err_cnt);
88
+
}
89
+
static DEVICE_ATTR_RO(errcnt);
90
+
91
+
static ssize_t dis_block_break_store(struct device *dev,
92
+
struct device_attribute *attr,
93
+
const char *buf, size_t size)
94
+
{
95
+
struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev);
96
+
int ret;
97
+
long value;
98
+
99
+
ret = kstrtoul(buf, 16, &value);
100
+
if (ret)
101
+
return ret;
102
+
103
+
/* unblock the break signal*/
104
+
xtmr_manager->cr_val &= ~(1 << XTMR_MANAGER_CR_BB_SHIFT);
105
+
xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET,
106
+
xtmr_manager->cr_val);
107
+
return size;
108
+
}
109
+
static DEVICE_ATTR_WO(dis_block_break);
110
+
111
+
static struct attribute *xtmr_manager_dev_attrs[] = {
112
+
&dev_attr_dis_block_break.attr,
113
+
&dev_attr_errcnt.attr,
114
+
NULL,
115
+
};
116
+
ATTRIBUTE_GROUPS(xtmr_manager_dev);
117
+
118
+
static void xtmr_manager_init(struct xtmr_manager_dev *xtmr_manager)
119
+
{
120
+
/* Clear the SEM interrupt mask register to disable the interrupt */
121
+
xtmr_manager_write(xtmr_manager, XTMR_MANAGER_SEMIMR_OFFSET, 0);
122
+
123
+
/* Allow recovery reset by default */
124
+
xtmr_manager->cr_val = (1 << XTMR_MANAGER_CR_RIR_SHIFT) |
125
+
xtmr_manager->magic1;
126
+
xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET,
127
+
xtmr_manager->cr_val);
128
+
/*
129
+
* Configure Break Delay Initialization Register to zero so that
130
+
* break occurs immediately
131
+
*/
132
+
xtmr_manager_write(xtmr_manager, XTMR_MANAGER_BDIR_OFFSET, 0);
133
+
134
+
/*
135
+
* To come out of break handler need to block the break signal
136
+
* in the tmr manager, update the xtmr_manager cr_val for the same
137
+
*/
138
+
xtmr_manager->cr_val |= (1 << XTMR_MANAGER_CR_BB_SHIFT);
139
+
140
+
/*
141
+
* When the break vector gets asserted because of error injection,
142
+
* the break signal must be blocked before exiting from the
143
+
* break handler, Below api updates the TMR manager address and
144
+
* control register and error counter callback arguments,
145
+
* which will be used by the break handler to block the
146
+
* break and call the callback function.
147
+
*/
148
+
xmb_manager_register(xtmr_manager->phys_baseaddr, xtmr_manager->cr_val,
149
+
(void *)xmb_manager_update_errcnt,
150
+
xtmr_manager, (void *)xmb_manager_reset_handler);
151
+
}
152
+
153
+
/**
154
+
* xtmr_manager_probe - Driver probe function
155
+
* @pdev: Pointer to the platform_device structure
156
+
*
157
+
* This is the driver probe routine. It does all the memory
158
+
* allocation for the device.
159
+
*
160
+
* Return: 0 on success and failure value on error
161
+
*/
162
+
static int xtmr_manager_probe(struct platform_device *pdev)
163
+
{
164
+
struct xtmr_manager_dev *xtmr_manager;
165
+
struct resource *res;
166
+
int err;
167
+
168
+
xtmr_manager = devm_kzalloc(&pdev->dev, sizeof(*xtmr_manager),
169
+
GFP_KERNEL);
170
+
if (!xtmr_manager)
171
+
return -ENOMEM;
172
+
173
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
174
+
xtmr_manager->regs = devm_ioremap_resource(&pdev->dev, res);
175
+
if (IS_ERR(xtmr_manager->regs))
176
+
return PTR_ERR(xtmr_manager->regs);
177
+
178
+
xtmr_manager->phys_baseaddr = res->start;
179
+
180
+
err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic1",
181
+
&xtmr_manager->magic1);
182
+
if (err < 0) {
183
+
dev_err(&pdev->dev, "unable to read xlnx,magic1 property");
184
+
return err;
185
+
}
186
+
187
+
if (xtmr_manager->magic1 > XTMR_MANAGER_MAGIC1_MAX_VAL) {
188
+
dev_err(&pdev->dev, "invalid xlnx,magic1 property value");
189
+
return -EINVAL;
190
+
}
191
+
192
+
/* Initialize TMR Manager */
193
+
xtmr_manager_init(xtmr_manager);
194
+
195
+
platform_set_drvdata(pdev, xtmr_manager);
196
+
197
+
return 0;
198
+
}
199
+
200
+
static const struct of_device_id xtmr_manager_of_match[] = {
201
+
{
202
+
.compatible = "xlnx,tmr-manager-1.0",
203
+
},
204
+
{ /* end of table */ }
205
+
};
206
+
MODULE_DEVICE_TABLE(of, xtmr_manager_of_match);
207
+
208
+
static struct platform_driver xtmr_manager_driver = {
209
+
.driver = {
210
+
.name = "xilinx-tmr_manager",
211
+
.of_match_table = xtmr_manager_of_match,
212
+
.dev_groups = xtmr_manager_dev_groups,
213
+
},
214
+
.probe = xtmr_manager_probe,
215
+
};
216
+
module_platform_driver(xtmr_manager_driver);
217
+
218
+
MODULE_AUTHOR("Advanced Micro Devices, Inc");
219
+
MODULE_DESCRIPTION("Xilinx TMR Manager Driver");
220
+
MODULE_LICENSE("GPL");
+1
-1
drivers/most/Kconfig
+1
-1
drivers/most/Kconfig
+3
-2
drivers/most/most_cdev.c
+3
-2
drivers/most/most_cdev.c
···
297
297
return mask;
298
298
}
299
299
300
-
/**
300
+
/*
301
301
* Initialization of struct file_operations
302
302
*/
303
303
static const struct file_operations channel_fops = {
···
404
404
* @channel_id: channel index/ID
405
405
* @cfg: pointer to actual channel configuration
406
406
* @name: name of the device to be created
407
+
* @args: pointer to array of component parameters (from configfs)
407
408
*
408
-
* This allocates achannel object and creates the device node in /dev
409
+
* This allocates a channel object and creates the device node in /dev
409
410
*
410
411
* Returns 0 on success or error code otherwise.
411
412
*/
+6
-4
drivers/most/most_snd.c
+6
-4
drivers/most/most_snd.c
···
27
27
/**
28
28
* struct channel - private structure to keep channel specific data
29
29
* @substream: stores the substream structure
30
+
* @pcm_hardware: low-level hardware description
30
31
* @iface: interface for which the channel belongs to
31
32
* @cfg: channel configuration
32
33
* @card: registered sound card
···
39
38
* @opened: set when the stream is opened
40
39
* @playback_task: playback thread
41
40
* @playback_waitq: waitq used by playback thread
41
+
* @copy_fn: copy function for PCM-specific format and width
42
42
*/
43
43
struct channel {
44
44
struct snd_pcm_substream *substream;
···
402
400
return channel->buffer_pos;
403
401
}
404
402
405
-
/**
403
+
/*
406
404
* Initialization of struct snd_pcm_ops
407
405
*/
408
406
static const struct snd_pcm_ops pcm_ops = {
···
503
501
* @iface: pointer to interface instance
504
502
* @channel_id: channel index/ID
505
503
* @cfg: pointer to actual channel configuration
506
-
* @arg_list: string that provides the name of the device to be created in /dev
507
-
* plus the desired audio resolution
504
+
* @device_name: name of the device to be created in /dev
505
+
* @arg_list: string that provides the desired audio resolution
508
506
*
509
507
* Creates sound card, pcm device, sets pcm ops and registers sound card.
510
508
*
···
701
699
return 0;
702
700
}
703
701
704
-
/**
702
+
/*
705
703
* Initialization of the struct most_component
706
704
*/
707
705
static struct most_component comp = {
+3
-3
drivers/most/most_usb.c
+3
-3
drivers/most/most_usb.c
···
660
660
661
661
/**
662
662
* link_stat_timer_handler - schedule work obtaining mac address and link status
663
-
* @data: pointer to USB device instance
663
+
* @t: pointer to timer_list which holds a pointer to the USB device instance
664
664
*
665
665
* The handler runs in interrupt context. That's why we need to defer the
666
666
* tasks to a work queue.
···
763
763
mutex_unlock(&mdev->io_mutex);
764
764
}
765
765
766
-
/**
766
+
/*
767
767
* hdm_usb_fops - file operation table for USB driver
768
768
*/
769
769
static const struct file_operations hdm_usb_fops = {
770
770
.owner = THIS_MODULE,
771
771
};
772
772
773
-
/**
773
+
/*
774
774
* usb_device_id - ID table for HCD device probing
775
775
*/
776
776
static const struct usb_device_id usbid[] = {
+10
drivers/nvmem/Kconfig
+10
drivers/nvmem/Kconfig
···
290
290
This driver can also be built as a module. If so, the module
291
291
will be called nvmem-sprd-efuse.
292
292
293
+
config NVMEM_STM32_BSEC_OPTEE_TA
294
+
def_bool NVMEM_STM32_ROMEM && OPTEE
295
+
help
296
+
Say y here to enable the accesses to STM32MP SoC OTPs by the OP-TEE
297
+
trusted application STM32MP BSEC.
298
+
299
+
This library is a used by stm32-romem driver or included in the module
300
+
called nvmem-stm32-romem.
301
+
293
302
config NVMEM_STM32_ROMEM
294
303
tristate "STMicroelectronics STM32 factory-programmed memory support"
295
304
depends on ARCH_STM32 || COMPILE_TEST
305
+
depends on OPTEE || !OPTEE
296
306
help
297
307
Say y here to enable read-only access for STMicroelectronics STM32
298
308
factory-programmed memory area.
+1
drivers/nvmem/Makefile
+1
drivers/nvmem/Makefile
···
61
61
nvmem_sprd_efuse-y := sprd-efuse.o
62
62
obj-$(CONFIG_NVMEM_STM32_ROMEM) += nvmem_stm32_romem.o
63
63
nvmem_stm32_romem-y := stm32-romem.o
64
+
nvmem_stm32_romem-$(CONFIG_NVMEM_STM32_BSEC_OPTEE_TA) += stm32-bsec-optee-ta.o
64
65
obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o
65
66
nvmem_sunplus_ocotp-y := sunplus-ocotp.o
66
67
obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o
+74
-71
drivers/nvmem/core.c
+74
-71
drivers/nvmem/core.c
···
60
60
struct nvmem_cell {
61
61
struct nvmem_cell_entry *entry;
62
62
const char *id;
63
+
int index;
63
64
};
64
65
65
66
static DEFINE_MUTEX(nvmem_mutex);
···
502
501
}
503
502
504
503
/**
504
+
* nvmem_add_one_cell() - Add one cell information to an nvmem device
505
+
*
506
+
* @nvmem: nvmem device to add cells to.
507
+
* @info: nvmem cell info to add to the device
508
+
*
509
+
* Return: 0 or negative error code on failure.
510
+
*/
511
+
int nvmem_add_one_cell(struct nvmem_device *nvmem,
512
+
const struct nvmem_cell_info *info)
513
+
{
514
+
struct nvmem_cell_entry *cell;
515
+
int rval;
516
+
517
+
cell = kzalloc(sizeof(*cell), GFP_KERNEL);
518
+
if (!cell)
519
+
return -ENOMEM;
520
+
521
+
rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, info, cell);
522
+
if (rval) {
523
+
kfree(cell);
524
+
return rval;
525
+
}
526
+
527
+
nvmem_cell_entry_add(cell);
528
+
529
+
return 0;
530
+
}
531
+
EXPORT_SYMBOL_GPL(nvmem_add_one_cell);
532
+
533
+
/**
505
534
* nvmem_add_cells() - Add cell information to an nvmem device
506
535
*
507
536
* @nvmem: nvmem device to add cells to.
···
544
513
const struct nvmem_cell_info *info,
545
514
int ncells)
546
515
{
547
-
struct nvmem_cell_entry **cells;
548
516
int i, rval;
549
517
550
-
cells = kcalloc(ncells, sizeof(*cells), GFP_KERNEL);
551
-
if (!cells)
552
-
return -ENOMEM;
553
-
554
518
for (i = 0; i < ncells; i++) {
555
-
cells[i] = kzalloc(sizeof(**cells), GFP_KERNEL);
556
-
if (!cells[i]) {
557
-
rval = -ENOMEM;
558
-
goto err;
559
-
}
560
-
561
-
rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, &info[i], cells[i]);
562
-
if (rval) {
563
-
kfree(cells[i]);
564
-
goto err;
565
-
}
566
-
567
-
nvmem_cell_entry_add(cells[i]);
519
+
rval = nvmem_add_one_cell(nvmem, &info[i]);
520
+
if (rval)
521
+
return rval;
568
522
}
569
523
570
-
/* remove tmp array */
571
-
kfree(cells);
572
-
573
524
return 0;
574
-
err:
575
-
while (i--)
576
-
nvmem_cell_entry_drop(cells[i]);
577
-
578
-
kfree(cells);
579
-
580
-
return rval;
581
525
}
582
526
583
527
/**
···
688
682
689
683
static int nvmem_add_cells_from_of(struct nvmem_device *nvmem)
690
684
{
691
-
struct device_node *parent, *child;
692
685
struct device *dev = &nvmem->dev;
693
-
struct nvmem_cell_entry *cell;
686
+
struct device_node *child;
694
687
const __be32 *addr;
695
-
int len;
688
+
int len, ret;
696
689
697
-
parent = dev->of_node;
690
+
for_each_child_of_node(dev->of_node, child) {
691
+
struct nvmem_cell_info info = {0};
698
692
699
-
for_each_child_of_node(parent, child) {
700
693
addr = of_get_property(child, "reg", &len);
701
694
if (!addr)
702
695
continue;
···
705
700
return -EINVAL;
706
701
}
707
702
708
-
cell = kzalloc(sizeof(*cell), GFP_KERNEL);
709
-
if (!cell) {
710
-
of_node_put(child);
711
-
return -ENOMEM;
712
-
}
713
-
714
-
cell->nvmem = nvmem;
715
-
cell->offset = be32_to_cpup(addr++);
716
-
cell->bytes = be32_to_cpup(addr);
717
-
cell->name = kasprintf(GFP_KERNEL, "%pOFn", child);
703
+
info.offset = be32_to_cpup(addr++);
704
+
info.bytes = be32_to_cpup(addr);
705
+
info.name = kasprintf(GFP_KERNEL, "%pOFn", child);
718
706
719
707
addr = of_get_property(child, "bits", &len);
720
708
if (addr && len == (2 * sizeof(u32))) {
721
-
cell->bit_offset = be32_to_cpup(addr++);
722
-
cell->nbits = be32_to_cpup(addr);
709
+
info.bit_offset = be32_to_cpup(addr++);
710
+
info.nbits = be32_to_cpup(addr);
723
711
}
724
712
725
-
if (cell->nbits)
726
-
cell->bytes = DIV_ROUND_UP(
727
-
cell->nbits + cell->bit_offset,
728
-
BITS_PER_BYTE);
713
+
info.np = of_node_get(child);
729
714
730
-
if (!IS_ALIGNED(cell->offset, nvmem->stride)) {
731
-
dev_err(dev, "cell %s unaligned to nvmem stride %d\n",
732
-
cell->name, nvmem->stride);
733
-
/* Cells already added will be freed later. */
734
-
kfree_const(cell->name);
735
-
kfree(cell);
715
+
ret = nvmem_add_one_cell(nvmem, &info);
716
+
kfree(info.name);
717
+
if (ret) {
736
718
of_node_put(child);
737
-
return -EINVAL;
719
+
return ret;
738
720
}
739
-
740
-
cell->np = of_node_get(child);
741
-
nvmem_cell_entry_add(cell);
742
721
}
743
722
744
723
return 0;
···
753
764
if (!nvmem)
754
765
return ERR_PTR(-ENOMEM);
755
766
756
-
rval = ida_alloc(&nvmem_ida, GFP_KERNEL);
767
+
rval = ida_alloc(&nvmem_ida, GFP_KERNEL);
757
768
if (rval < 0) {
758
769
kfree(nvmem);
759
770
return ERR_PTR(rval);
···
1111
1122
}
1112
1123
EXPORT_SYMBOL_GPL(devm_nvmem_device_get);
1113
1124
1114
-
static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry, const char *id)
1125
+
static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry,
1126
+
const char *id, int index)
1115
1127
{
1116
1128
struct nvmem_cell *cell;
1117
1129
const char *name = NULL;
···
1131
1141
1132
1142
cell->id = name;
1133
1143
cell->entry = entry;
1144
+
cell->index = index;
1134
1145
1135
1146
return cell;
1136
1147
}
···
1170
1179
__nvmem_device_put(nvmem);
1171
1180
cell = ERR_PTR(-ENOENT);
1172
1181
} else {
1173
-
cell = nvmem_create_cell(cell_entry, con_id);
1182
+
cell = nvmem_create_cell(cell_entry, con_id, 0);
1174
1183
if (IS_ERR(cell))
1175
1184
__nvmem_device_put(nvmem);
1176
1185
}
···
1218
1227
struct nvmem_device *nvmem;
1219
1228
struct nvmem_cell_entry *cell_entry;
1220
1229
struct nvmem_cell *cell;
1230
+
struct of_phandle_args cell_spec;
1221
1231
int index = 0;
1232
+
int cell_index = 0;
1233
+
int ret;
1222
1234
1223
1235
/* if cell name exists, find index to the name */
1224
1236
if (id)
1225
1237
index = of_property_match_string(np, "nvmem-cell-names", id);
1226
1238
1227
-
cell_np = of_parse_phandle(np, "nvmem-cells", index);
1228
-
if (!cell_np)
1229
-
return ERR_PTR(-ENOENT);
1239
+
ret = of_parse_phandle_with_optional_args(np, "nvmem-cells",
1240
+
"#nvmem-cell-cells",
1241
+
index, &cell_spec);
1242
+
if (ret)
1243
+
return ERR_PTR(ret);
1244
+
1245
+
if (cell_spec.args_count > 1)
1246
+
return ERR_PTR(-EINVAL);
1247
+
1248
+
cell_np = cell_spec.np;
1249
+
if (cell_spec.args_count)
1250
+
cell_index = cell_spec.args[0];
1230
1251
1231
1252
nvmem_np = of_get_parent(cell_np);
1232
1253
if (!nvmem_np) {
···
1260
1257
return ERR_PTR(-ENOENT);
1261
1258
}
1262
1259
1263
-
cell = nvmem_create_cell(cell_entry, id);
1260
+
cell = nvmem_create_cell(cell_entry, id, cell_index);
1264
1261
if (IS_ERR(cell))
1265
1262
__nvmem_device_put(nvmem);
1266
1263
···
1413
1410
}
1414
1411
1415
1412
static int __nvmem_cell_read(struct nvmem_device *nvmem,
1416
-
struct nvmem_cell_entry *cell,
1417
-
void *buf, size_t *len, const char *id)
1413
+
struct nvmem_cell_entry *cell,
1414
+
void *buf, size_t *len, const char *id, int index)
1418
1415
{
1419
1416
int rc;
1420
1417
···
1428
1425
nvmem_shift_read_buffer_in_place(cell, buf);
1429
1426
1430
1427
if (nvmem->cell_post_process) {
1431
-
rc = nvmem->cell_post_process(nvmem->priv, id,
1428
+
rc = nvmem->cell_post_process(nvmem->priv, id, index,
1432
1429
cell->offset, buf, cell->bytes);
1433
1430
if (rc)
1434
1431
return rc;
···
1463
1460
if (!buf)
1464
1461
return ERR_PTR(-ENOMEM);
1465
1462
1466
-
rc = __nvmem_cell_read(nvmem, cell->entry, buf, len, cell->id);
1463
+
rc = __nvmem_cell_read(nvmem, cell->entry, buf, len, cell->id, cell->index);
1467
1464
if (rc) {
1468
1465
kfree(buf);
1469
1466
return ERR_PTR(rc);
···
1776
1773
if (rc)
1777
1774
return rc;
1778
1775
1779
-
rc = __nvmem_cell_read(nvmem, &cell, buf, &len, NULL);
1776
+
rc = __nvmem_cell_read(nvmem, &cell, buf, &len, NULL, 0);
1780
1777
if (rc)
1781
1778
return rc;
1782
1779
+2
-2
drivers/nvmem/imx-ocotp.c
+2
-2
drivers/nvmem/imx-ocotp.c
···
222
222
return ret;
223
223
}
224
224
225
-
static int imx_ocotp_cell_pp(void *context, const char *id, unsigned int offset,
226
-
void *data, size_t bytes)
225
+
static int imx_ocotp_cell_pp(void *context, const char *id, int index,
226
+
unsigned int offset, void *data, size_t bytes)
227
227
{
228
228
struct ocotp_priv *priv = context;
229
229
+1
-12
drivers/nvmem/qcom-spmi-sdam.c
+1
-12
drivers/nvmem/qcom-spmi-sdam.c
···
175
175
},
176
176
.probe = sdam_probe,
177
177
};
178
-
179
-
static int __init sdam_init(void)
180
-
{
181
-
return platform_driver_register(&sdam_driver);
182
-
}
183
-
subsys_initcall(sdam_init);
184
-
185
-
static void __exit sdam_exit(void)
186
-
{
187
-
return platform_driver_unregister(&sdam_driver);
188
-
}
189
-
module_exit(sdam_exit);
178
+
module_platform_driver(sdam_driver);
190
179
191
180
MODULE_DESCRIPTION("QCOM SPMI SDAM driver");
192
181
MODULE_LICENSE("GPL v2");
+1
-1
drivers/nvmem/rave-sp-eeprom.c
+1
-1
drivers/nvmem/rave-sp-eeprom.c
+298
drivers/nvmem/stm32-bsec-optee-ta.c
+298
drivers/nvmem/stm32-bsec-optee-ta.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver
4
+
*
5
+
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
6
+
*/
7
+
8
+
#include <linux/tee_drv.h>
9
+
10
+
#include "stm32-bsec-optee-ta.h"
11
+
12
+
/*
13
+
* Read OTP memory
14
+
*
15
+
* [in] value[0].a OTP start offset in byte
16
+
* [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock)
17
+
* [out] memref[1].buffer Output buffer to store read values
18
+
* [out] memref[1].size Size of OTP to be read
19
+
*
20
+
* Return codes:
21
+
* TEE_SUCCESS - Invoke command success
22
+
* TEE_ERROR_BAD_PARAMETERS - Incorrect input param
23
+
* TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
24
+
*/
25
+
#define PTA_BSEC_READ_MEM 0x0
26
+
27
+
/*
28
+
* Write OTP memory
29
+
*
30
+
* [in] value[0].a OTP start offset in byte
31
+
* [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock)
32
+
* [in] memref[1].buffer Input buffer to read values
33
+
* [in] memref[1].size Size of OTP to be written
34
+
*
35
+
* Return codes:
36
+
* TEE_SUCCESS - Invoke command success
37
+
* TEE_ERROR_BAD_PARAMETERS - Incorrect input param
38
+
* TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
39
+
*/
40
+
#define PTA_BSEC_WRITE_MEM 0x1
41
+
42
+
/* value of PTA_BSEC access type = value[in] b */
43
+
#define SHADOW_ACCESS 0
44
+
#define FUSE_ACCESS 1
45
+
#define LOCK_ACCESS 2
46
+
47
+
/* Bitfield definition for LOCK status */
48
+
#define LOCK_PERM BIT(30)
49
+
50
+
/* OP-TEE STM32MP BSEC TA UUID */
51
+
static const uuid_t stm32mp_bsec_ta_uuid =
52
+
UUID_INIT(0x94cf71ad, 0x80e6, 0x40b5,
53
+
0xa7, 0xc6, 0x3d, 0xc5, 0x01, 0xeb, 0x28, 0x03);
54
+
55
+
/*
56
+
* Check whether this driver supports the BSEC TA in the TEE instance
57
+
* represented by the params (ver/data) to this function.
58
+
*/
59
+
static int stm32_bsec_optee_ta_match(struct tee_ioctl_version_data *ver,
60
+
const void *data)
61
+
{
62
+
/* Currently this driver only supports GP compliant, OP-TEE based TA */
63
+
if ((ver->impl_id == TEE_IMPL_ID_OPTEE) &&
64
+
(ver->gen_caps & TEE_GEN_CAP_GP))
65
+
return 1;
66
+
else
67
+
return 0;
68
+
}
69
+
70
+
/* Open a session to OP-TEE for STM32MP BSEC TA */
71
+
static int stm32_bsec_ta_open_session(struct tee_context *ctx, u32 *id)
72
+
{
73
+
struct tee_ioctl_open_session_arg sess_arg;
74
+
int rc;
75
+
76
+
memset(&sess_arg, 0, sizeof(sess_arg));
77
+
export_uuid(sess_arg.uuid, &stm32mp_bsec_ta_uuid);
78
+
sess_arg.clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL;
79
+
sess_arg.num_params = 0;
80
+
81
+
rc = tee_client_open_session(ctx, &sess_arg, NULL);
82
+
if ((rc < 0) || (sess_arg.ret != 0)) {
83
+
pr_err("%s: tee_client_open_session failed err:%#x, ret:%#x\n",
84
+
__func__, sess_arg.ret, rc);
85
+
if (!rc)
86
+
rc = -EINVAL;
87
+
} else {
88
+
*id = sess_arg.session;
89
+
}
90
+
91
+
return rc;
92
+
}
93
+
94
+
/* close a session to OP-TEE for STM32MP BSEC TA */
95
+
static void stm32_bsec_ta_close_session(void *ctx, u32 id)
96
+
{
97
+
tee_client_close_session(ctx, id);
98
+
}
99
+
100
+
/* stm32_bsec_optee_ta_open() - initialize the STM32MP BSEC TA */
101
+
int stm32_bsec_optee_ta_open(struct tee_context **ctx)
102
+
{
103
+
struct tee_context *tee_ctx;
104
+
u32 session_id;
105
+
int rc;
106
+
107
+
/* Open context with TEE driver */
108
+
tee_ctx = tee_client_open_context(NULL, stm32_bsec_optee_ta_match, NULL, NULL);
109
+
if (IS_ERR(tee_ctx)) {
110
+
rc = PTR_ERR(tee_ctx);
111
+
if (rc == -ENOENT)
112
+
return -EPROBE_DEFER;
113
+
pr_err("%s: tee_client_open_context failed (%d)\n", __func__, rc);
114
+
115
+
return rc;
116
+
}
117
+
118
+
/* Check STM32MP BSEC TA presence */
119
+
rc = stm32_bsec_ta_open_session(tee_ctx, &session_id);
120
+
if (rc) {
121
+
tee_client_close_context(tee_ctx);
122
+
return rc;
123
+
}
124
+
125
+
stm32_bsec_ta_close_session(tee_ctx, session_id);
126
+
127
+
*ctx = tee_ctx;
128
+
129
+
return 0;
130
+
}
131
+
132
+
/* stm32_bsec_optee_ta_open() - release the PTA STM32MP BSEC TA */
133
+
void stm32_bsec_optee_ta_close(void *ctx)
134
+
{
135
+
tee_client_close_context(ctx);
136
+
}
137
+
138
+
/* stm32_bsec_optee_ta_read() - nvmem read access using PTA client driver */
139
+
int stm32_bsec_optee_ta_read(struct tee_context *ctx, unsigned int offset,
140
+
void *buf, size_t bytes)
141
+
{
142
+
struct tee_shm *shm;
143
+
struct tee_ioctl_invoke_arg arg;
144
+
struct tee_param param[2];
145
+
u8 *shm_buf;
146
+
u32 start, num_bytes;
147
+
int ret;
148
+
u32 session_id;
149
+
150
+
ret = stm32_bsec_ta_open_session(ctx, &session_id);
151
+
if (ret)
152
+
return ret;
153
+
154
+
memset(&arg, 0, sizeof(arg));
155
+
memset(¶m, 0, sizeof(param));
156
+
157
+
arg.func = PTA_BSEC_READ_MEM;
158
+
arg.session = session_id;
159
+
arg.num_params = 2;
160
+
161
+
/* align access on 32bits */
162
+
start = ALIGN_DOWN(offset, 4);
163
+
num_bytes = round_up(offset + bytes - start, 4);
164
+
param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT;
165
+
param[0].u.value.a = start;
166
+
param[0].u.value.b = SHADOW_ACCESS;
167
+
168
+
shm = tee_shm_alloc_kernel_buf(ctx, num_bytes);
169
+
if (IS_ERR(shm)) {
170
+
ret = PTR_ERR(shm);
171
+
goto out_tee_session;
172
+
}
173
+
174
+
param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
175
+
param[1].u.memref.shm = shm;
176
+
param[1].u.memref.size = num_bytes;
177
+
178
+
ret = tee_client_invoke_func(ctx, &arg, param);
179
+
if (ret < 0 || arg.ret != 0) {
180
+
pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n",
181
+
arg.ret, ret);
182
+
if (!ret)
183
+
ret = -EIO;
184
+
}
185
+
if (!ret) {
186
+
shm_buf = tee_shm_get_va(shm, 0);
187
+
if (IS_ERR(shm_buf)) {
188
+
ret = PTR_ERR(shm_buf);
189
+
pr_err("tee_shm_get_va failed for transmit (%d)\n", ret);
190
+
} else {
191
+
/* read data from 32 bits aligned buffer */
192
+
memcpy(buf, &shm_buf[offset % 4], bytes);
193
+
}
194
+
}
195
+
196
+
tee_shm_free(shm);
197
+
198
+
out_tee_session:
199
+
stm32_bsec_ta_close_session(ctx, session_id);
200
+
201
+
return ret;
202
+
}
203
+
204
+
/* stm32_bsec_optee_ta_write() - nvmem write access using PTA client driver */
205
+
int stm32_bsec_optee_ta_write(struct tee_context *ctx, unsigned int lower,
206
+
unsigned int offset, void *buf, size_t bytes)
207
+
{ struct tee_shm *shm;
208
+
struct tee_ioctl_invoke_arg arg;
209
+
struct tee_param param[2];
210
+
u8 *shm_buf;
211
+
int ret;
212
+
u32 session_id;
213
+
214
+
ret = stm32_bsec_ta_open_session(ctx, &session_id);
215
+
if (ret)
216
+
return ret;
217
+
218
+
/* Allow only writing complete 32-bits aligned words */
219
+
if ((bytes % 4) || (offset % 4))
220
+
return -EINVAL;
221
+
222
+
memset(&arg, 0, sizeof(arg));
223
+
memset(¶m, 0, sizeof(param));
224
+
225
+
arg.func = PTA_BSEC_WRITE_MEM;
226
+
arg.session = session_id;
227
+
arg.num_params = 2;
228
+
229
+
param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT;
230
+
param[0].u.value.a = offset;
231
+
param[0].u.value.b = FUSE_ACCESS;
232
+
233
+
shm = tee_shm_alloc_kernel_buf(ctx, bytes);
234
+
if (IS_ERR(shm)) {
235
+
ret = PTR_ERR(shm);
236
+
goto out_tee_session;
237
+
}
238
+
239
+
param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT;
240
+
param[1].u.memref.shm = shm;
241
+
param[1].u.memref.size = bytes;
242
+
243
+
shm_buf = tee_shm_get_va(shm, 0);
244
+
if (IS_ERR(shm_buf)) {
245
+
ret = PTR_ERR(shm_buf);
246
+
pr_err("tee_shm_get_va failed for transmit (%d)\n", ret);
247
+
tee_shm_free(shm);
248
+
249
+
goto out_tee_session;
250
+
}
251
+
252
+
memcpy(shm_buf, buf, bytes);
253
+
254
+
ret = tee_client_invoke_func(ctx, &arg, param);
255
+
if (ret < 0 || arg.ret != 0) {
256
+
pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", arg.ret, ret);
257
+
if (!ret)
258
+
ret = -EIO;
259
+
}
260
+
pr_debug("Write OTPs %d to %zu, ret=%d\n", offset / 4, (offset + bytes) / 4, ret);
261
+
262
+
/* Lock the upper OTPs with ECC protection, word programming only */
263
+
if (!ret && ((offset + bytes) >= (lower * 4))) {
264
+
u32 start, nb_lock;
265
+
u32 *lock = (u32 *)shm_buf;
266
+
int i;
267
+
268
+
/*
269
+
* don't lock the lower OTPs, no ECC protection and incremental
270
+
* bit programming, a second write is allowed
271
+
*/
272
+
start = max_t(u32, offset, lower * 4);
273
+
nb_lock = (offset + bytes - start) / 4;
274
+
275
+
param[0].u.value.a = start;
276
+
param[0].u.value.b = LOCK_ACCESS;
277
+
param[1].u.memref.size = nb_lock * 4;
278
+
279
+
for (i = 0; i < nb_lock; i++)
280
+
lock[i] = LOCK_PERM;
281
+
282
+
ret = tee_client_invoke_func(ctx, &arg, param);
283
+
if (ret < 0 || arg.ret != 0) {
284
+
pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", arg.ret, ret);
285
+
if (!ret)
286
+
ret = -EIO;
287
+
}
288
+
pr_debug("Lock upper OTPs %d to %d, ret=%d\n",
289
+
start / 4, start / 4 + nb_lock, ret);
290
+
}
291
+
292
+
tee_shm_free(shm);
293
+
294
+
out_tee_session:
295
+
stm32_bsec_ta_close_session(ctx, session_id);
296
+
297
+
return ret;
298
+
}
+80
drivers/nvmem/stm32-bsec-optee-ta.h
+80
drivers/nvmem/stm32-bsec-optee-ta.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver
4
+
*
5
+
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
6
+
*/
7
+
8
+
#if IS_ENABLED(CONFIG_NVMEM_STM32_BSEC_OPTEE_TA)
9
+
/**
10
+
* stm32_bsec_optee_ta_open() - initialize the STM32 BSEC TA
11
+
* @ctx: the OP-TEE context on success
12
+
*
13
+
* Return:
14
+
* On success, 0. On failure, -errno.
15
+
*/
16
+
int stm32_bsec_optee_ta_open(struct tee_context **ctx);
17
+
18
+
/**
19
+
* stm32_bsec_optee_ta_close() - release the STM32 BSEC TA
20
+
* @ctx: the OP-TEE context
21
+
*
22
+
* This function used to clean the OP-TEE resources initialized in
23
+
* stm32_bsec_optee_ta_open(); it can be used as callback to
24
+
* devm_add_action_or_reset()
25
+
*/
26
+
void stm32_bsec_optee_ta_close(void *ctx);
27
+
28
+
/**
29
+
* stm32_bsec_optee_ta_read() - nvmem read access using TA client driver
30
+
* @ctx: the OP-TEE context provided by stm32_bsec_optee_ta_open
31
+
* @offset: nvmem offset
32
+
* @buf: buffer to fill with nvem values
33
+
* @bytes: number of bytes to read
34
+
*
35
+
* Return:
36
+
* On success, 0. On failure, -errno.
37
+
*/
38
+
int stm32_bsec_optee_ta_read(struct tee_context *ctx, unsigned int offset,
39
+
void *buf, size_t bytes);
40
+
41
+
/**
42
+
* stm32_bsec_optee_ta_write() - nvmem write access using TA client driver
43
+
* @ctx: the OP-TEE context provided by stm32_bsec_optee_ta_open
44
+
* @lower: number of lower OTP, not protected by ECC
45
+
* @offset: nvmem offset
46
+
* @buf: buffer with nvem values
47
+
* @bytes: number of bytes to write
48
+
*
49
+
* Return:
50
+
* On success, 0. On failure, -errno.
51
+
*/
52
+
int stm32_bsec_optee_ta_write(struct tee_context *ctx, unsigned int lower,
53
+
unsigned int offset, void *buf, size_t bytes);
54
+
55
+
#else
56
+
57
+
static inline int stm32_bsec_optee_ta_open(struct tee_context **ctx)
58
+
{
59
+
return -EOPNOTSUPP;
60
+
}
61
+
62
+
static inline void stm32_bsec_optee_ta_close(void *ctx)
63
+
{
64
+
}
65
+
66
+
static inline int stm32_bsec_optee_ta_read(struct tee_context *ctx,
67
+
unsigned int offset, void *buf,
68
+
size_t bytes)
69
+
{
70
+
return -EOPNOTSUPP;
71
+
}
72
+
73
+
static inline int stm32_bsec_optee_ta_write(struct tee_context *ctx,
74
+
unsigned int lower,
75
+
unsigned int offset, void *buf,
76
+
size_t bytes)
77
+
{
78
+
return -EOPNOTSUPP;
79
+
}
80
+
#endif /* CONFIG_NVMEM_STM32_BSEC_OPTEE_TA */
+81
-3
drivers/nvmem/stm32-romem.c
+81
-3
drivers/nvmem/stm32-romem.c
···
11
11
#include <linux/module.h>
12
12
#include <linux/nvmem-provider.h>
13
13
#include <linux/of_device.h>
14
+
#include <linux/tee_drv.h>
15
+
16
+
#include "stm32-bsec-optee-ta.h"
14
17
15
18
/* BSEC secure service access from non-secure */
16
19
#define STM32_SMC_BSEC 0x82001003
···
28
25
struct stm32_romem_cfg {
29
26
int size;
30
27
u8 lower;
28
+
bool ta;
31
29
};
32
30
33
31
struct stm32_romem_priv {
34
32
void __iomem *base;
35
33
struct nvmem_config cfg;
36
34
u8 lower;
35
+
struct tee_context *ctx;
37
36
};
38
37
39
38
static int stm32_romem_read(void *context, unsigned int offset, void *buf,
···
143
138
return 0;
144
139
}
145
140
141
+
static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf,
142
+
size_t bytes)
143
+
{
144
+
struct stm32_romem_priv *priv = context;
145
+
146
+
return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);
147
+
}
148
+
149
+
static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf,
150
+
size_t bytes)
151
+
{
152
+
struct stm32_romem_priv *priv = context;
153
+
154
+
return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);
155
+
}
156
+
157
+
static bool stm32_bsec_smc_check(void)
158
+
{
159
+
u32 val;
160
+
int ret;
161
+
162
+
/* check that the OP-TEE support the BSEC SMC (legacy mode) */
163
+
ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val);
164
+
165
+
return !ret;
166
+
}
167
+
168
+
static bool optee_presence_check(void)
169
+
{
170
+
struct device_node *np;
171
+
bool tee_detected = false;
172
+
173
+
/* check that the OP-TEE node is present and available. */
174
+
np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
175
+
if (np && of_device_is_available(np))
176
+
tee_detected = true;
177
+
of_node_put(np);
178
+
179
+
return tee_detected;
180
+
}
181
+
146
182
static int stm32_romem_probe(struct platform_device *pdev)
147
183
{
148
184
const struct stm32_romem_cfg *cfg;
149
185
struct device *dev = &pdev->dev;
150
186
struct stm32_romem_priv *priv;
151
187
struct resource *res;
188
+
int rc;
152
189
153
190
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
154
191
if (!priv)
···
220
173
} else {
221
174
priv->cfg.size = cfg->size;
222
175
priv->lower = cfg->lower;
223
-
priv->cfg.reg_read = stm32_bsec_read;
224
-
priv->cfg.reg_write = stm32_bsec_write;
176
+
if (cfg->ta || optee_presence_check()) {
177
+
rc = stm32_bsec_optee_ta_open(&priv->ctx);
178
+
if (rc) {
179
+
/* wait for OP-TEE client driver to be up and ready */
180
+
if (rc == -EPROBE_DEFER)
181
+
return -EPROBE_DEFER;
182
+
/* BSEC PTA is required or SMC not supported */
183
+
if (cfg->ta || !stm32_bsec_smc_check())
184
+
return rc;
185
+
}
186
+
}
187
+
if (priv->ctx) {
188
+
rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);
189
+
if (rc) {
190
+
dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc);
191
+
return rc;
192
+
}
193
+
priv->cfg.reg_read = stm32_bsec_pta_read;
194
+
priv->cfg.reg_write = stm32_bsec_pta_write;
195
+
} else {
196
+
priv->cfg.reg_read = stm32_bsec_read;
197
+
priv->cfg.reg_write = stm32_bsec_write;
198
+
}
225
199
}
226
200
227
201
return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
228
202
}
229
203
230
204
/*
231
-
* STM32MP15 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
205
+
* STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
232
206
* => 96 x 32-bits data words
233
207
* - Lower: 1K bits, 2:1 redundancy, incremental bit programming
234
208
* => 32 (x 32-bits) lower shadow registers = words 0 to 31
···
259
191
static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
260
192
.size = 384,
261
193
.lower = 32,
194
+
.ta = false,
195
+
};
196
+
197
+
static const struct stm32_romem_cfg stm32mp13_bsec_cfg = {
198
+
.size = 384,
199
+
.lower = 32,
200
+
.ta = true,
262
201
};
263
202
264
203
static const struct of_device_id stm32_romem_of_match[] = {
···
273
198
.compatible = "st,stm32mp15-bsec",
274
199
.data = (void *)&stm32mp15_bsec_cfg,
275
200
}, {
201
+
.compatible = "st,stm32mp13-bsec",
202
+
.data = (void *)&stm32mp13_bsec_cfg,
276
203
},
204
+
{ /* sentinel */ },
277
205
};
278
206
MODULE_DEVICE_TABLE(of, stm32_romem_of_match);
279
207
+1
-7
drivers/nvmem/sunxi_sid.c
+1
-7
drivers/nvmem/sunxi_sid.c
···
197
197
.need_register_readout = true,
198
198
};
199
199
200
-
static const struct sunxi_sid_cfg sun20i_d1_cfg = {
201
-
.value_offset = 0x200,
202
-
.size = 0x100,
203
-
};
204
-
205
200
static const struct sunxi_sid_cfg sun50i_a64_cfg = {
206
201
.value_offset = 0x200,
207
202
.size = 0x100,
208
-
.need_register_readout = true,
209
203
};
210
204
211
205
static const struct sunxi_sid_cfg sun50i_h6_cfg = {
···
212
218
{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
213
219
{ .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
214
220
{ .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
215
-
{ .compatible = "allwinner,sun20i-d1-sid", .data = &sun20i_d1_cfg },
221
+
{ .compatible = "allwinner,sun20i-d1-sid", .data = &sun50i_a64_cfg },
216
222
{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
217
223
{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
218
224
{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
+3
-3
drivers/of/property.c
+3
-3
drivers/of/property.c
···
1202
1202
if (strcmp(prop_name, list_name))
1203
1203
return NULL;
1204
1204
1205
-
if (of_parse_phandle_with_args(np, list_name, cells_name, index,
1206
-
&sup_args))
1205
+
if (__of_parse_phandle_with_args(np, list_name, cells_name, 0, index,
1206
+
&sup_args))
1207
1207
return NULL;
1208
1208
1209
1209
return sup_args.np;
···
1307
1307
DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells")
1308
1308
DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells")
1309
1309
DEFINE_SIMPLE_PROP(extcon, "extcon", NULL)
1310
-
DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", NULL)
1310
+
DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", "#nvmem-cell-cells")
1311
1311
DEFINE_SIMPLE_PROP(phys, "phys", "#phy-cells")
1312
1312
DEFINE_SIMPLE_PROP(wakeup_parent, "wakeup-parent", NULL)
1313
1313
DEFINE_SIMPLE_PROP(pinctrl0, "pinctrl-0", NULL)
+88
-41
drivers/parport/parport_pc.c
+88
-41
drivers/parport/parport_pc.c
···
106
106
static void frob_econtrol(struct parport *pb, unsigned char m,
107
107
unsigned char v)
108
108
{
109
+
const struct parport_pc_private *priv = pb->physport->private_data;
110
+
unsigned char ecr_writable = priv->ecr_writable;
109
111
unsigned char ectr = 0;
112
+
unsigned char new;
110
113
111
114
if (m != 0xff)
112
115
ectr = inb(ECONTROL(pb));
113
116
114
-
pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n",
115
-
m, v, ectr, (ectr & ~m) ^ v);
117
+
new = (ectr & ~m) ^ v;
118
+
if (ecr_writable)
119
+
/* All known users of the ECR mask require bit 0 to be set. */
120
+
new = (new & ecr_writable) | 1;
116
121
117
-
outb((ectr & ~m) ^ v, ECONTROL(pb));
122
+
pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", m, v, ectr, new);
123
+
124
+
outb(new, ECONTROL(pb));
118
125
}
119
126
120
127
static inline void frob_set_mode(struct parport *p, int mode)
···
1486
1479
struct parport_pc_private *priv = pb->private_data;
1487
1480
unsigned char r = 0xc;
1488
1481
1489
-
outb(r, CONTROL(pb));
1490
-
if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1491
-
outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1482
+
if (!priv->ecr_writable) {
1483
+
outb(r, CONTROL(pb));
1484
+
if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1485
+
outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1492
1486
1493
-
r = inb(CONTROL(pb));
1494
-
if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1495
-
goto no_reg; /* Sure that no ECR register exists */
1487
+
r = inb(CONTROL(pb));
1488
+
if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1489
+
/* Sure that no ECR register exists */
1490
+
goto no_reg;
1491
+
}
1492
+
1493
+
if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1494
+
goto no_reg;
1495
+
1496
+
ECR_WRITE(pb, 0x34);
1497
+
if (inb(ECONTROL(pb)) != 0x35)
1498
+
goto no_reg;
1496
1499
}
1497
-
1498
-
if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1499
-
goto no_reg;
1500
-
1501
-
ECR_WRITE(pb, 0x34);
1502
-
if (inb(ECONTROL(pb)) != 0x35)
1503
-
goto no_reg;
1504
1500
1505
1501
priv->ecr = 1;
1506
1502
outb(0xc, CONTROL(pb));
···
2010
2000
static LIST_HEAD(ports_list);
2011
2001
static DEFINE_SPINLOCK(ports_lock);
2012
2002
2013
-
struct parport *parport_pc_probe_port(unsigned long int base,
2014
-
unsigned long int base_hi,
2015
-
int irq, int dma,
2016
-
struct device *dev,
2017
-
int irqflags)
2003
+
static struct parport *__parport_pc_probe_port(unsigned long int base,
2004
+
unsigned long int base_hi,
2005
+
int irq, int dma,
2006
+
struct device *dev,
2007
+
int irqflags,
2008
+
unsigned int mode_mask,
2009
+
unsigned char ecr_writable)
2018
2010
{
2019
2011
struct parport_pc_private *priv;
2020
2012
struct parport_operations *ops;
···
2065
2053
priv->ctr = 0xc;
2066
2054
priv->ctr_writable = ~0x10;
2067
2055
priv->ecr = 0;
2056
+
priv->ecr_writable = ecr_writable;
2068
2057
priv->fifo_depth = 0;
2069
2058
priv->dma_buf = NULL;
2070
2059
priv->dma_handle = 0;
···
2129
2116
p->dma != PARPORT_DMA_NOFIFO &&
2130
2117
priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2131
2118
p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2132
-
p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2133
-
#ifdef CONFIG_PARPORT_1284
2134
-
p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2135
-
/* currently broken, but working on it.. (FB) */
2136
-
/* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2137
-
#endif /* IEEE 1284 support */
2138
-
if (p->dma != PARPORT_DMA_NONE) {
2139
-
pr_cont(", dma %d", p->dma);
2119
+
if (p->dma != PARPORT_DMA_NONE)
2140
2120
p->modes |= PARPORT_MODE_DMA;
2141
-
} else
2142
-
pr_cont(", using FIFO");
2143
2121
} else
2144
2122
/* We can't use the DMA channel after all. */
2145
2123
p->dma = PARPORT_DMA_NONE;
2124
+
#endif /* Allowed to use FIFO/DMA */
2125
+
2126
+
p->modes &= ~mode_mask;
2127
+
2128
+
#ifdef CONFIG_PARPORT_PC_FIFO
2129
+
if ((p->modes & PARPORT_MODE_COMPAT) != 0)
2130
+
p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2131
+
#ifdef CONFIG_PARPORT_1284
2132
+
if ((p->modes & PARPORT_MODE_ECP) != 0)
2133
+
p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2134
+
#endif
2135
+
if ((p->modes & (PARPORT_MODE_ECP | PARPORT_MODE_COMPAT)) != 0) {
2136
+
if ((p->modes & PARPORT_MODE_DMA) != 0)
2137
+
pr_cont(", dma %d", p->dma);
2138
+
else
2139
+
pr_cont(", using FIFO");
2140
+
}
2146
2141
#endif /* Allowed to use FIFO/DMA */
2147
2142
2148
2143
pr_cont(" [");
···
2259
2238
if (pdev)
2260
2239
platform_device_unregister(pdev);
2261
2240
return NULL;
2241
+
}
2242
+
2243
+
struct parport *parport_pc_probe_port(unsigned long int base,
2244
+
unsigned long int base_hi,
2245
+
int irq, int dma,
2246
+
struct device *dev,
2247
+
int irqflags)
2248
+
{
2249
+
return __parport_pc_probe_port(base, base_hi, irq, dma,
2250
+
dev, irqflags, 0, 0);
2262
2251
}
2263
2252
EXPORT_SYMBOL(parport_pc_probe_port);
2264
2253
···
2657
2626
int lo;
2658
2627
int hi;
2659
2628
/* -1 if not there, >6 for offset-method (max BAR is 6) */
2660
-
} addr[4];
2629
+
} addr[2];
2630
+
2631
+
/* Bit field of parport modes to exclude. */
2632
+
unsigned int mode_mask;
2633
+
2634
+
/* If non-zero, sets the bitmask of writable ECR bits. In that
2635
+
* case additionally bit 0 will be forcibly set on writes. */
2636
+
unsigned char ecr_writable;
2661
2637
2662
2638
/* If set, this is called immediately after pci_enable_device.
2663
2639
* If it returns non-zero, no probing will take place and the
···
2696
2658
/* titan_010l */ { 1, { { 3, -1 }, } },
2697
2659
/* avlab_1p */ { 1, { { 0, 1}, } },
2698
2660
/* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2699
-
/* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2700
-
* and 840 locks up if you write 1 to bit 2! */
2701
-
/* oxsemi_952 */ { 1, { { 0, 1 }, } },
2702
-
/* oxsemi_954 */ { 1, { { 0, -1 }, } },
2703
-
/* oxsemi_840 */ { 1, { { 0, 1 }, } },
2704
-
/* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2661
+
/* The Oxford Semi cards are unusual: older variants of 954 don't
2662
+
* support ECP, and 840 locks up if you write 1 to bit 2! None
2663
+
* implement nFault or service interrupts and all require 00001
2664
+
* bit pattern to be used for bits 4:0 with ECR writes. */
2665
+
/* oxsemi_952 */ { 1, { { 0, 1 }, },
2666
+
PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2667
+
/* oxsemi_954 */ { 1, { { 0, 1 }, },
2668
+
PARPORT_MODE_ECP |
2669
+
PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2670
+
/* oxsemi_840 */ { 1, { { 0, 1 }, },
2671
+
PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2672
+
/* oxsemi_pcie_pport */ { 1, { { 0, 1 }, },
2673
+
PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2705
2674
/* aks_0100 */ { 1, { { 0, -1 }, } },
2706
2675
/* mobility_pp */ { 1, { { 0, 1 }, } },
2707
2676
/* netmos_9900 */ { 1, { { 0, -1 }, } },
···
2876
2831
id->vendor, id->device, io_lo, io_hi, irq);
2877
2832
}
2878
2833
data->ports[count] =
2879
-
parport_pc_probe_port(io_lo, io_hi, irq,
2880
-
PARPORT_DMA_NONE, &dev->dev,
2881
-
IRQF_SHARED);
2834
+
__parport_pc_probe_port(io_lo, io_hi, irq,
2835
+
PARPORT_DMA_NONE, &dev->dev,
2836
+
IRQF_SHARED,
2837
+
cards[i].mode_mask,
2838
+
cards[i].ecr_writable);
2882
2839
if (data->ports[count])
2883
2840
count++;
2884
2841
}
+231
include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h
+231
include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H
8
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H
9
+
10
+
/* aggre1_noc */
11
+
#define MASTER_QUP_3 0
12
+
#define MASTER_EMAC 1
13
+
#define MASTER_EMAC_1 2
14
+
#define MASTER_SDC 3
15
+
#define MASTER_UFS_MEM 4
16
+
#define MASTER_USB2 5
17
+
#define MASTER_USB3_0 6
18
+
#define MASTER_USB3_1 7
19
+
#define SLAVE_A1NOC_SNOC 8
20
+
21
+
/* aggre2_noc */
22
+
#define MASTER_QDSS_BAM 0
23
+
#define MASTER_QUP_0 1
24
+
#define MASTER_QUP_1 2
25
+
#define MASTER_QUP_2 3
26
+
#define MASTER_CNOC_A2NOC 4
27
+
#define MASTER_CRYPTO_CORE0 5
28
+
#define MASTER_CRYPTO_CORE1 6
29
+
#define MASTER_IPA 7
30
+
#define MASTER_QDSS_ETR_0 8
31
+
#define MASTER_QDSS_ETR_1 9
32
+
#define MASTER_UFS_CARD 10
33
+
#define SLAVE_A2NOC_SNOC 11
34
+
35
+
/* clk_virt */
36
+
#define MASTER_QUP_CORE_0 0
37
+
#define MASTER_QUP_CORE_1 1
38
+
#define MASTER_QUP_CORE_2 2
39
+
#define MASTER_QUP_CORE_3 3
40
+
#define SLAVE_QUP_CORE_0 4
41
+
#define SLAVE_QUP_CORE_1 5
42
+
#define SLAVE_QUP_CORE_2 6
43
+
#define SLAVE_QUP_CORE_3 7
44
+
45
+
/* config_noc */
46
+
#define MASTER_GEM_NOC_CNOC 0
47
+
#define MASTER_GEM_NOC_PCIE_SNOC 1
48
+
#define SLAVE_AHB2PHY_0 2
49
+
#define SLAVE_AHB2PHY_1 3
50
+
#define SLAVE_AHB2PHY_2 4
51
+
#define SLAVE_AHB2PHY_3 5
52
+
#define SLAVE_ANOC_THROTTLE_CFG 6
53
+
#define SLAVE_AOSS 7
54
+
#define SLAVE_APPSS 8
55
+
#define SLAVE_BOOT_ROM 9
56
+
#define SLAVE_CAMERA_CFG 10
57
+
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11
58
+
#define SLAVE_CAMERA_RT_THROTTLE_CFG 12
59
+
#define SLAVE_CLK_CTL 13
60
+
#define SLAVE_CDSP_CFG 14
61
+
#define SLAVE_CDSP1_CFG 15
62
+
#define SLAVE_RBCPR_CX_CFG 16
63
+
#define SLAVE_RBCPR_MMCX_CFG 17
64
+
#define SLAVE_RBCPR_MX_CFG 18
65
+
#define SLAVE_CPR_NSPCX 19
66
+
#define SLAVE_CRYPTO_0_CFG 20
67
+
#define SLAVE_CX_RDPM 21
68
+
#define SLAVE_DISPLAY_CFG 22
69
+
#define SLAVE_DISPLAY_RT_THROTTLE_CFG 23
70
+
#define SLAVE_DISPLAY1_CFG 24
71
+
#define SLAVE_DISPLAY1_RT_THROTTLE_CFG 25
72
+
#define SLAVE_EMAC_CFG 26
73
+
#define SLAVE_EMAC1_CFG 27
74
+
#define SLAVE_GP_DSP0_CFG 28
75
+
#define SLAVE_GP_DSP1_CFG 29
76
+
#define SLAVE_GPDSP0_THROTTLE_CFG 30
77
+
#define SLAVE_GPDSP1_THROTTLE_CFG 31
78
+
#define SLAVE_GPU_TCU_THROTTLE_CFG 32
79
+
#define SLAVE_GFX3D_CFG 33
80
+
#define SLAVE_HWKM 34
81
+
#define SLAVE_IMEM_CFG 35
82
+
#define SLAVE_IPA_CFG 36
83
+
#define SLAVE_IPC_ROUTER_CFG 37
84
+
#define SLAVE_LPASS 38
85
+
#define SLAVE_LPASS_THROTTLE_CFG 39
86
+
#define SLAVE_MX_RDPM 40
87
+
#define SLAVE_MXC_RDPM 41
88
+
#define SLAVE_PCIE_0_CFG 42
89
+
#define SLAVE_PCIE_1_CFG 43
90
+
#define SLAVE_PCIE_RSC_CFG 44
91
+
#define SLAVE_PCIE_TCU_THROTTLE_CFG 45
92
+
#define SLAVE_PCIE_THROTTLE_CFG 46
93
+
#define SLAVE_PDM 47
94
+
#define SLAVE_PIMEM_CFG 48
95
+
#define SLAVE_PKA_WRAPPER_CFG 49
96
+
#define SLAVE_QDSS_CFG 50
97
+
#define SLAVE_QM_CFG 51
98
+
#define SLAVE_QM_MPU_CFG 52
99
+
#define SLAVE_QUP_0 53
100
+
#define SLAVE_QUP_1 54
101
+
#define SLAVE_QUP_2 55
102
+
#define SLAVE_QUP_3 56
103
+
#define SLAVE_SAIL_THROTTLE_CFG 57
104
+
#define SLAVE_SDC1 58
105
+
#define SLAVE_SECURITY 59
106
+
#define SLAVE_SNOC_THROTTLE_CFG 60
107
+
#define SLAVE_TCSR 61
108
+
#define SLAVE_TLMM 62
109
+
#define SLAVE_TSC_CFG 63
110
+
#define SLAVE_UFS_CARD_CFG 64
111
+
#define SLAVE_UFS_MEM_CFG 65
112
+
#define SLAVE_USB2 66
113
+
#define SLAVE_USB3_0 67
114
+
#define SLAVE_USB3_1 68
115
+
#define SLAVE_VENUS_CFG 69
116
+
#define SLAVE_VENUS_CVP_THROTTLE_CFG 70
117
+
#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 71
118
+
#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 72
119
+
#define SLAVE_DDRSS_CFG 73
120
+
#define SLAVE_GPDSP_NOC_CFG 74
121
+
#define SLAVE_CNOC_MNOC_HF_CFG 75
122
+
#define SLAVE_CNOC_MNOC_SF_CFG 76
123
+
#define SLAVE_PCIE_ANOC_CFG 77
124
+
#define SLAVE_SNOC_CFG 78
125
+
#define SLAVE_BOOT_IMEM 79
126
+
#define SLAVE_IMEM 80
127
+
#define SLAVE_PIMEM 81
128
+
#define SLAVE_PCIE_0 82
129
+
#define SLAVE_PCIE_1 83
130
+
#define SLAVE_QDSS_STM 84
131
+
#define SLAVE_TCU 85
132
+
133
+
/* dc_noc */
134
+
#define MASTER_CNOC_DC_NOC 0
135
+
#define SLAVE_LLCC_CFG 1
136
+
#define SLAVE_GEM_NOC_CFG 2
137
+
138
+
/* gem_noc */
139
+
#define MASTER_GPU_TCU 0
140
+
#define MASTER_PCIE_TCU 1
141
+
#define MASTER_SYS_TCU 2
142
+
#define MASTER_APPSS_PROC 3
143
+
#define MASTER_COMPUTE_NOC 4
144
+
#define MASTER_COMPUTE_NOC_1 5
145
+
#define MASTER_GEM_NOC_CFG 6
146
+
#define MASTER_GPDSP_SAIL 7
147
+
#define MASTER_GFX3D 8
148
+
#define MASTER_MNOC_HF_MEM_NOC 9
149
+
#define MASTER_MNOC_SF_MEM_NOC 10
150
+
#define MASTER_ANOC_PCIE_GEM_NOC 11
151
+
#define MASTER_SNOC_GC_MEM_NOC 12
152
+
#define MASTER_SNOC_SF_MEM_NOC 13
153
+
#define SLAVE_GEM_NOC_CNOC 14
154
+
#define SLAVE_LLCC 15
155
+
#define SLAVE_GEM_NOC_PCIE_CNOC 16
156
+
#define SLAVE_SERVICE_GEM_NOC_1 17
157
+
#define SLAVE_SERVICE_GEM_NOC_2 18
158
+
#define SLAVE_SERVICE_GEM_NOC 19
159
+
#define SLAVE_SERVICE_GEM_NOC2 20
160
+
161
+
/* gpdsp_anoc */
162
+
#define MASTER_DSP0 0
163
+
#define MASTER_DSP1 1
164
+
#define SLAVE_GP_DSP_SAIL_NOC 2
165
+
166
+
/* lpass_ag_noc */
167
+
#define MASTER_CNOC_LPASS_AG_NOC 0
168
+
#define MASTER_LPASS_PROC 1
169
+
#define SLAVE_LPASS_CORE_CFG 2
170
+
#define SLAVE_LPASS_LPI_CFG 3
171
+
#define SLAVE_LPASS_MPU_CFG 4
172
+
#define SLAVE_LPASS_TOP_CFG 5
173
+
#define SLAVE_LPASS_SNOC 6
174
+
#define SLAVE_SERVICES_LPASS_AML_NOC 7
175
+
#define SLAVE_SERVICE_LPASS_AG_NOC 8
176
+
177
+
/* mc_virt */
178
+
#define MASTER_LLCC 0
179
+
#define SLAVE_EBI1 1
180
+
181
+
/*mmss_noc */
182
+
#define MASTER_CAMNOC_HF 0
183
+
#define MASTER_CAMNOC_ICP 1
184
+
#define MASTER_CAMNOC_SF 2
185
+
#define MASTER_MDP0 3
186
+
#define MASTER_MDP1 4
187
+
#define MASTER_MDP_CORE1_0 5
188
+
#define MASTER_MDP_CORE1_1 6
189
+
#define MASTER_CNOC_MNOC_HF_CFG 7
190
+
#define MASTER_CNOC_MNOC_SF_CFG 8
191
+
#define MASTER_VIDEO_P0 9
192
+
#define MASTER_VIDEO_P1 10
193
+
#define MASTER_VIDEO_PROC 11
194
+
#define MASTER_VIDEO_V_PROC 12
195
+
#define SLAVE_MNOC_HF_MEM_NOC 13
196
+
#define SLAVE_MNOC_SF_MEM_NOC 14
197
+
#define SLAVE_SERVICE_MNOC_HF 15
198
+
#define SLAVE_SERVICE_MNOC_SF 16
199
+
200
+
/* nspa_noc */
201
+
#define MASTER_CDSP_NOC_CFG 0
202
+
#define MASTER_CDSP_PROC 1
203
+
#define SLAVE_HCP_A 2
204
+
#define SLAVE_CDSP_MEM_NOC 3
205
+
#define SLAVE_SERVICE_NSP_NOC 4
206
+
207
+
/* nspb_noc */
208
+
#define MASTER_CDSPB_NOC_CFG 0
209
+
#define MASTER_CDSP_PROC_B 1
210
+
#define SLAVE_CDSPB_MEM_NOC 2
211
+
#define SLAVE_HCP_B 3
212
+
#define SLAVE_SERVICE_NSPB_NOC 4
213
+
214
+
/* pcie_anoc */
215
+
#define MASTER_PCIE_0 0
216
+
#define MASTER_PCIE_1 1
217
+
#define SLAVE_ANOC_PCIE_GEM_NOC 2
218
+
219
+
/* system_noc */
220
+
#define MASTER_GIC_AHB 0
221
+
#define MASTER_A1NOC_SNOC 1
222
+
#define MASTER_A2NOC_SNOC 2
223
+
#define MASTER_LPASS_ANOC 3
224
+
#define MASTER_SNOC_CFG 4
225
+
#define MASTER_PIMEM 5
226
+
#define MASTER_GIC 6
227
+
#define SLAVE_SNOC_GEM_NOC_GC 7
228
+
#define SLAVE_SNOC_GEM_NOC_SF 8
229
+
#define SLAVE_SERVICE_SNOC 9
230
+
231
+
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H */
-3
include/dt-bindings/interconnect/qcom,sc7180.h
-3
include/dt-bindings/interconnect/qcom,sc7180.h
-3
include/dt-bindings/interconnect/qcom,sc8180x.h
-3
include/dt-bindings/interconnect/qcom,sc8180x.h
+2
-2
include/dt-bindings/interconnect/qcom,sc8280xp.h
+2
-2
include/dt-bindings/interconnect/qcom,sc8280xp.h
···
48
48
#define SLAVE_SERVICE_A2NOC 19
49
49
50
50
/* clk_virt */
51
-
#define MASTER_IPA_CORE 0
51
+
/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
52
52
#define MASTER_QUP_CORE_0 1
53
53
#define MASTER_QUP_CORE_1 2
54
54
#define MASTER_QUP_CORE_2 3
55
-
#define SLAVE_IPA_CORE 4
55
+
/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
56
56
#define SLAVE_QUP_CORE_0 5
57
57
#define SLAVE_QUP_CORE_1 6
58
58
#define SLAVE_QUP_CORE_2 7
+136
include/dt-bindings/interconnect/qcom,sdm670-rpmh.h
+136
include/dt-bindings/interconnect/qcom,sdm670-rpmh.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Qualcomm SDM670 interconnect IDs
4
+
*
5
+
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H
9
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H
10
+
11
+
#define MASTER_A1NOC_CFG 0
12
+
#define MASTER_BLSP_1 1
13
+
#define MASTER_TSIF 2
14
+
#define MASTER_EMMC 3
15
+
#define MASTER_SDCC_2 4
16
+
#define MASTER_SDCC_4 5
17
+
#define MASTER_UFS_MEM 6
18
+
#define SLAVE_A1NOC_SNOC 7
19
+
#define SLAVE_SERVICE_A1NOC 8
20
+
21
+
#define MASTER_A2NOC_CFG 0
22
+
#define MASTER_QDSS_BAM 1
23
+
#define MASTER_BLSP_2 2
24
+
#define MASTER_CNOC_A2NOC 3
25
+
#define MASTER_CRYPTO_CORE_0 4
26
+
#define MASTER_IPA 5
27
+
#define MASTER_QDSS_ETR 6
28
+
#define MASTER_USB3 7
29
+
#define SLAVE_A2NOC_SNOC 8
30
+
#define SLAVE_SERVICE_A2NOC 9
31
+
32
+
33
+
#define MASTER_SPDM 0
34
+
#define MASTER_SNOC_CNOC 1
35
+
#define SLAVE_A1NOC_CFG 2
36
+
#define SLAVE_A2NOC_CFG 3
37
+
#define SLAVE_AOP 4
38
+
#define SLAVE_AOSS 5
39
+
#define SLAVE_CAMERA_CFG 6
40
+
#define SLAVE_CLK_CTL 7
41
+
#define SLAVE_CDSP_CFG 8
42
+
#define SLAVE_RBCPR_CX_CFG 9
43
+
#define SLAVE_CRYPTO_0_CFG 10
44
+
#define SLAVE_DCC_CFG 11
45
+
#define SLAVE_CNOC_DDRSS 12
46
+
#define SLAVE_DISPLAY_CFG 13
47
+
#define SLAVE_EMMC_CFG 14
48
+
#define SLAVE_GLM 15
49
+
#define SLAVE_GRAPHICS_3D_CFG 16
50
+
#define SLAVE_IMEM_CFG 17
51
+
#define SLAVE_IPA_CFG 18
52
+
#define SLAVE_CNOC_MNOC_CFG 19
53
+
#define SLAVE_PDM 20
54
+
#define SLAVE_SOUTH_PHY_CFG 21
55
+
#define SLAVE_PIMEM_CFG 22
56
+
#define SLAVE_PRNG 23
57
+
#define SLAVE_QDSS_CFG 24
58
+
#define SLAVE_BLSP_2 25
59
+
#define SLAVE_BLSP_1 26
60
+
#define SLAVE_SDCC_2 27
61
+
#define SLAVE_SDCC_4 28
62
+
#define SLAVE_SNOC_CFG 29
63
+
#define SLAVE_SPDM_WRAPPER 30
64
+
#define SLAVE_TCSR 31
65
+
#define SLAVE_TLMM_NORTH 32
66
+
#define SLAVE_TLMM_SOUTH 33
67
+
#define SLAVE_TSIF 34
68
+
#define SLAVE_UFS_MEM_CFG 35
69
+
#define SLAVE_USB3 36
70
+
#define SLAVE_VENUS_CFG 37
71
+
#define SLAVE_VSENSE_CTRL_CFG 38
72
+
#define SLAVE_CNOC_A2NOC 39
73
+
#define SLAVE_SERVICE_CNOC 40
74
+
75
+
#define MASTER_CNOC_DC_NOC 0
76
+
#define SLAVE_LLCC_CFG 1
77
+
#define SLAVE_MEM_NOC_CFG 2
78
+
79
+
#define MASTER_AMPSS_M0 0
80
+
#define MASTER_GNOC_CFG 1
81
+
#define SLAVE_GNOC_SNOC 2
82
+
#define SLAVE_GNOC_MEM_NOC 3
83
+
#define SLAVE_SERVICE_GNOC 4
84
+
85
+
#define MASTER_TCU_0 0
86
+
#define MASTER_MEM_NOC_CFG 1
87
+
#define MASTER_GNOC_MEM_NOC 2
88
+
#define MASTER_MNOC_HF_MEM_NOC 3
89
+
#define MASTER_MNOC_SF_MEM_NOC 4
90
+
#define MASTER_SNOC_GC_MEM_NOC 5
91
+
#define MASTER_SNOC_SF_MEM_NOC 6
92
+
#define MASTER_GRAPHICS_3D 7
93
+
#define SLAVE_MSS_PROC_MS_MPU_CFG 8
94
+
#define SLAVE_MEM_NOC_GNOC 9
95
+
#define SLAVE_LLCC 10
96
+
#define SLAVE_MEM_NOC_SNOC 11
97
+
#define SLAVE_SERVICE_MEM_NOC 12
98
+
#define MASTER_LLCC 13
99
+
#define SLAVE_EBI_CH0 14
100
+
101
+
#define MASTER_CNOC_MNOC_CFG 0
102
+
#define MASTER_CAMNOC_HF0 1
103
+
#define MASTER_CAMNOC_HF1 2
104
+
#define MASTER_CAMNOC_SF 3
105
+
#define MASTER_MDP_PORT0 4
106
+
#define MASTER_MDP_PORT1 5
107
+
#define MASTER_ROTATOR 6
108
+
#define MASTER_VIDEO_P0 7
109
+
#define MASTER_VIDEO_P1 8
110
+
#define MASTER_VIDEO_PROC 9
111
+
#define SLAVE_MNOC_SF_MEM_NOC 10
112
+
#define SLAVE_MNOC_HF_MEM_NOC 11
113
+
#define SLAVE_SERVICE_MNOC 12
114
+
115
+
#define MASTER_SNOC_CFG 0
116
+
#define MASTER_A1NOC_SNOC 1
117
+
#define MASTER_A2NOC_SNOC 2
118
+
#define MASTER_GNOC_SNOC 3
119
+
#define MASTER_MEM_NOC_SNOC 4
120
+
#define MASTER_PIMEM 5
121
+
#define MASTER_GIC 6
122
+
#define SLAVE_APPSS 7
123
+
#define SLAVE_SNOC_CNOC 8
124
+
#define SLAVE_SNOC_MEM_NOC_GC 9
125
+
#define SLAVE_SNOC_MEM_NOC_SF 10
126
+
#define SLAVE_OCIMEM 11
127
+
#define SLAVE_PIMEM 12
128
+
#define SLAVE_SERVICE_SNOC 13
129
+
#define SLAVE_QDSS_STM 14
130
+
#define SLAVE_TCU 15
131
+
#define MASTER_CAMNOC_HF0_UNCOMP 16
132
+
#define MASTER_CAMNOC_HF1_UNCOMP 17
133
+
#define MASTER_CAMNOC_SF_UNCOMP 18
134
+
#define SLAVE_CAMNOC_UNCOMP 19
135
+
136
+
#endif
-2
include/dt-bindings/interconnect/qcom,sdx55.h
-2
include/dt-bindings/interconnect/qcom,sdx55.h
-3
include/dt-bindings/interconnect/qcom,sm8150.h
-3
include/dt-bindings/interconnect/qcom,sm8150.h
-3
include/dt-bindings/interconnect/qcom,sm8250.h
-3
include/dt-bindings/interconnect/qcom,sm8250.h
+23
-11
include/linux/coresight-pmu.h
+23
-11
include/linux/coresight-pmu.h
···
7
7
#ifndef _LINUX_CORESIGHT_PMU_H
8
8
#define _LINUX_CORESIGHT_PMU_H
9
9
10
+
#include <linux/bits.h>
11
+
10
12
#define CORESIGHT_ETM_PMU_NAME "cs_etm"
11
-
#define CORESIGHT_ETM_PMU_SEED 0x10
13
+
14
+
/*
15
+
* The legacy Trace ID system based on fixed calculation from the cpu
16
+
* number. This has been replaced by drivers using a dynamic allocation
17
+
* system - but need to retain the legacy algorithm for backward comparibility
18
+
* in certain situations:-
19
+
* a) new perf running on older systems that generate the legacy mapping
20
+
* b) older tools that may not update at the same time as the kernel.
21
+
*/
22
+
#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2))
12
23
13
24
/*
14
25
* Below are the definition of bit offsets for perf option, and works as
···
45
34
#define ETM4_CFG_BIT_RETSTK 12
46
35
#define ETM4_CFG_BIT_VMID_OPT 15
47
36
48
-
static inline int coresight_get_trace_id(int cpu)
49
-
{
50
-
/*
51
-
* A trace ID of value 0 is invalid, so let's start at some
52
-
* random value that fits in 7 bits and go from there. Since
53
-
* the common convention is to have data trace IDs be I(N) + 1,
54
-
* set instruction trace IDs as a function of the CPU number.
55
-
*/
56
-
return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
57
-
}
37
+
/*
38
+
* Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload.
39
+
* Used to associate a CPU with the CoreSight Trace ID.
40
+
* [07:00] - Trace ID - uses 8 bits to make value easy to read in file.
41
+
* [59:08] - Unused (SBZ)
42
+
* [63:60] - Version
43
+
*/
44
+
#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
45
+
#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60)
46
+
47
+
#define CS_AUX_HW_ID_CURR_VERSION 0
58
48
59
49
#endif
+1
-3
include/linux/coresight.h
+1
-3
include/linux/coresight.h
···
61
61
CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
62
62
CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
63
63
CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
64
+
CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS,
64
65
};
65
66
66
67
enum coresight_dev_subtype_helper {
···
315
314
* Operations available for sources.
316
315
* @cpu_id: returns the value of the CPU number this component
317
316
* is associated to.
318
-
* @trace_id: returns the value of the component's trace ID as known
319
-
* to the HW.
320
317
* @enable: enables tracing for a source.
321
318
* @disable: disables tracing for a source.
322
319
*/
323
320
struct coresight_ops_source {
324
321
int (*cpu_id)(struct coresight_device *csdev);
325
-
int (*trace_id)(struct coresight_device *csdev);
326
322
int (*enable)(struct coresight_device *csdev,
327
323
struct perf_event *event, u32 mode);
328
324
void (*disable)(struct coresight_device *csdev,
+14
include/linux/etherdevice.h
+14
include/linux/etherdevice.h
···
508
508
}
509
509
510
510
/**
511
+
* eth_addr_add() - Add (or subtract) an offset to/from the given MAC address.
512
+
*
513
+
* @offset: Offset to add.
514
+
* @addr: Pointer to a six-byte array containing Ethernet address to increment.
515
+
*/
516
+
static inline void eth_addr_add(u8 *addr, long offset)
517
+
{
518
+
u64 u = ether_addr_to_u64(addr);
519
+
520
+
u += offset;
521
+
u64_to_ether_addr(u, addr);
522
+
}
523
+
524
+
/**
511
525
* is_etherdev_addr - Tell if given Ethernet address belongs to the device.
512
526
* @dev: Pointer to a device structure
513
527
* @addr: Pointer to a six-byte array containing the Ethernet address
+15
include/linux/hisi_acc_qm.h
+15
include/linux/hisi_acc_qm.h
···
271
271
u16 *qp_finish_id;
272
272
};
273
273
274
+
/**
275
+
* struct qm_err_isolate
276
+
* @isolate_lock: protects device error log
277
+
* @err_threshold: user config error threshold which triggers isolation
278
+
* @is_isolate: device isolation state
279
+
* @uacce_hw_errs: index into qm device error list
280
+
*/
281
+
struct qm_err_isolate {
282
+
struct mutex isolate_lock;
283
+
u32 err_threshold;
284
+
bool is_isolate;
285
+
struct list_head qm_hw_errs;
286
+
};
287
+
274
288
struct hisi_qm {
275
289
enum qm_hw_ver ver;
276
290
enum qm_fun_type fun_type;
···
354
340
struct qm_shaper_factor *factor;
355
341
u32 mb_qos;
356
342
u32 type_rate;
343
+
struct qm_err_isolate isolate_data;
357
344
};
358
345
359
346
struct hisi_qp_status {
+5
include/linux/iio/iio.h
+5
include/linux/iio/iio.h
+2
-2
include/linux/mhi_ep.h
+2
-2
include/linux/mhi_ep.h
···
70
70
* @cmd_ctx_cache_phys: Physical address of the host command context cache
71
71
* @chdb: Array of channel doorbell interrupt info
72
72
* @event_lock: Lock for protecting event rings
73
-
* @list_lock: Lock for protecting state transition and channel doorbell lists
74
73
* @state_lock: Lock for protecting state transitions
74
+
* @list_lock: Lock for protecting state transition and channel doorbell lists
75
75
* @st_transition_list: List of state transitions
76
76
* @ch_db_list: List of queued channel doorbells
77
77
* @wq: Dedicated workqueue for handling rings and state changes
···
117
117
118
118
struct mhi_ep_db_info chdb[4];
119
119
struct mutex event_lock;
120
+
struct mutex state_lock;
120
121
spinlock_t list_lock;
121
-
spinlock_t state_lock;
122
122
123
123
struct list_head st_transition_list;
124
124
struct list_head ch_db_list;
+1
-9
include/linux/nvmem-consumer.h
+1
-9
include/linux/nvmem-consumer.h
···
18
18
/* consumer cookie */
19
19
struct nvmem_cell;
20
20
struct nvmem_device;
21
-
22
-
struct nvmem_cell_info {
23
-
const char *name;
24
-
unsigned int offset;
25
-
unsigned int bytes;
26
-
unsigned int bit_offset;
27
-
unsigned int nbits;
28
-
struct device_node *np;
29
-
};
21
+
struct nvmem_cell_info;
30
22
31
23
/**
32
24
* struct nvmem_cell_lookup - cell lookup entry
+28
-3
include/linux/nvmem-provider.h
+28
-3
include/linux/nvmem-provider.h
···
14
14
#include <linux/gpio/consumer.h>
15
15
16
16
struct nvmem_device;
17
-
struct nvmem_cell_info;
18
17
typedef int (*nvmem_reg_read_t)(void *priv, unsigned int offset,
19
18
void *val, size_t bytes);
20
19
typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset,
21
20
void *val, size_t bytes);
22
21
/* used for vendor specific post processing of cell data */
23
-
typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, unsigned int offset,
24
-
void *buf, size_t bytes);
22
+
typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, int index,
23
+
unsigned int offset, void *buf, size_t bytes);
25
24
26
25
enum nvmem_type {
27
26
NVMEM_TYPE_UNKNOWN = 0,
···
44
45
unsigned int start;
45
46
unsigned int end;
46
47
unsigned char value;
48
+
};
49
+
50
+
/**
51
+
* struct nvmem_cell_info - NVMEM cell description
52
+
* @name: Name.
53
+
* @offset: Offset within the NVMEM device.
54
+
* @bytes: Length of the cell.
55
+
* @bit_offset: Bit offset if cell is smaller than a byte.
56
+
* @nbits: Number of bits.
57
+
* @np: Optional device_node pointer.
58
+
*/
59
+
struct nvmem_cell_info {
60
+
const char *name;
61
+
unsigned int offset;
62
+
unsigned int bytes;
63
+
unsigned int bit_offset;
64
+
unsigned int nbits;
65
+
struct device_node *np;
47
66
};
48
67
49
68
/**
···
153
136
void nvmem_add_cell_table(struct nvmem_cell_table *table);
154
137
void nvmem_del_cell_table(struct nvmem_cell_table *table);
155
138
139
+
int nvmem_add_one_cell(struct nvmem_device *nvmem,
140
+
const struct nvmem_cell_info *info);
141
+
156
142
#else
157
143
158
144
static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c)
···
173
153
174
154
static inline void nvmem_add_cell_table(struct nvmem_cell_table *table) {}
175
155
static inline void nvmem_del_cell_table(struct nvmem_cell_table *table) {}
156
+
static inline int nvmem_add_one_cell(struct nvmem_device *nvmem,
157
+
const struct nvmem_cell_info *info)
158
+
{
159
+
return -EOPNOTSUPP;
160
+
}
176
161
177
162
#endif /* CONFIG_NVMEM */
178
163
#endif /* ifndef _LINUX_NVMEM_PROVIDER_H */
+25
include/linux/of.h
+25
include/linux/of.h
···
1009
1009
}
1010
1010
1011
1011
/**
1012
+
* of_parse_phandle_with_optional_args() - Find a node pointed by phandle in a list
1013
+
* @np: pointer to a device tree node containing a list
1014
+
* @list_name: property name that contains a list
1015
+
* @cells_name: property name that specifies phandles' arguments count
1016
+
* @index: index of a phandle to parse out
1017
+
* @out_args: optional pointer to output arguments structure (will be filled)
1018
+
*
1019
+
* Same as of_parse_phandle_with_args() except that if the cells_name property
1020
+
* is not found, cell_count of 0 is assumed.
1021
+
*
1022
+
* This is used to useful, if you have a phandle which didn't have arguments
1023
+
* before and thus doesn't have a '#*-cells' property but is now migrated to
1024
+
* having arguments while retaining backwards compatibility.
1025
+
*/
1026
+
static inline int of_parse_phandle_with_optional_args(const struct device_node *np,
1027
+
const char *list_name,
1028
+
const char *cells_name,
1029
+
int index,
1030
+
struct of_phandle_args *out_args)
1031
+
{
1032
+
return __of_parse_phandle_with_args(np, list_name, cells_name,
1033
+
0, index, out_args);
1034
+
}
1035
+
1036
+
/**
1012
1037
* of_property_count_u8_elems - Count the number of u8 elements in a property
1013
1038
*
1014
1039
* @np: device node from which the property value is to be read.
+3
include/linux/parport_pc.h
+3
include/linux/parport_pc.h
-9
include/linux/platform_data/tsl2563.h
-9
include/linux/platform_data/tsl2563.h
+12
include/linux/uacce.h
+12
include/linux/uacce.h
···
8
8
#define UACCE_NAME "uacce"
9
9
#define UACCE_MAX_REGION 2
10
10
#define UACCE_MAX_NAME_SIZE 64
11
+
#define UACCE_MAX_ERR_THRESHOLD 65535
11
12
12
13
struct uacce_queue;
13
14
struct uacce_device;
···
31
30
* @is_q_updated: check whether the task is finished
32
31
* @mmap: mmap addresses of queue to user space
33
32
* @ioctl: ioctl for user space users of the queue
33
+
* @get_isolate_state: get the device state after set the isolate strategy
34
+
* @isolate_err_threshold_write: stored the isolate error threshold to the device
35
+
* @isolate_err_threshold_read: read the isolate error threshold value from the device
34
36
*/
35
37
struct uacce_ops {
36
38
int (*get_available_instances)(struct uacce_device *uacce);
···
47
43
struct uacce_qfile_region *qfr);
48
44
long (*ioctl)(struct uacce_queue *q, unsigned int cmd,
49
45
unsigned long arg);
46
+
enum uacce_dev_state (*get_isolate_state)(struct uacce_device *uacce);
47
+
int (*isolate_err_threshold_write)(struct uacce_device *uacce, u32 num);
48
+
u32 (*isolate_err_threshold_read)(struct uacce_device *uacce);
50
49
};
51
50
52
51
/**
···
62
55
char name[UACCE_MAX_NAME_SIZE];
63
56
unsigned int flags;
64
57
const struct uacce_ops *ops;
58
+
};
59
+
60
+
enum uacce_dev_state {
61
+
UACCE_DEV_NORMAL,
62
+
UACCE_DEV_ISOLATE,
65
63
};
66
64
67
65
enum uacce_q_state {
+13
-6
include/linux/uuid.h
+13
-6
include/linux/uuid.h
···
8
8
#ifndef _LINUX_UUID_H_
9
9
#define _LINUX_UUID_H_
10
10
11
-
#include <uapi/linux/uuid.h>
12
11
#include <linux/string.h>
13
12
14
13
#define UUID_SIZE 16
15
14
16
15
typedef struct {
17
16
__u8 b[UUID_SIZE];
17
+
} guid_t;
18
+
19
+
typedef struct {
20
+
__u8 b[UUID_SIZE];
18
21
} uuid_t;
22
+
23
+
#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
24
+
((guid_t) \
25
+
{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
26
+
(b) & 0xff, ((b) >> 8) & 0xff, \
27
+
(c) & 0xff, ((c) >> 8) & 0xff, \
28
+
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
19
29
20
30
#define UUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
21
31
((uuid_t) \
···
107
97
int guid_parse(const char *uuid, guid_t *u);
108
98
int uuid_parse(const char *uuid, uuid_t *u);
109
99
110
-
/* backwards compatibility, don't use in new code */
111
-
static inline int uuid_le_cmp(const guid_t u1, const guid_t u2)
112
-
{
113
-
return memcmp(&u1, &u2, sizeof(guid_t));
114
-
}
100
+
/* MEI UUID type, don't use anywhere else */
101
+
#include <uapi/linux/uuid.h>
115
102
116
103
#endif
+6
-1
include/uapi/linux/android/binder.h
+6
-1
include/uapi/linux/android/binder.h
···
450
450
451
451
BR_FROZEN_REPLY = _IO('r', 18),
452
452
/*
453
-
* The target of the last transaction (either a bcTRANSACTION or
453
+
* The target of the last sync transaction (either a bcTRANSACTION or
454
454
* a bcATTEMPT_ACQUIRE) is frozen. No parameters.
455
455
*/
456
456
···
459
459
* Current process sent too many oneway calls to target, and the last
460
460
* asynchronous transaction makes the allocated async buffer size exceed
461
461
* detection threshold. No parameters.
462
+
*/
463
+
464
+
BR_TRANSACTION_PENDING_FROZEN = _IO('r', 20),
465
+
/*
466
+
* The target of the last async transaction is frozen. No parameters.
462
467
*/
463
468
};
464
469
+4
-8
include/uapi/linux/uuid.h
+4
-8
include/uapi/linux/uuid.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2
2
/* DO NOT USE in new code! This is solely for MEI due to legacy reasons */
3
3
/*
4
-
* UUID/GUID definition
4
+
* MEI UUID definition
5
5
*
6
6
* Copyright (C) 2010, Intel Corp.
7
7
* Huang Ying <ying.huang@intel.com>
···
14
14
15
15
typedef struct {
16
16
__u8 b[16];
17
-
} guid_t;
17
+
} uuid_le;
18
18
19
-
#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
20
-
((guid_t) \
19
+
#define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
20
+
((uuid_le) \
21
21
{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
22
22
(b) & 0xff, ((b) >> 8) & 0xff, \
23
23
(c) & 0xff, ((c) >> 8) & 0xff, \
24
24
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
25
25
26
-
/* backwards compatibility, don't use in new code */
27
-
typedef guid_t uuid_le;
28
-
#define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
29
-
GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7)
30
26
#define NULL_UUID_LE \
31
27
UUID_LE(0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, \
32
28
0x00, 0x00, 0x00, 0x00)
+1
kernel/events/core.c
+1
kernel/events/core.c
+6
-17
tools/iio/iio_utils.c
+6
-17
tools/iio/iio_utils.c
···
264
264
if (fscanf(sysfsfp, "%f", output) != 1)
265
265
ret = errno ? -errno : -ENODATA;
266
266
267
+
fclose(sysfsfp);
267
268
break;
268
269
}
269
270
error_free_filename:
···
346
345
}
347
346
348
347
sysfsfp = fopen(filename, "r");
348
+
free(filename);
349
349
if (!sysfsfp) {
350
350
ret = -errno;
351
-
free(filename);
352
351
goto error_close_dir;
353
352
}
354
353
···
358
357
if (fclose(sysfsfp))
359
358
perror("build_channel_array(): Failed to close file");
360
359
361
-
free(filename);
362
360
goto error_close_dir;
363
361
}
364
362
if (ret == 1)
···
365
365
366
366
if (fclose(sysfsfp)) {
367
367
ret = -errno;
368
-
free(filename);
369
368
goto error_close_dir;
370
369
}
371
370
372
-
free(filename);
373
371
}
374
372
375
373
*ci_array = malloc(sizeof(**ci_array) * (*counter));
···
393
395
}
394
396
395
397
sysfsfp = fopen(filename, "r");
398
+
free(filename);
396
399
if (!sysfsfp) {
397
400
ret = -errno;
398
-
free(filename);
399
401
count--;
400
402
goto error_cleanup_array;
401
403
}
···
403
405
errno = 0;
404
406
if (fscanf(sysfsfp, "%i", ¤t_enabled) != 1) {
405
407
ret = errno ? -errno : -ENODATA;
406
-
free(filename);
407
408
count--;
408
409
goto error_cleanup_array;
409
410
}
410
411
411
412
if (fclose(sysfsfp)) {
412
413
ret = -errno;
413
-
free(filename);
414
414
count--;
415
415
goto error_cleanup_array;
416
416
}
417
417
418
418
if (!current_enabled) {
419
-
free(filename);
420
419
count--;
421
420
continue;
422
421
}
···
424
429
strlen(ent->d_name) -
425
430
strlen("_en"));
426
431
if (!current->name) {
427
-
free(filename);
428
432
ret = -ENOMEM;
429
433
count--;
430
434
goto error_cleanup_array;
···
433
439
ret = iioutils_break_up_name(current->name,
434
440
¤t->generic_name);
435
441
if (ret) {
436
-
free(filename);
437
442
free(current->name);
438
443
count--;
439
444
goto error_cleanup_array;
···
443
450
scan_el_dir,
444
451
current->name);
445
452
if (ret < 0) {
446
-
free(filename);
447
453
ret = -ENOMEM;
448
454
goto error_cleanup_array;
449
455
}
450
456
451
457
sysfsfp = fopen(filename, "r");
458
+
free(filename);
452
459
if (!sysfsfp) {
453
460
ret = -errno;
454
-
fprintf(stderr, "failed to open %s\n",
455
-
filename);
456
-
free(filename);
461
+
fprintf(stderr, "failed to open %s/%s_index\n",
462
+
scan_el_dir, current->name);
457
463
goto error_cleanup_array;
458
464
}
459
465
···
462
470
if (fclose(sysfsfp))
463
471
perror("build_channel_array(): Failed to close file");
464
472
465
-
free(filename);
466
473
goto error_cleanup_array;
467
474
}
468
475
469
476
if (fclose(sysfsfp)) {
470
477
ret = -errno;
471
-
free(filename);
472
478
goto error_cleanup_array;
473
479
}
474
480
475
-
free(filename);
476
481
/* Find the scale */
477
482
ret = iioutils_get_param_float(¤t->scale,
478
483
"scale",