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linux
clk: qcom: gcc-msm8916: move GPLL definitions up
Move GPLL definitions up, before the clock parent tables, so that we can
use gpll hw clock fields in the parent_data/parent_hws tables.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-5-dmitry.baryshkov@linaro.org
authored by
Dmitry Baryshkov
and committed by
Bjorn Andersson
69da4290
5a6d3067
+108
-108
+108
-108
drivers/clk/qcom/gcc-msm8916.c
+108
-108
drivers/clk/qcom/gcc-msm8916.c
···
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P_EXT_MCLK,
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};
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+
static struct clk_pll gpll0 = {
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.l_reg = 0x21004,
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.m_reg = 0x21008,
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.n_reg = 0x2100c,
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.config_reg = 0x21010,
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.mode_reg = 0x21000,
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.status_reg = 0x2101c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll0",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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+
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static struct clk_regmap gpll0_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpll0_vote",
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.parent_names = (const char *[]){ "gpll0" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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+
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static struct clk_pll gpll1 = {
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.l_reg = 0x20004,
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.m_reg = 0x20008,
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.n_reg = 0x2000c,
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.config_reg = 0x20010,
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.mode_reg = 0x20000,
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.status_reg = 0x2001c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll1",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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static struct clk_regmap gpll1_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "gpll1_vote",
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.parent_names = (const char *[]){ "gpll1" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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+
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static struct clk_pll gpll2 = {
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.l_reg = 0x4a004,
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.m_reg = 0x4a008,
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.n_reg = 0x4a00c,
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.config_reg = 0x4a010,
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.mode_reg = 0x4a000,
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.status_reg = 0x4a01c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll2",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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+
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static struct clk_regmap gpll2_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(2),
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.hw.init = &(struct clk_init_data){
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.name = "gpll2_vote",
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.parent_names = (const char *[]){ "gpll2" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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static struct clk_pll bimc_pll = {
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.l_reg = 0x23004,
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.m_reg = 0x23008,
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.n_reg = 0x2300c,
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.config_reg = 0x23010,
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.mode_reg = 0x23000,
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.status_reg = 0x2301c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "bimc_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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+
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static struct clk_regmap bimc_pll_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(3),
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.hw.init = &(struct clk_init_data){
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.name = "bimc_pll_vote",
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.parent_names = (const char *[]){ "bimc_pll" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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+
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static const struct parent_map gcc_xo_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
···
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"gpll1_vote",
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"ext_mclk",
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"sleep_clk",
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-
};
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-
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static struct clk_pll gpll0 = {
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.l_reg = 0x21004,
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.m_reg = 0x21008,
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.n_reg = 0x2100c,
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.config_reg = 0x21010,
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.mode_reg = 0x21000,
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.status_reg = 0x2101c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll0",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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static struct clk_regmap gpll0_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpll0_vote",
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.parent_names = (const char *[]){ "gpll0" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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static struct clk_pll gpll1 = {
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.l_reg = 0x20004,
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.m_reg = 0x20008,
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.n_reg = 0x2000c,
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.config_reg = 0x20010,
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.mode_reg = 0x20000,
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.status_reg = 0x2001c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll1",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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static struct clk_regmap gpll1_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "gpll1_vote",
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.parent_names = (const char *[]){ "gpll1" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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static struct clk_pll gpll2 = {
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.l_reg = 0x4a004,
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.m_reg = 0x4a008,
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.n_reg = 0x4a00c,
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.config_reg = 0x4a010,
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.mode_reg = 0x4a000,
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.status_reg = 0x4a01c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll2",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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static struct clk_regmap gpll2_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(2),
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.hw.init = &(struct clk_init_data){
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.name = "gpll2_vote",
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.parent_names = (const char *[]){ "gpll2" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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static struct clk_pll bimc_pll = {
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.l_reg = 0x23004,
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.m_reg = 0x23008,
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.n_reg = 0x2300c,
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.config_reg = 0x23010,
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.mode_reg = 0x23000,
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.status_reg = 0x2301c,
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.status_bit = 17,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "bimc_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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static struct clk_regmap bimc_pll_vote = {
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.enable_reg = 0x45000,
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.enable_mask = BIT(3),
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.hw.init = &(struct clk_init_data){
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.name = "bimc_pll_vote",
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.parent_names = (const char *[]){ "bimc_pll" },
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.num_parents = 1,
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.ops = &clk_pll_vote_ops,
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},
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};
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static struct clk_rcg2 pcnoc_bfdcd_clk_src = {