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EDAC/amd64: Remove NUM_CONTROLLERS macro

Currently, the NUM_CONTROLLERS macro is used to limit the amount of memory
controllers (UMCs) available per node. The number of UMCs available per node,
however, is already cached by the max_mcs variable of struct amd64_pvt.

Allocate the relevant data structures dynamically using the variable instead
of static allocation through the macro.

The max_mcs variable is used for legacy systems too. These systems have a max
of 2 controllers. Since the default value of max_mcs, set in per_family_init(),
is 2, these legacy systems are also covered.

Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20251106015727.1987246-1-avadhut.naik@amd.com

authored by

Avadhut Naik and committed by
Borislav Petkov (AMD) 6a857969 e9abd990

+6 -2
+5
drivers/edac/amd64_edac.c
··· 3732 3732 pci_dev_put(pvt->F1); 3733 3733 pci_dev_put(pvt->F2); 3734 3734 kfree(pvt->umc); 3735 + kfree(pvt->csels); 3735 3736 } 3736 3737 3737 3738 static struct low_ops umc_ops = { ··· 3915 3914 else 3916 3915 scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), "F%02Xh_M%02Xh", 3917 3916 pvt->fam, pvt->model); 3917 + 3918 + pvt->csels = kcalloc(pvt->max_mcs, sizeof(*pvt->csels), GFP_KERNEL); 3919 + if (!pvt->csels) 3920 + return -ENOMEM; 3918 3921 3919 3922 return 0; 3920 3923 }
+1 -2
drivers/edac/amd64_edac.h
··· 96 96 /* Hardware limit on ChipSelect rows per MC and processors per system */ 97 97 #define NUM_CHIPSELECTS 8 98 98 #define DRAM_RANGES 8 99 - #define NUM_CONTROLLERS 16 100 99 101 100 #define ON true 102 101 #define OFF false ··· 347 348 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ 348 349 349 350 /* one for each DCT/UMC */ 350 - struct chip_select csels[NUM_CONTROLLERS]; 351 + struct chip_select *csels; 351 352 352 353 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ 353 354 struct dram_range ranges[DRAM_RANGES];