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drm/rcar-du: dsi: Clean up handling of DRM mode flags

Introduce TXVMVPRMSET0R_BPP_MASK macro and use FIELD_PREP() to generate
appropriate bitfield from mask and value without bitshift, assign this
value into vprmset0r. Remove TXVMVPRMSET0R_CSPC_RGB which is never used,
replace it with code comment next to TXVMVPRMSET0R_CSPC_YCbCr.

Replace (mode->flags & DRM_MODE_FLAG_P.SYNC) test with inverted conditional
(mode->flags & DRM_MODE_FLAG_N.SYNC) and bitwise orr vprmset0r with either
or both TXVMVPRMSET0R_HSPOL_LOW and TXVMVPRMSET0R_VSPOL_LOW if conditional
matches.

Do not convert bits and bitfields to BIT() and GENMASK() yet, to be
consisten with the current style. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.

Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/20251028232959.109936-10-marek.vasut+renesas@mailbox.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

authored by

Marek Vasut and committed by
Tomi Valkeinen 94fe479f dd3957e0

+13 -15
+6 -6
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
··· 490 490 491 491 rcar_mipi_dsi_write(dsi, TXVMSETR, setr); 492 492 493 - /* Configuration for Video Parameters */ 494 - vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ? 495 - TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW) 496 - | (mode->flags & DRM_MODE_FLAG_PHSYNC ? 497 - TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW) 498 - | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24; 493 + /* Configuration for Video Parameters, input is always RGB888 */ 494 + vprmset0r = TXVMVPRMSET0R_BPP_24; 495 + if (mode->flags & DRM_MODE_FLAG_NVSYNC) 496 + vprmset0r |= TXVMVPRMSET0R_VSPOL_LOW; 497 + if (mode->flags & DRM_MODE_FLAG_NHSYNC) 498 + vprmset0r |= TXVMVPRMSET0R_HSPOL_LOW; 499 499 500 500 vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay) 501 501 | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
+7 -9
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
··· 171 171 #define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c) 172 172 173 173 #define TXVMVPRMSET0R 0x1d0 174 - #define TXVMVPRMSET0R_HSPOL_HIG (0 << 17) 175 - #define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) 176 - #define TXVMVPRMSET0R_VSPOL_HIG (0 << 16) 177 - #define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) 178 - #define TXVMVPRMSET0R_CSPC_RGB (0 << 4) 179 - #define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) 180 - #define TXVMVPRMSET0R_BPP_16 (0 << 0) 181 - #define TXVMVPRMSET0R_BPP_18 (1 << 0) 182 - #define TXVMVPRMSET0R_BPP_24 (2 << 0) 174 + #define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) /* 0:High 1:Low */ 175 + #define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) /* 0:High 1:Low */ 176 + #define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) /* 0:RGB 1:YCbCr */ 177 + #define TXVMVPRMSET0R_BPP_MASK (7 << 0) 178 + #define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0) 179 + #define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1) 180 + #define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2) 183 181 184 182 #define TXVMVPRMSET1R 0x1d4 185 183 #define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16)