tjh.dev / kernel
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drm/i915: Remove i915_reg.h from intel_display_irq.c

Move VLV_IRQ_REGS to common header for interrupt to make
intel_display_irq.c free from including i915_reg.h.

v2: Move interrupt to dedicated header (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-18-uma.shankar@intel.com

Uma Shankar 6ef8bf1e 1506ba80

+63 -53
-1
drivers/gpu/drm/i915/display/intel_display_irq.c
··· 7 7 #include <drm/drm_vblank.h> 8 8 #include <drm/intel/intel_gmd_interrupt_regs.h> 9 9 10 - #include "i915_reg.h" 11 10 #include "icl_dsi_regs.h" 12 11 #include "intel_crtc.h" 13 12 #include "intel_de.h"
+5
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 1470 1470 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 1471 1471 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 1472 1472 1473 + /* Display Internal Timeout Register */ 1474 + #define RM_TIMEOUT _MMIO(0x42060) 1475 + #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) 1476 + #define MMIO_TIMEOUT_US(us) ((us) << 0) 1477 + 1473 1478 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 1474 1479 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 1475 1480 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
+2
drivers/gpu/drm/i915/gt/intel_gt_irq.c
··· 5 5 6 6 #include <linux/sched/clock.h> 7 7 8 + #include <drm/intel/intel_gmd_interrupt_regs.h> 9 + 8 10 #include "i915_drv.h" 9 11 #include "i915_irq.h" 10 12 #include "i915_reg.h"
+1
drivers/gpu/drm/i915/gt/intel_rc6.c
··· 8 8 9 9 #include <drm/drm_print.h> 10 10 #include <drm/intel/intel_pcode_regs.h> 11 + #include <drm/intel/intel_gmd_interrupt_regs.h> 11 12 12 13 #include "display/vlv_clock.h" 13 14 #include "gem/i915_gem_region.h"
+1
drivers/gpu/drm/i915/gvt/handlers.c
··· 41 41 #include <drm/display/drm_dp.h> 42 42 #include <drm/drm_print.h> 43 43 #include <drm/intel/intel_pcode_regs.h> 44 + #include <drm/intel/intel_gmd_interrupt_regs.h> 44 45 45 46 #include "display/bxt_dpio_phy_regs.h" 46 47 #include "display/i9xx_plane_regs.h"
+1
drivers/gpu/drm/i915/gvt/interrupt.c
··· 32 32 #include <linux/eventfd.h> 33 33 34 34 #include <drm/drm_print.h> 35 + #include <drm/intel/intel_gmd_interrupt_regs.h> 35 36 36 37 #include "display/intel_display_regs.h" 37 38
-52
drivers/gpu/drm/i915/i915_reg.h
··· 335 335 336 336 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 337 337 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 338 - #define SCPD0 _MMIO(0x209c) /* 915+ only */ 339 - #define SCPD_FBC_IGNORE_3D (1 << 6) 340 - #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 341 338 #define GEN2_IER _MMIO(0x20a0) 342 339 #define GEN2_IIR _MMIO(0x20a4) 343 340 #define GEN2_IMR _MMIO(0x20a8) ··· 347 350 #define GINT_DIS (1 << 22) 348 351 #define GCFG_DIS (1 << 8) 349 352 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 350 - #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 351 - #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 352 - #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 353 - #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 354 - #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 355 - #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 356 - #define VLV_PCBR_ADDR_SHIFT 12 357 353 358 354 #define EIR _MMIO(0x20b0) 359 355 #define EMR _MMIO(0x20b4) ··· 672 682 #define PCH_3DCGDIS1 _MMIO(0x46024) 673 683 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 674 684 675 - /* Display Internal Timeout Register */ 676 - #define RM_TIMEOUT _MMIO(0x42060) 677 - #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) 678 - #define MMIO_TIMEOUT_US(us) ((us) << 0) 679 - 680 685 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 681 686 #define MASTER_INTERRUPT_ENABLE (1 << 31) 682 687 ··· 683 698 #define GT_IRQ_REGS I915_IRQ_REGS(GTIMR, \ 684 699 GTIER, \ 685 700 GTIIR) 686 - 687 - #define GEN8_MASTER_IRQ _MMIO(0x44200) 688 - #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 689 - #define GEN8_PCU_IRQ (1 << 30) 690 - #define GEN8_DE_PCH_IRQ (1 << 23) 691 - #define GEN8_DE_MISC_IRQ (1 << 22) 692 - #define GEN8_DE_PORT_IRQ (1 << 20) 693 - #define GEN8_DE_PIPE_C_IRQ (1 << 18) 694 - #define GEN8_DE_PIPE_B_IRQ (1 << 17) 695 - #define GEN8_DE_PIPE_A_IRQ (1 << 16) 696 - #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 697 - #define GEN8_GT_VECS_IRQ (1 << 6) 698 - #define GEN8_GT_GUC_IRQ (1 << 5) 699 - #define GEN8_GT_PM_IRQ (1 << 4) 700 - #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 701 - #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 702 - #define GEN8_GT_BCS_IRQ (1 << 1) 703 - #define GEN8_GT_RCS_IRQ (1 << 0) 704 701 705 702 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 706 703 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) ··· 708 741 #define GEN8_PCU_IRQ_REGS I915_IRQ_REGS(GEN8_PCU_IMR, \ 709 742 GEN8_PCU_IER, \ 710 743 GEN8_PCU_IIR) 711 - 712 - #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 713 - #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 714 - #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 715 - #define GEN11_GU_MISC_IER _MMIO(0x444fc) 716 - #define GEN11_GU_MISC_GSE (1 << 27) 717 - 718 - #define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \ 719 - GEN11_GU_MISC_IER, \ 720 - GEN11_GU_MISC_IIR) 721 - 722 - #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 723 - #define GEN11_MASTER_IRQ (1 << 31) 724 - #define GEN11_PCU_IRQ (1 << 30) 725 - #define GEN11_GU_MISC_IRQ (1 << 29) 726 - #define GEN11_DISPLAY_IRQ (1 << 16) 727 - #define GEN11_GT_DW_IRQ(x) (1 << (x)) 728 - #define GEN11_GT_DW1_IRQ (1 << 1) 729 - #define GEN11_GT_DW0_IRQ (1 << 0) 730 744 731 745 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 732 746 #define DG1_MSTR_IRQ REG_BIT(31)
+1
drivers/gpu/drm/i915/intel_clock_gating.c
··· 27 27 28 28 #include <drm/drm_print.h> 29 29 #include <drm/intel/intel_gmd_misc_regs.h> 30 + #include <drm/intel/intel_gmd_interrupt_regs.h> 30 31 31 32 #include "display/i9xx_plane_regs.h" 32 33 #include "display/intel_display.h"
+2
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
··· 6 6 #include <drm/intel/intel_pcode_regs.h> 7 7 #include <drm/intel/intel_gmd_misc_regs.h> 8 8 9 + #include <drm/intel/intel_gmd_interrupt_regs.h> 10 + 9 11 #include "display/bxt_dpio_phy_regs.h" 10 12 #include "display/i9xx_plane_regs.h" 11 13 #include "display/i9xx_wm_regs.h"
+1
drivers/gpu/drm/i915/vlv_suspend.c
··· 7 7 #include <linux/kernel.h> 8 8 9 9 #include <drm/drm_print.h> 10 + #include <drm/intel/intel_gmd_interrupt_regs.h> 10 11 11 12 #include "gt/intel_gt_regs.h" 12 13
+49
include/drm/intel/intel_gmd_interrupt_regs.h
··· 40 40 #define I915_ASLE_INTERRUPT (1 << 0) 41 41 #define I915_BSD_USER_INTERRUPT (1 << 25) 42 42 43 + #define GEN8_MASTER_IRQ _MMIO(0x44200) 44 + #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 45 + #define GEN8_PCU_IRQ (1 << 30) 46 + #define GEN8_DE_PCH_IRQ (1 << 23) 47 + #define GEN8_DE_MISC_IRQ (1 << 22) 48 + #define GEN8_DE_PORT_IRQ (1 << 20) 49 + #define GEN8_DE_PIPE_C_IRQ (1 << 18) 50 + #define GEN8_DE_PIPE_B_IRQ (1 << 17) 51 + #define GEN8_DE_PIPE_A_IRQ (1 << 16) 52 + #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 53 + #define GEN8_GT_VECS_IRQ (1 << 6) 54 + #define GEN8_GT_GUC_IRQ (1 << 5) 55 + #define GEN8_GT_PM_IRQ (1 << 4) 56 + #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 57 + #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 58 + #define GEN8_GT_BCS_IRQ (1 << 1) 59 + #define GEN8_GT_RCS_IRQ (1 << 0) 60 + 61 + #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 62 + #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 63 + #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 64 + #define GEN11_GU_MISC_IER _MMIO(0x444fc) 65 + #define GEN11_GU_MISC_GSE (1 << 27) 66 + 67 + #define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \ 68 + GEN11_GU_MISC_IER, \ 69 + GEN11_GU_MISC_IIR) 70 + 71 + #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 72 + #define GEN11_MASTER_IRQ (1 << 31) 73 + #define GEN11_PCU_IRQ (1 << 30) 74 + #define GEN11_GU_MISC_IRQ (1 << 29) 75 + #define GEN11_DISPLAY_IRQ (1 << 16) 76 + #define GEN11_GT_DW_IRQ(x) (1 << (x)) 77 + #define GEN11_GT_DW1_IRQ (1 << 1) 78 + #define GEN11_GT_DW0_IRQ (1 << 0) 79 + 80 + #define SCPD0 _MMIO(0x209c) /* 915+ only */ 81 + #define SCPD_FBC_IGNORE_3D (1 << 6) 82 + #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 83 + 84 + #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 85 + #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 86 + #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 87 + #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 88 + #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 89 + #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 90 + #define VLV_PCBR_ADDR_SHIFT 12 91 + 43 92 #endif