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net: stmmac: move stmmac_axi_blen_to_mask() to stmmac_main.c

Move the call to stmmac_axi_blen_to_mask() out of the individual
MAC version drivers into the main code in stmmac_init_dma_engine(),
passing the resulting value through a new member, axi_blen_regval,
in the struct stmmac_axi structure.

There is now no need for stmmac_axi_blen_to_dma_mask() to use
u32p_replace_bits(), so use FIELD_PREP() instead.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vLfLW-0000000FMb1-0zKV@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Russell King (Oracle) and committed by
Jakub Kicinski 6ff3310c 2704af20

+10 -8
+1 -2
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
··· 41 41 * set). Note that the UNDEF bit is readonly, and is the inverse of 42 42 * Bus Mode bit 16. 43 43 */ 44 - stmmac_axi_blen_to_mask(&value, axi->axi_blen, 45 - ARRAY_SIZE(axi->axi_blen)); 44 + value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval; 46 45 47 46 writel(value, ioaddr + DMA_AXI_BUS_MODE); 48 47 }
+1 -2
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
··· 40 40 * set). Note that the UNDEF bit is readonly, and is the inverse of 41 41 * Bus Mode bit 16. 42 42 */ 43 - stmmac_axi_blen_to_mask(&value, axi->axi_blen, 44 - ARRAY_SIZE(axi->axi_blen)); 43 + value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval; 45 44 46 45 writel(value, ioaddr + DMA_SYS_BUS_MODE); 47 46 }
+1 -2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
··· 106 106 * set). Note that the UNDEF bit is readonly, and is the inverse of 107 107 * Bus Mode bit 16. 108 108 */ 109 - stmmac_axi_blen_to_mask(&value, axi->axi_blen, 110 - ARRAY_SIZE(axi->axi_blen)); 109 + value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval; 111 110 112 111 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); 113 112 writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
+6 -2
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
··· 223 223 val |= burst >> 2; 224 224 } 225 225 226 - u32p_replace_bits(regval, val, DMA_AXI_BLEN_MASK); 226 + *regval = FIELD_PREP(DMA_AXI_BLEN_MASK, val); 227 227 } 228 228 229 229 /** ··· 3212 3212 /* DMA Configuration */ 3213 3213 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg); 3214 3214 3215 - if (priv->plat->axi) 3215 + if (priv->plat->axi) { 3216 + /* Encode the AXI burst length to a register value */ 3217 + stmmac_axi_blen_to_mask(&priv->plat->axi->axi_blen_regval, 3218 + priv->plat->axi->axi_blen, AXI_BLEN); 3216 3219 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 3220 + } 3217 3221 3218 3222 /* DMA CSR Channel configuration */ 3219 3223 for (chan = 0; chan < dma_csr_ch; chan++) {
+1
include/linux/stmmac.h
··· 113 113 u32 axi_wr_osr_lmt; 114 114 u32 axi_rd_osr_lmt; 115 115 bool axi_kbbe; 116 + u32 axi_blen_regval; 116 117 u32 axi_blen[AXI_BLEN]; 117 118 bool axi_fb; 118 119 bool axi_mb;