Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: lcc-msm8960: use macros to implement mi2s clocks
Split and extend existing CLK_AIF_OSR_DIV macro to implement mi2s
clocks. This simplifies the driver and removes extra code duplication.
The clock mi2s_div_clk used .enable_reg/.enable_bit, however these
fields are not used with by the clk_regmap_div_ops, thus they are
silently dropped. Clock enablement is handled in the mi2s_bit_div_clk
clock.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-6-dmitry.baryshkov@linaro.org
authored by
Dmitry Baryshkov
and committed by
Bjorn Andersson
7026af10
e38fc8f0
+27
-115
+27
-115
drivers/clk/qcom/lcc-msm8960.c
+27
-115
drivers/clk/qcom/lcc-msm8960.c
···
86
86
{ }
87
87
};
88
88
89
-
static struct clk_rcg mi2s_osr_src = {
90
-
.ns_reg = 0x48,
91
-
.md_reg = 0x4c,
92
-
.mn = {
93
-
.mnctr_en_bit = 8,
94
-
.mnctr_reset_bit = 7,
95
-
.mnctr_mode_shift = 5,
96
-
.n_val_shift = 24,
97
-
.m_val_shift = 8,
98
-
.width = 8,
99
-
},
100
-
.p = {
101
-
.pre_div_shift = 3,
102
-
.pre_div_width = 2,
103
-
},
104
-
.s = {
105
-
.src_sel_shift = 0,
106
-
.parent_map = lcc_pxo_pll4_map,
107
-
},
108
-
.freq_tbl = clk_tbl_aif_osr_393,
109
-
.clkr = {
110
-
.enable_reg = 0x48,
111
-
.enable_mask = BIT(9),
112
-
.hw.init = &(struct clk_init_data){
113
-
.name = "mi2s_osr_src",
114
-
.parent_names = lcc_pxo_pll4,
115
-
.num_parents = 2,
116
-
.ops = &clk_rcg_ops,
117
-
.flags = CLK_SET_RATE_GATE,
118
-
},
119
-
},
120
-
};
121
-
122
-
static const char * const lcc_mi2s_parents[] = {
123
-
"mi2s_osr_src",
124
-
};
125
-
126
-
static struct clk_branch mi2s_osr_clk = {
127
-
.halt_reg = 0x50,
128
-
.halt_bit = 1,
129
-
.halt_check = BRANCH_HALT_ENABLE,
130
-
.clkr = {
131
-
.enable_reg = 0x48,
132
-
.enable_mask = BIT(17),
133
-
.hw.init = &(struct clk_init_data){
134
-
.name = "mi2s_osr_clk",
135
-
.parent_names = lcc_mi2s_parents,
136
-
.num_parents = 1,
137
-
.ops = &clk_branch_ops,
138
-
.flags = CLK_SET_RATE_PARENT,
139
-
},
140
-
},
141
-
};
142
-
143
-
static struct clk_regmap_div mi2s_div_clk = {
144
-
.reg = 0x48,
145
-
.shift = 10,
146
-
.width = 4,
147
-
.clkr = {
148
-
.enable_reg = 0x48,
149
-
.enable_mask = BIT(15),
150
-
.hw.init = &(struct clk_init_data){
151
-
.name = "mi2s_div_clk",
152
-
.parent_names = lcc_mi2s_parents,
153
-
.num_parents = 1,
154
-
.ops = &clk_regmap_div_ops,
155
-
},
156
-
},
157
-
};
158
-
159
-
static struct clk_branch mi2s_bit_div_clk = {
160
-
.halt_reg = 0x50,
161
-
.halt_bit = 0,
162
-
.halt_check = BRANCH_HALT_ENABLE,
163
-
.clkr = {
164
-
.enable_reg = 0x48,
165
-
.enable_mask = BIT(15),
166
-
.hw.init = &(struct clk_init_data){
167
-
.name = "mi2s_bit_div_clk",
168
-
.parent_names = (const char *[]){ "mi2s_div_clk" },
169
-
.num_parents = 1,
170
-
.ops = &clk_branch_ops,
171
-
.flags = CLK_SET_RATE_PARENT,
172
-
},
173
-
},
174
-
};
175
-
176
-
static struct clk_regmap_mux mi2s_bit_clk = {
177
-
.reg = 0x48,
178
-
.shift = 14,
179
-
.width = 1,
180
-
.clkr = {
181
-
.hw.init = &(struct clk_init_data){
182
-
.name = "mi2s_bit_clk",
183
-
.parent_names = (const char *[]){
184
-
"mi2s_bit_div_clk",
185
-
"mi2s_codec_clk",
186
-
},
187
-
.num_parents = 2,
188
-
.ops = &clk_regmap_mux_closest_ops,
189
-
.flags = CLK_SET_RATE_PARENT,
190
-
},
191
-
},
192
-
};
193
-
194
-
#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
89
+
#define CLK_AIF_OSR_SRC(prefix, _ns, _md) \
195
90
static struct clk_rcg prefix##_osr_src = { \
196
91
.ns_reg = _ns, \
197
92
.md_reg = _md, \
···
123
228
static const char * const lcc_##prefix##_parents[] = { \
124
229
#prefix "_osr_src", \
125
230
}; \
126
-
\
231
+
232
+
#define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit) \
127
233
static struct clk_branch prefix##_osr_clk = { \
128
234
.halt_reg = hr, \
129
235
.halt_bit = 1, \
130
236
.halt_check = BRANCH_HALT_ENABLE, \
131
237
.clkr = { \
132
238
.enable_reg = _ns, \
133
-
.enable_mask = BIT(21), \
239
+
.enable_mask = BIT(en_bit), \
134
240
.hw.init = &(struct clk_init_data){ \
135
241
.name = #prefix "_osr_clk", \
136
242
.parent_names = lcc_##prefix##_parents, \
···
141
245
}, \
142
246
}, \
143
247
}; \
144
-
\
248
+
249
+
#define CLK_AIF_OSR_DIV_CLK(prefix, _ns, _width) \
145
250
static struct clk_regmap_div prefix##_div_clk = { \
146
251
.reg = _ns, \
147
252
.shift = 10, \
148
-
.width = 8, \
253
+
.width = _width, \
149
254
.clkr = { \
150
255
.hw.init = &(struct clk_init_data){ \
151
256
.name = #prefix "_div_clk", \
···
156
259
}, \
157
260
}, \
158
261
}; \
159
-
\
262
+
263
+
#define CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, en_bit) \
160
264
static struct clk_branch prefix##_bit_div_clk = { \
161
265
.halt_reg = hr, \
162
266
.halt_bit = 0, \
163
267
.halt_check = BRANCH_HALT_ENABLE, \
164
268
.clkr = { \
165
269
.enable_reg = _ns, \
166
-
.enable_mask = BIT(19), \
270
+
.enable_mask = BIT(en_bit), \
167
271
.hw.init = &(struct clk_init_data){ \
168
272
.name = #prefix "_bit_div_clk", \
169
273
.parent_names = (const char *[]){ \
···
176
278
}, \
177
279
}, \
178
280
}; \
179
-
\
281
+
282
+
#define CLK_AIF_OSR_BIT_CLK(prefix, _ns, _shift) \
180
283
static struct clk_regmap_mux prefix##_bit_clk = { \
181
284
.reg = _ns, \
182
-
.shift = 18, \
285
+
.shift = _shift, \
183
286
.width = 1, \
184
287
.clkr = { \
185
288
.hw.init = &(struct clk_init_data){ \
···
194
295
.flags = CLK_SET_RATE_PARENT, \
195
296
}, \
196
297
}, \
197
-
}
298
+
};
299
+
300
+
CLK_AIF_OSR_SRC(mi2s, 0x48, 0x4c)
301
+
CLK_AIF_OSR_CLK(mi2s, 0x48, 0x50, 17)
302
+
CLK_AIF_OSR_DIV_CLK(mi2s, 0x48, 4)
303
+
CLK_AIF_OSR_BIT_DIV_CLK(mi2s, 0x48, 0x50, 15)
304
+
CLK_AIF_OSR_BIT_CLK(mi2s, 0x48, 14)
305
+
306
+
#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
307
+
CLK_AIF_OSR_SRC(prefix, _ns, _md) \
308
+
CLK_AIF_OSR_CLK(prefix, _ns, hr, 21) \
309
+
CLK_AIF_OSR_DIV_CLK(prefix, _ns, 8) \
310
+
CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, 19) \
311
+
CLK_AIF_OSR_BIT_CLK(prefix, _ns, 18)
198
312
199
313
CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
200
314
CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);