tjh.dev / kernel
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clk: qcom: gcc-msm8960: use parent_hws/_data instead of parent_names

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-5-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson e38fc8f0 d247abe6

+232 -132
+232 -132
drivers/clk/qcom/gcc-msm8960.c
··· 35 35 .status_bit = 16, 36 36 .clkr.hw.init = &(struct clk_init_data){ 37 37 .name = "pll3", 38 - .parent_names = (const char *[]){ "pxo" }, 38 + .parent_data = &(const struct clk_parent_data){ 39 + .fw_name = "pxo", .name = "pxo_board", 40 + }, 39 41 .num_parents = 1, 40 42 .ops = &clk_pll_ops, 41 43 }, ··· 48 46 .enable_mask = BIT(4), 49 47 .hw.init = &(struct clk_init_data){ 50 48 .name = "pll4_vote", 51 - .parent_names = (const char *[]){ "pll4" }, 49 + .parent_data = &(const struct clk_parent_data){ 50 + .fw_name = "pll4", .name = "pll4", 51 + }, 52 52 .num_parents = 1, 53 53 .ops = &clk_pll_vote_ops, 54 54 }, ··· 66 62 .status_bit = 16, 67 63 .clkr.hw.init = &(struct clk_init_data){ 68 64 .name = "pll8", 69 - .parent_names = (const char *[]){ "pxo" }, 65 + .parent_data = &(const struct clk_parent_data){ 66 + .fw_name = "pxo", .name = "pxo_board", 67 + }, 70 68 .num_parents = 1, 71 69 .ops = &clk_pll_ops, 72 70 }, ··· 79 73 .enable_mask = BIT(8), 80 74 .hw.init = &(struct clk_init_data){ 81 75 .name = "pll8_vote", 82 - .parent_names = (const char *[]){ "pll8" }, 76 + .parent_hws = (const struct clk_hw*[]){ 77 + &pll8.clkr.hw 78 + }, 83 79 .num_parents = 1, 84 80 .ops = &clk_pll_vote_ops, 85 81 }, ··· 104 96 static struct clk_hfpll hfpll0 = { 105 97 .d = &hfpll0_data, 106 98 .clkr.hw.init = &(struct clk_init_data){ 107 - .parent_names = (const char *[]){ "pxo" }, 99 + .parent_data = &(const struct clk_parent_data){ 100 + .fw_name = "pxo", .name = "pxo_board", 101 + }, 108 102 .num_parents = 1, 109 103 .name = "hfpll0", 110 104 .ops = &clk_ops_hfpll, ··· 146 136 static struct clk_hfpll hfpll1 = { 147 137 .d = &hfpll1_data, 148 138 .clkr.hw.init = &(struct clk_init_data){ 149 - .parent_names = (const char *[]){ "pxo" }, 139 + .parent_data = &(const struct clk_parent_data){ 140 + .fw_name = "pxo", .name = "pxo_board", 141 + }, 150 142 .num_parents = 1, 151 143 .name = "hfpll1", 152 144 .ops = &clk_ops_hfpll, ··· 174 162 static struct clk_hfpll hfpll2 = { 175 163 .d = &hfpll2_data, 176 164 .clkr.hw.init = &(struct clk_init_data){ 177 - .parent_names = (const char *[]){ "pxo" }, 165 + .parent_data = &(const struct clk_parent_data){ 166 + .fw_name = "pxo", .name = "pxo_board", 167 + }, 178 168 .num_parents = 1, 179 169 .name = "hfpll2", 180 170 .ops = &clk_ops_hfpll, ··· 202 188 static struct clk_hfpll hfpll3 = { 203 189 .d = &hfpll3_data, 204 190 .clkr.hw.init = &(struct clk_init_data){ 205 - .parent_names = (const char *[]){ "pxo" }, 191 + .parent_data = &(const struct clk_parent_data){ 192 + .fw_name = "pxo", .name = "pxo_board", 193 + }, 206 194 .num_parents = 1, 207 195 .name = "hfpll3", 208 196 .ops = &clk_ops_hfpll, ··· 244 228 static struct clk_hfpll hfpll_l2 = { 245 229 .d = &hfpll_l2_data, 246 230 .clkr.hw.init = &(struct clk_init_data){ 247 - .parent_names = (const char *[]){ "pxo" }, 231 + .parent_data = &(const struct clk_parent_data){ 232 + .fw_name = "pxo", .name = "pxo_board", 233 + }, 248 234 .num_parents = 1, 249 235 .name = "hfpll_l2", 250 236 .ops = &clk_ops_hfpll, ··· 265 247 .status_bit = 16, 266 248 .clkr.hw.init = &(struct clk_init_data){ 267 249 .name = "pll14", 268 - .parent_names = (const char *[]){ "pxo" }, 250 + .parent_data = &(const struct clk_parent_data){ 251 + .fw_name = "pxo", .name = "pxo_board", 252 + }, 269 253 .num_parents = 1, 270 254 .ops = &clk_pll_ops, 271 255 }, ··· 278 258 .enable_mask = BIT(14), 279 259 .hw.init = &(struct clk_init_data){ 280 260 .name = "pll14_vote", 281 - .parent_names = (const char *[]){ "pll14" }, 261 + .parent_hws = (const struct clk_hw*[]){ 262 + &pll14.clkr.hw 263 + }, 282 264 .num_parents = 1, 283 265 .ops = &clk_pll_vote_ops, 284 266 }, ··· 298 276 { P_PLL8, 3 } 299 277 }; 300 278 301 - static const char * const gcc_pxo_pll8[] = { 302 - "pxo", 303 - "pll8_vote", 279 + static const struct clk_parent_data gcc_pxo_pll8[] = { 280 + { .fw_name = "pxo", .name = "pxo_board" }, 281 + { .hw = &pll8_vote.hw }, 304 282 }; 305 283 306 284 static const struct parent_map gcc_pxo_pll8_cxo_map[] = { ··· 309 287 { P_CXO, 5 } 310 288 }; 311 289 312 - static const char * const gcc_pxo_pll8_cxo[] = { 313 - "pxo", 314 - "pll8_vote", 315 - "cxo", 290 + static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { 291 + { .fw_name = "pxo", .name = "pxo_board" }, 292 + { .hw = &pll8_vote.hw }, 293 + { .fw_name = "cxo", .name = "cxo_board" }, 316 294 }; 317 295 318 296 static const struct parent_map gcc_pxo_pll8_pll3_map[] = { ··· 321 299 { P_PLL3, 6 } 322 300 }; 323 301 324 - static const char * const gcc_pxo_pll8_pll3[] = { 325 - "pxo", 326 - "pll8_vote", 327 - "pll3", 302 + static const struct clk_parent_data gcc_pxo_pll8_pll3[] = { 303 + { .fw_name = "pxo", .name = "pxo_board" }, 304 + { .hw = &pll8_vote.hw }, 305 + { .hw = &pll3.clkr.hw }, 328 306 }; 329 307 330 308 static struct freq_tbl clk_tbl_gsbi_uart[] = { ··· 370 348 .enable_mask = BIT(11), 371 349 .hw.init = &(struct clk_init_data){ 372 350 .name = "gsbi1_uart_src", 373 - .parent_names = gcc_pxo_pll8, 351 + .parent_data = gcc_pxo_pll8, 374 352 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 375 353 .ops = &clk_rcg_ops, 376 354 .flags = CLK_SET_PARENT_GATE, ··· 386 364 .enable_mask = BIT(9), 387 365 .hw.init = &(struct clk_init_data){ 388 366 .name = "gsbi1_uart_clk", 389 - .parent_names = (const char *[]){ 390 - "gsbi1_uart_src", 367 + .parent_hws = (const struct clk_hw*[]){ 368 + &gsbi1_uart_src.clkr.hw 391 369 }, 392 370 .num_parents = 1, 393 371 .ops = &clk_branch_ops, ··· 421 399 .enable_mask = BIT(11), 422 400 .hw.init = &(struct clk_init_data){ 423 401 .name = "gsbi2_uart_src", 424 - .parent_names = gcc_pxo_pll8, 402 + .parent_data = gcc_pxo_pll8, 425 403 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 426 404 .ops = &clk_rcg_ops, 427 405 .flags = CLK_SET_PARENT_GATE, ··· 437 415 .enable_mask = BIT(9), 438 416 .hw.init = &(struct clk_init_data){ 439 417 .name = "gsbi2_uart_clk", 440 - .parent_names = (const char *[]){ 441 - "gsbi2_uart_src", 418 + .parent_hws = (const struct clk_hw*[]){ 419 + &gsbi2_uart_src.clkr.hw 442 420 }, 443 421 .num_parents = 1, 444 422 .ops = &clk_branch_ops, ··· 472 450 .enable_mask = BIT(11), 473 451 .hw.init = &(struct clk_init_data){ 474 452 .name = "gsbi3_uart_src", 475 - .parent_names = gcc_pxo_pll8, 453 + .parent_data = gcc_pxo_pll8, 476 454 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 477 455 .ops = &clk_rcg_ops, 478 456 .flags = CLK_SET_PARENT_GATE, ··· 488 466 .enable_mask = BIT(9), 489 467 .hw.init = &(struct clk_init_data){ 490 468 .name = "gsbi3_uart_clk", 491 - .parent_names = (const char *[]){ 492 - "gsbi3_uart_src", 469 + .parent_hws = (const struct clk_hw*[]){ 470 + &gsbi3_uart_src.clkr.hw 493 471 }, 494 472 .num_parents = 1, 495 473 .ops = &clk_branch_ops, ··· 523 501 .enable_mask = BIT(11), 524 502 .hw.init = &(struct clk_init_data){ 525 503 .name = "gsbi4_uart_src", 526 - .parent_names = gcc_pxo_pll8, 504 + .parent_data = gcc_pxo_pll8, 527 505 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 528 506 .ops = &clk_rcg_ops, 529 507 .flags = CLK_SET_PARENT_GATE, ··· 539 517 .enable_mask = BIT(9), 540 518 .hw.init = &(struct clk_init_data){ 541 519 .name = "gsbi4_uart_clk", 542 - .parent_names = (const char *[]){ 543 - "gsbi4_uart_src", 520 + .parent_hws = (const struct clk_hw*[]){ 521 + &gsbi4_uart_src.clkr.hw 544 522 }, 545 523 .num_parents = 1, 546 524 .ops = &clk_branch_ops, ··· 574 552 .enable_mask = BIT(11), 575 553 .hw.init = &(struct clk_init_data){ 576 554 .name = "gsbi5_uart_src", 577 - .parent_names = gcc_pxo_pll8, 555 + .parent_data = gcc_pxo_pll8, 578 556 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 579 557 .ops = &clk_rcg_ops, 580 558 .flags = CLK_SET_PARENT_GATE, ··· 590 568 .enable_mask = BIT(9), 591 569 .hw.init = &(struct clk_init_data){ 592 570 .name = "gsbi5_uart_clk", 593 - .parent_names = (const char *[]){ 594 - "gsbi5_uart_src", 571 + .parent_hws = (const struct clk_hw*[]){ 572 + &gsbi5_uart_src.clkr.hw 595 573 }, 596 574 .num_parents = 1, 597 575 .ops = &clk_branch_ops, ··· 625 603 .enable_mask = BIT(11), 626 604 .hw.init = &(struct clk_init_data){ 627 605 .name = "gsbi6_uart_src", 628 - .parent_names = gcc_pxo_pll8, 606 + .parent_data = gcc_pxo_pll8, 629 607 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 630 608 .ops = &clk_rcg_ops, 631 609 .flags = CLK_SET_PARENT_GATE, ··· 641 619 .enable_mask = BIT(9), 642 620 .hw.init = &(struct clk_init_data){ 643 621 .name = "gsbi6_uart_clk", 644 - .parent_names = (const char *[]){ 645 - "gsbi6_uart_src", 622 + .parent_hws = (const struct clk_hw*[]){ 623 + &gsbi6_uart_src.clkr.hw 646 624 }, 647 625 .num_parents = 1, 648 626 .ops = &clk_branch_ops, ··· 676 654 .enable_mask = BIT(11), 677 655 .hw.init = &(struct clk_init_data){ 678 656 .name = "gsbi7_uart_src", 679 - .parent_names = gcc_pxo_pll8, 657 + .parent_data = gcc_pxo_pll8, 680 658 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 681 659 .ops = &clk_rcg_ops, 682 660 .flags = CLK_SET_PARENT_GATE, ··· 692 670 .enable_mask = BIT(9), 693 671 .hw.init = &(struct clk_init_data){ 694 672 .name = "gsbi7_uart_clk", 695 - .parent_names = (const char *[]){ 696 - "gsbi7_uart_src", 673 + .parent_hws = (const struct clk_hw*[]){ 674 + &gsbi7_uart_src.clkr.hw 697 675 }, 698 676 .num_parents = 1, 699 677 .ops = &clk_branch_ops, ··· 727 705 .enable_mask = BIT(11), 728 706 .hw.init = &(struct clk_init_data){ 729 707 .name = "gsbi8_uart_src", 730 - .parent_names = gcc_pxo_pll8, 708 + .parent_data = gcc_pxo_pll8, 731 709 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 732 710 .ops = &clk_rcg_ops, 733 711 .flags = CLK_SET_PARENT_GATE, ··· 743 721 .enable_mask = BIT(9), 744 722 .hw.init = &(struct clk_init_data){ 745 723 .name = "gsbi8_uart_clk", 746 - .parent_names = (const char *[]){ "gsbi8_uart_src" }, 724 + .parent_hws = (const struct clk_hw*[]){ 725 + &gsbi8_uart_src.clkr.hw 726 + }, 747 727 .num_parents = 1, 748 728 .ops = &clk_branch_ops, 749 729 .flags = CLK_SET_RATE_PARENT, ··· 778 754 .enable_mask = BIT(11), 779 755 .hw.init = &(struct clk_init_data){ 780 756 .name = "gsbi9_uart_src", 781 - .parent_names = gcc_pxo_pll8, 757 + .parent_data = gcc_pxo_pll8, 782 758 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 783 759 .ops = &clk_rcg_ops, 784 760 .flags = CLK_SET_PARENT_GATE, ··· 794 770 .enable_mask = BIT(9), 795 771 .hw.init = &(struct clk_init_data){ 796 772 .name = "gsbi9_uart_clk", 797 - .parent_names = (const char *[]){ "gsbi9_uart_src" }, 773 + .parent_hws = (const struct clk_hw*[]){ 774 + &gsbi9_uart_src.clkr.hw 775 + }, 798 776 .num_parents = 1, 799 777 .ops = &clk_branch_ops, 800 778 .flags = CLK_SET_RATE_PARENT, ··· 829 803 .enable_mask = BIT(11), 830 804 .hw.init = &(struct clk_init_data){ 831 805 .name = "gsbi10_uart_src", 832 - .parent_names = gcc_pxo_pll8, 806 + .parent_data = gcc_pxo_pll8, 833 807 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 834 808 .ops = &clk_rcg_ops, 835 809 .flags = CLK_SET_PARENT_GATE, ··· 845 819 .enable_mask = BIT(9), 846 820 .hw.init = &(struct clk_init_data){ 847 821 .name = "gsbi10_uart_clk", 848 - .parent_names = (const char *[]){ "gsbi10_uart_src" }, 822 + .parent_hws = (const struct clk_hw*[]){ 823 + &gsbi10_uart_src.clkr.hw 824 + }, 849 825 .num_parents = 1, 850 826 .ops = &clk_branch_ops, 851 827 .flags = CLK_SET_RATE_PARENT, ··· 880 852 .enable_mask = BIT(11), 881 853 .hw.init = &(struct clk_init_data){ 882 854 .name = "gsbi11_uart_src", 883 - .parent_names = gcc_pxo_pll8, 855 + .parent_data = gcc_pxo_pll8, 884 856 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 885 857 .ops = &clk_rcg_ops, 886 858 .flags = CLK_SET_PARENT_GATE, ··· 896 868 .enable_mask = BIT(9), 897 869 .hw.init = &(struct clk_init_data){ 898 870 .name = "gsbi11_uart_clk", 899 - .parent_names = (const char *[]){ "gsbi11_uart_src" }, 871 + .parent_hws = (const struct clk_hw*[]){ 872 + &gsbi11_uart_src.clkr.hw 873 + }, 900 874 .num_parents = 1, 901 875 .ops = &clk_branch_ops, 902 876 .flags = CLK_SET_RATE_PARENT, ··· 931 901 .enable_mask = BIT(11), 932 902 .hw.init = &(struct clk_init_data){ 933 903 .name = "gsbi12_uart_src", 934 - .parent_names = gcc_pxo_pll8, 904 + .parent_data = gcc_pxo_pll8, 935 905 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 936 906 .ops = &clk_rcg_ops, 937 907 .flags = CLK_SET_PARENT_GATE, ··· 947 917 .enable_mask = BIT(9), 948 918 .hw.init = &(struct clk_init_data){ 949 919 .name = "gsbi12_uart_clk", 950 - .parent_names = (const char *[]){ "gsbi12_uart_src" }, 920 + .parent_hws = (const struct clk_hw*[]){ 921 + &gsbi12_uart_src.clkr.hw 922 + }, 951 923 .num_parents = 1, 952 924 .ops = &clk_branch_ops, 953 925 .flags = CLK_SET_RATE_PARENT, ··· 995 963 .enable_mask = BIT(11), 996 964 .hw.init = &(struct clk_init_data){ 997 965 .name = "gsbi1_qup_src", 998 - .parent_names = gcc_pxo_pll8, 966 + .parent_data = gcc_pxo_pll8, 999 967 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1000 968 .ops = &clk_rcg_ops, 1001 969 .flags = CLK_SET_PARENT_GATE, ··· 1011 979 .enable_mask = BIT(9), 1012 980 .hw.init = &(struct clk_init_data){ 1013 981 .name = "gsbi1_qup_clk", 1014 - .parent_names = (const char *[]){ "gsbi1_qup_src" }, 982 + .parent_hws = (const struct clk_hw*[]){ 983 + &gsbi1_qup_src.clkr.hw 984 + }, 1015 985 .num_parents = 1, 1016 986 .ops = &clk_branch_ops, 1017 987 .flags = CLK_SET_RATE_PARENT, ··· 1046 1012 .enable_mask = BIT(11), 1047 1013 .hw.init = &(struct clk_init_data){ 1048 1014 .name = "gsbi2_qup_src", 1049 - .parent_names = gcc_pxo_pll8, 1015 + .parent_data = gcc_pxo_pll8, 1050 1016 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1051 1017 .ops = &clk_rcg_ops, 1052 1018 .flags = CLK_SET_PARENT_GATE, ··· 1062 1028 .enable_mask = BIT(9), 1063 1029 .hw.init = &(struct clk_init_data){ 1064 1030 .name = "gsbi2_qup_clk", 1065 - .parent_names = (const char *[]){ "gsbi2_qup_src" }, 1031 + .parent_hws = (const struct clk_hw*[]){ 1032 + &gsbi2_qup_src.clkr.hw 1033 + }, 1066 1034 .num_parents = 1, 1067 1035 .ops = &clk_branch_ops, 1068 1036 .flags = CLK_SET_RATE_PARENT, ··· 1097 1061 .enable_mask = BIT(11), 1098 1062 .hw.init = &(struct clk_init_data){ 1099 1063 .name = "gsbi3_qup_src", 1100 - .parent_names = gcc_pxo_pll8, 1064 + .parent_data = gcc_pxo_pll8, 1101 1065 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1102 1066 .ops = &clk_rcg_ops, 1103 1067 .flags = CLK_SET_PARENT_GATE, ··· 1113 1077 .enable_mask = BIT(9), 1114 1078 .hw.init = &(struct clk_init_data){ 1115 1079 .name = "gsbi3_qup_clk", 1116 - .parent_names = (const char *[]){ "gsbi3_qup_src" }, 1080 + .parent_hws = (const struct clk_hw*[]){ 1081 + &gsbi3_qup_src.clkr.hw 1082 + }, 1117 1083 .num_parents = 1, 1118 1084 .ops = &clk_branch_ops, 1119 1085 .flags = CLK_SET_RATE_PARENT, ··· 1148 1110 .enable_mask = BIT(11), 1149 1111 .hw.init = &(struct clk_init_data){ 1150 1112 .name = "gsbi4_qup_src", 1151 - .parent_names = gcc_pxo_pll8, 1113 + .parent_data = gcc_pxo_pll8, 1152 1114 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1153 1115 .ops = &clk_rcg_ops, 1154 1116 .flags = CLK_SET_PARENT_GATE, ··· 1164 1126 .enable_mask = BIT(9), 1165 1127 .hw.init = &(struct clk_init_data){ 1166 1128 .name = "gsbi4_qup_clk", 1167 - .parent_names = (const char *[]){ "gsbi4_qup_src" }, 1129 + .parent_hws = (const struct clk_hw*[]){ 1130 + &gsbi4_qup_src.clkr.hw 1131 + }, 1168 1132 .num_parents = 1, 1169 1133 .ops = &clk_branch_ops, 1170 1134 .flags = CLK_SET_RATE_PARENT, ··· 1199 1159 .enable_mask = BIT(11), 1200 1160 .hw.init = &(struct clk_init_data){ 1201 1161 .name = "gsbi5_qup_src", 1202 - .parent_names = gcc_pxo_pll8, 1162 + .parent_data = gcc_pxo_pll8, 1203 1163 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1204 1164 .ops = &clk_rcg_ops, 1205 1165 .flags = CLK_SET_PARENT_GATE, ··· 1215 1175 .enable_mask = BIT(9), 1216 1176 .hw.init = &(struct clk_init_data){ 1217 1177 .name = "gsbi5_qup_clk", 1218 - .parent_names = (const char *[]){ "gsbi5_qup_src" }, 1178 + .parent_hws = (const struct clk_hw*[]){ 1179 + &gsbi5_qup_src.clkr.hw 1180 + }, 1219 1181 .num_parents = 1, 1220 1182 .ops = &clk_branch_ops, 1221 1183 .flags = CLK_SET_RATE_PARENT, ··· 1250 1208 .enable_mask = BIT(11), 1251 1209 .hw.init = &(struct clk_init_data){ 1252 1210 .name = "gsbi6_qup_src", 1253 - .parent_names = gcc_pxo_pll8, 1211 + .parent_data = gcc_pxo_pll8, 1254 1212 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1255 1213 .ops = &clk_rcg_ops, 1256 1214 .flags = CLK_SET_PARENT_GATE, ··· 1266 1224 .enable_mask = BIT(9), 1267 1225 .hw.init = &(struct clk_init_data){ 1268 1226 .name = "gsbi6_qup_clk", 1269 - .parent_names = (const char *[]){ "gsbi6_qup_src" }, 1227 + .parent_hws = (const struct clk_hw*[]){ 1228 + &gsbi6_qup_src.clkr.hw 1229 + }, 1270 1230 .num_parents = 1, 1271 1231 .ops = &clk_branch_ops, 1272 1232 .flags = CLK_SET_RATE_PARENT, ··· 1301 1257 .enable_mask = BIT(11), 1302 1258 .hw.init = &(struct clk_init_data){ 1303 1259 .name = "gsbi7_qup_src", 1304 - .parent_names = gcc_pxo_pll8, 1260 + .parent_data = gcc_pxo_pll8, 1305 1261 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1306 1262 .ops = &clk_rcg_ops, 1307 1263 .flags = CLK_SET_PARENT_GATE, ··· 1317 1273 .enable_mask = BIT(9), 1318 1274 .hw.init = &(struct clk_init_data){ 1319 1275 .name = "gsbi7_qup_clk", 1320 - .parent_names = (const char *[]){ "gsbi7_qup_src" }, 1276 + .parent_hws = (const struct clk_hw*[]){ 1277 + &gsbi7_qup_src.clkr.hw 1278 + }, 1321 1279 .num_parents = 1, 1322 1280 .ops = &clk_branch_ops, 1323 1281 .flags = CLK_SET_RATE_PARENT, ··· 1352 1306 .enable_mask = BIT(11), 1353 1307 .hw.init = &(struct clk_init_data){ 1354 1308 .name = "gsbi8_qup_src", 1355 - .parent_names = gcc_pxo_pll8, 1309 + .parent_data = gcc_pxo_pll8, 1356 1310 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1357 1311 .ops = &clk_rcg_ops, 1358 1312 .flags = CLK_SET_PARENT_GATE, ··· 1368 1322 .enable_mask = BIT(9), 1369 1323 .hw.init = &(struct clk_init_data){ 1370 1324 .name = "gsbi8_qup_clk", 1371 - .parent_names = (const char *[]){ "gsbi8_qup_src" }, 1325 + .parent_hws = (const struct clk_hw*[]){ 1326 + &gsbi8_qup_src.clkr.hw 1327 + }, 1372 1328 .num_parents = 1, 1373 1329 .ops = &clk_branch_ops, 1374 1330 .flags = CLK_SET_RATE_PARENT, ··· 1403 1355 .enable_mask = BIT(11), 1404 1356 .hw.init = &(struct clk_init_data){ 1405 1357 .name = "gsbi9_qup_src", 1406 - .parent_names = gcc_pxo_pll8, 1358 + .parent_data = gcc_pxo_pll8, 1407 1359 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1408 1360 .ops = &clk_rcg_ops, 1409 1361 .flags = CLK_SET_PARENT_GATE, ··· 1419 1371 .enable_mask = BIT(9), 1420 1372 .hw.init = &(struct clk_init_data){ 1421 1373 .name = "gsbi9_qup_clk", 1422 - .parent_names = (const char *[]){ "gsbi9_qup_src" }, 1374 + .parent_hws = (const struct clk_hw*[]){ 1375 + &gsbi9_qup_src.clkr.hw 1376 + }, 1423 1377 .num_parents = 1, 1424 1378 .ops = &clk_branch_ops, 1425 1379 .flags = CLK_SET_RATE_PARENT, ··· 1454 1404 .enable_mask = BIT(11), 1455 1405 .hw.init = &(struct clk_init_data){ 1456 1406 .name = "gsbi10_qup_src", 1457 - .parent_names = gcc_pxo_pll8, 1407 + .parent_data = gcc_pxo_pll8, 1458 1408 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1459 1409 .ops = &clk_rcg_ops, 1460 1410 .flags = CLK_SET_PARENT_GATE, ··· 1470 1420 .enable_mask = BIT(9), 1471 1421 .hw.init = &(struct clk_init_data){ 1472 1422 .name = "gsbi10_qup_clk", 1473 - .parent_names = (const char *[]){ "gsbi10_qup_src" }, 1423 + .parent_hws = (const struct clk_hw*[]){ 1424 + &gsbi10_qup_src.clkr.hw 1425 + }, 1474 1426 .num_parents = 1, 1475 1427 .ops = &clk_branch_ops, 1476 1428 .flags = CLK_SET_RATE_PARENT, ··· 1505 1453 .enable_mask = BIT(11), 1506 1454 .hw.init = &(struct clk_init_data){ 1507 1455 .name = "gsbi11_qup_src", 1508 - .parent_names = gcc_pxo_pll8, 1456 + .parent_data = gcc_pxo_pll8, 1509 1457 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1510 1458 .ops = &clk_rcg_ops, 1511 1459 .flags = CLK_SET_PARENT_GATE, ··· 1521 1469 .enable_mask = BIT(9), 1522 1470 .hw.init = &(struct clk_init_data){ 1523 1471 .name = "gsbi11_qup_clk", 1524 - .parent_names = (const char *[]){ "gsbi11_qup_src" }, 1472 + .parent_hws = (const struct clk_hw*[]){ 1473 + &gsbi11_qup_src.clkr.hw 1474 + }, 1525 1475 .num_parents = 1, 1526 1476 .ops = &clk_branch_ops, 1527 1477 .flags = CLK_SET_RATE_PARENT, ··· 1556 1502 .enable_mask = BIT(11), 1557 1503 .hw.init = &(struct clk_init_data){ 1558 1504 .name = "gsbi12_qup_src", 1559 - .parent_names = gcc_pxo_pll8, 1505 + .parent_data = gcc_pxo_pll8, 1560 1506 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1561 1507 .ops = &clk_rcg_ops, 1562 1508 .flags = CLK_SET_PARENT_GATE, ··· 1572 1518 .enable_mask = BIT(9), 1573 1519 .hw.init = &(struct clk_init_data){ 1574 1520 .name = "gsbi12_qup_clk", 1575 - .parent_names = (const char *[]){ "gsbi12_qup_src" }, 1521 + .parent_hws = (const struct clk_hw*[]){ 1522 + &gsbi12_qup_src.clkr.hw 1523 + }, 1576 1524 .num_parents = 1, 1577 1525 .ops = &clk_branch_ops, 1578 1526 .flags = CLK_SET_RATE_PARENT, ··· 1620 1564 .enable_mask = BIT(11), 1621 1565 .hw.init = &(struct clk_init_data){ 1622 1566 .name = "gp0_src", 1623 - .parent_names = gcc_pxo_pll8_cxo, 1567 + .parent_data = gcc_pxo_pll8_cxo, 1624 1568 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1625 1569 .ops = &clk_rcg_ops, 1626 1570 .flags = CLK_SET_PARENT_GATE, ··· 1636 1580 .enable_mask = BIT(9), 1637 1581 .hw.init = &(struct clk_init_data){ 1638 1582 .name = "gp0_clk", 1639 - .parent_names = (const char *[]){ "gp0_src" }, 1583 + .parent_hws = (const struct clk_hw*[]){ 1584 + &gp0_src.clkr.hw 1585 + }, 1640 1586 .num_parents = 1, 1641 1587 .ops = &clk_branch_ops, 1642 1588 .flags = CLK_SET_RATE_PARENT, ··· 1671 1613 .enable_mask = BIT(11), 1672 1614 .hw.init = &(struct clk_init_data){ 1673 1615 .name = "gp1_src", 1674 - .parent_names = gcc_pxo_pll8_cxo, 1616 + .parent_data = gcc_pxo_pll8_cxo, 1675 1617 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1676 1618 .ops = &clk_rcg_ops, 1677 1619 .flags = CLK_SET_RATE_GATE, ··· 1687 1629 .enable_mask = BIT(9), 1688 1630 .hw.init = &(struct clk_init_data){ 1689 1631 .name = "gp1_clk", 1690 - .parent_names = (const char *[]){ "gp1_src" }, 1632 + .parent_hws = (const struct clk_hw*[]){ 1633 + &gp1_src.clkr.hw 1634 + }, 1691 1635 .num_parents = 1, 1692 1636 .ops = &clk_branch_ops, 1693 1637 .flags = CLK_SET_RATE_PARENT, ··· 1722 1662 .enable_mask = BIT(11), 1723 1663 .hw.init = &(struct clk_init_data){ 1724 1664 .name = "gp2_src", 1725 - .parent_names = gcc_pxo_pll8_cxo, 1665 + .parent_data = gcc_pxo_pll8_cxo, 1726 1666 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1727 1667 .ops = &clk_rcg_ops, 1728 1668 .flags = CLK_SET_RATE_GATE, ··· 1738 1678 .enable_mask = BIT(9), 1739 1679 .hw.init = &(struct clk_init_data){ 1740 1680 .name = "gp2_clk", 1741 - .parent_names = (const char *[]){ "gp2_src" }, 1681 + .parent_hws = (const struct clk_hw*[]){ 1682 + &gp2_src.clkr.hw 1683 + }, 1742 1684 .num_parents = 1, 1743 1685 .ops = &clk_branch_ops, 1744 1686 .flags = CLK_SET_RATE_PARENT, ··· 1776 1714 .clkr = { 1777 1715 .hw.init = &(struct clk_init_data){ 1778 1716 .name = "prng_src", 1779 - .parent_names = gcc_pxo_pll8, 1717 + .parent_data = gcc_pxo_pll8, 1780 1718 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1781 1719 .ops = &clk_rcg_ops, 1782 1720 }, ··· 1792 1730 .enable_mask = BIT(10), 1793 1731 .hw.init = &(struct clk_init_data){ 1794 1732 .name = "prng_clk", 1795 - .parent_names = (const char *[]){ "prng_src" }, 1733 + .parent_hws = (const struct clk_hw*[]){ 1734 + &prng_src.clkr.hw 1735 + }, 1796 1736 .num_parents = 1, 1797 1737 .ops = &clk_branch_ops, 1798 1738 }, ··· 1840 1776 .enable_mask = BIT(11), 1841 1777 .hw.init = &(struct clk_init_data){ 1842 1778 .name = "sdc1_src", 1843 - .parent_names = gcc_pxo_pll8, 1779 + .parent_data = gcc_pxo_pll8, 1844 1780 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1845 1781 .ops = &clk_rcg_ops, 1846 1782 }, ··· 1855 1791 .enable_mask = BIT(9), 1856 1792 .hw.init = &(struct clk_init_data){ 1857 1793 .name = "sdc1_clk", 1858 - .parent_names = (const char *[]){ "sdc1_src" }, 1794 + .parent_hws = (const struct clk_hw*[]){ 1795 + &sdc1_src.clkr.hw 1796 + }, 1859 1797 .num_parents = 1, 1860 1798 .ops = &clk_branch_ops, 1861 1799 .flags = CLK_SET_RATE_PARENT, ··· 1890 1824 .enable_mask = BIT(11), 1891 1825 .hw.init = &(struct clk_init_data){ 1892 1826 .name = "sdc2_src", 1893 - .parent_names = gcc_pxo_pll8, 1827 + .parent_data = gcc_pxo_pll8, 1894 1828 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1895 1829 .ops = &clk_rcg_ops, 1896 1830 }, ··· 1905 1839 .enable_mask = BIT(9), 1906 1840 .hw.init = &(struct clk_init_data){ 1907 1841 .name = "sdc2_clk", 1908 - .parent_names = (const char *[]){ "sdc2_src" }, 1842 + .parent_hws = (const struct clk_hw*[]){ 1843 + &sdc2_src.clkr.hw 1844 + }, 1909 1845 .num_parents = 1, 1910 1846 .ops = &clk_branch_ops, 1911 1847 .flags = CLK_SET_RATE_PARENT, ··· 1940 1872 .enable_mask = BIT(11), 1941 1873 .hw.init = &(struct clk_init_data){ 1942 1874 .name = "sdc3_src", 1943 - .parent_names = gcc_pxo_pll8, 1875 + .parent_data = gcc_pxo_pll8, 1944 1876 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1945 1877 .ops = &clk_rcg_ops, 1946 1878 }, ··· 1955 1887 .enable_mask = BIT(9), 1956 1888 .hw.init = &(struct clk_init_data){ 1957 1889 .name = "sdc3_clk", 1958 - .parent_names = (const char *[]){ "sdc3_src" }, 1890 + .parent_hws = (const struct clk_hw*[]){ 1891 + &sdc3_src.clkr.hw 1892 + }, 1959 1893 .num_parents = 1, 1960 1894 .ops = &clk_branch_ops, 1961 1895 .flags = CLK_SET_RATE_PARENT, ··· 1990 1920 .enable_mask = BIT(11), 1991 1921 .hw.init = &(struct clk_init_data){ 1992 1922 .name = "sdc4_src", 1993 - .parent_names = gcc_pxo_pll8, 1923 + .parent_data = gcc_pxo_pll8, 1994 1924 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1995 1925 .ops = &clk_rcg_ops, 1996 1926 }, ··· 2005 1935 .enable_mask = BIT(9), 2006 1936 .hw.init = &(struct clk_init_data){ 2007 1937 .name = "sdc4_clk", 2008 - .parent_names = (const char *[]){ "sdc4_src" }, 1938 + .parent_hws = (const struct clk_hw*[]){ 1939 + &sdc4_src.clkr.hw 1940 + }, 2009 1941 .num_parents = 1, 2010 1942 .ops = &clk_branch_ops, 2011 1943 .flags = CLK_SET_RATE_PARENT, ··· 2040 1968 .enable_mask = BIT(11), 2041 1969 .hw.init = &(struct clk_init_data){ 2042 1970 .name = "sdc5_src", 2043 - .parent_names = gcc_pxo_pll8, 1971 + .parent_data = gcc_pxo_pll8, 2044 1972 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2045 1973 .ops = &clk_rcg_ops, 2046 1974 }, ··· 2055 1983 .enable_mask = BIT(9), 2056 1984 .hw.init = &(struct clk_init_data){ 2057 1985 .name = "sdc5_clk", 2058 - .parent_names = (const char *[]){ "sdc5_src" }, 1986 + .parent_hws = (const struct clk_hw*[]){ 1987 + &sdc5_src.clkr.hw 1988 + }, 2059 1989 .num_parents = 1, 2060 1990 .ops = &clk_branch_ops, 2061 1991 .flags = CLK_SET_RATE_PARENT, ··· 2095 2021 .enable_mask = BIT(11), 2096 2022 .hw.init = &(struct clk_init_data){ 2097 2023 .name = "tsif_ref_src", 2098 - .parent_names = gcc_pxo_pll8, 2024 + .parent_data = gcc_pxo_pll8, 2099 2025 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2100 2026 .ops = &clk_rcg_ops, 2101 2027 .flags = CLK_SET_RATE_GATE, ··· 2111 2037 .enable_mask = BIT(9), 2112 2038 .hw.init = &(struct clk_init_data){ 2113 2039 .name = "tsif_ref_clk", 2114 - .parent_names = (const char *[]){ "tsif_ref_src" }, 2040 + .parent_hws = (const struct clk_hw*[]){ 2041 + &tsif_ref_src.clkr.hw 2042 + }, 2115 2043 .num_parents = 1, 2116 2044 .ops = &clk_branch_ops, 2117 2045 .flags = CLK_SET_RATE_PARENT, ··· 2151 2075 .enable_mask = BIT(11), 2152 2076 .hw.init = &(struct clk_init_data){ 2153 2077 .name = "usb_hs1_xcvr_src", 2154 - .parent_names = gcc_pxo_pll8, 2078 + .parent_data = gcc_pxo_pll8, 2155 2079 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2156 2080 .ops = &clk_rcg_ops, 2157 2081 .flags = CLK_SET_RATE_GATE, ··· 2167 2091 .enable_mask = BIT(9), 2168 2092 .hw.init = &(struct clk_init_data){ 2169 2093 .name = "usb_hs1_xcvr_clk", 2170 - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 2094 + .parent_hws = (const struct clk_hw*[]){ 2095 + &usb_hs1_xcvr_src.clkr.hw 2096 + }, 2171 2097 .num_parents = 1, 2172 2098 .ops = &clk_branch_ops, 2173 2099 .flags = CLK_SET_RATE_PARENT, ··· 2202 2124 .enable_mask = BIT(11), 2203 2125 .hw.init = &(struct clk_init_data){ 2204 2126 .name = "usb_hs3_xcvr_src", 2205 - .parent_names = gcc_pxo_pll8, 2127 + .parent_data = gcc_pxo_pll8, 2206 2128 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2207 2129 .ops = &clk_rcg_ops, 2208 2130 .flags = CLK_SET_RATE_GATE, ··· 2218 2140 .enable_mask = BIT(9), 2219 2141 .hw.init = &(struct clk_init_data){ 2220 2142 .name = "usb_hs3_xcvr_clk", 2221 - .parent_names = (const char *[]){ "usb_hs3_xcvr_src" }, 2143 + .parent_hws = (const struct clk_hw*[]){ 2144 + &usb_hs3_xcvr_src.clkr.hw 2145 + }, 2222 2146 .num_parents = 1, 2223 2147 .ops = &clk_branch_ops, 2224 2148 .flags = CLK_SET_RATE_PARENT, ··· 2253 2173 .enable_mask = BIT(11), 2254 2174 .hw.init = &(struct clk_init_data){ 2255 2175 .name = "usb_hs4_xcvr_src", 2256 - .parent_names = gcc_pxo_pll8, 2176 + .parent_data = gcc_pxo_pll8, 2257 2177 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2258 2178 .ops = &clk_rcg_ops, 2259 2179 .flags = CLK_SET_RATE_GATE, ··· 2269 2189 .enable_mask = BIT(9), 2270 2190 .hw.init = &(struct clk_init_data){ 2271 2191 .name = "usb_hs4_xcvr_clk", 2272 - .parent_names = (const char *[]){ "usb_hs4_xcvr_src" }, 2192 + .parent_hws = (const struct clk_hw*[]){ 2193 + &usb_hs4_xcvr_src.clkr.hw 2194 + }, 2273 2195 .num_parents = 1, 2274 2196 .ops = &clk_branch_ops, 2275 2197 .flags = CLK_SET_RATE_PARENT, ··· 2304 2222 .enable_mask = BIT(11), 2305 2223 .hw.init = &(struct clk_init_data){ 2306 2224 .name = "usb_hsic_xcvr_fs_src", 2307 - .parent_names = gcc_pxo_pll8, 2225 + .parent_data = gcc_pxo_pll8, 2308 2226 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2309 2227 .ops = &clk_rcg_ops, 2310 2228 .flags = CLK_SET_RATE_GATE, 2311 2229 }, 2312 2230 } 2313 2231 }; 2314 - 2315 - static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" }; 2316 2232 2317 2233 static struct clk_branch usb_hsic_xcvr_fs_clk = { 2318 2234 .halt_reg = 0x2fc8, ··· 2320 2240 .enable_mask = BIT(9), 2321 2241 .hw.init = &(struct clk_init_data){ 2322 2242 .name = "usb_hsic_xcvr_fs_clk", 2323 - .parent_names = usb_hsic_xcvr_fs_src_p, 2324 - .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p), 2243 + .parent_hws = (const struct clk_hw*[]){ 2244 + &usb_hsic_xcvr_fs_src.clkr.hw, 2245 + }, 2246 + .num_parents = 1, 2325 2247 .ops = &clk_branch_ops, 2326 2248 .flags = CLK_SET_RATE_PARENT, 2327 2249 }, ··· 2337 2255 .enable_reg = 0x292c, 2338 2256 .enable_mask = BIT(4), 2339 2257 .hw.init = &(struct clk_init_data){ 2340 - .parent_names = usb_hsic_xcvr_fs_src_p, 2341 - .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p), 2258 + .parent_hws = (const struct clk_hw*[]){ 2259 + &usb_hsic_xcvr_fs_src.clkr.hw, 2260 + }, 2261 + .num_parents = 1, 2342 2262 .name = "usb_hsic_system_clk", 2343 2263 .ops = &clk_branch_ops, 2344 2264 .flags = CLK_SET_RATE_PARENT, ··· 2355 2271 .enable_reg = 0x2b44, 2356 2272 .enable_mask = BIT(0), 2357 2273 .hw.init = &(struct clk_init_data){ 2358 - .parent_names = (const char *[]){ "pll14_vote" }, 2274 + .parent_hws = (const struct clk_hw*[]){ 2275 + &pll14_vote.hw 2276 + }, 2359 2277 .num_parents = 1, 2360 2278 .name = "usb_hsic_hsic_clk", 2361 2279 .ops = &clk_branch_ops, ··· 2403 2317 .enable_mask = BIT(11), 2404 2318 .hw.init = &(struct clk_init_data){ 2405 2319 .name = "usb_fs1_xcvr_fs_src", 2406 - .parent_names = gcc_pxo_pll8, 2320 + .parent_data = gcc_pxo_pll8, 2407 2321 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2408 2322 .ops = &clk_rcg_ops, 2409 2323 .flags = CLK_SET_RATE_GATE, 2410 2324 }, 2411 2325 } 2412 2326 }; 2413 - 2414 - static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; 2415 2327 2416 2328 static struct clk_branch usb_fs1_xcvr_fs_clk = { 2417 2329 .halt_reg = 0x2fcc, ··· 2419 2335 .enable_mask = BIT(9), 2420 2336 .hw.init = &(struct clk_init_data){ 2421 2337 .name = "usb_fs1_xcvr_fs_clk", 2422 - .parent_names = usb_fs1_xcvr_fs_src_p, 2423 - .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 2338 + .parent_hws = (const struct clk_hw*[]){ 2339 + &usb_fs1_xcvr_fs_src.clkr.hw, 2340 + }, 2341 + .num_parents = 1, 2424 2342 .ops = &clk_branch_ops, 2425 2343 .flags = CLK_SET_RATE_PARENT, 2426 2344 }, ··· 2436 2350 .enable_reg = 0x296c, 2437 2351 .enable_mask = BIT(4), 2438 2352 .hw.init = &(struct clk_init_data){ 2439 - .parent_names = usb_fs1_xcvr_fs_src_p, 2440 - .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 2353 + .parent_hws = (const struct clk_hw*[]){ 2354 + &usb_fs1_xcvr_fs_src.clkr.hw, 2355 + }, 2356 + .num_parents = 1, 2441 2357 .name = "usb_fs1_system_clk", 2442 2358 .ops = &clk_branch_ops, 2443 2359 .flags = CLK_SET_RATE_PARENT, ··· 2472 2384 .enable_mask = BIT(11), 2473 2385 .hw.init = &(struct clk_init_data){ 2474 2386 .name = "usb_fs2_xcvr_fs_src", 2475 - .parent_names = gcc_pxo_pll8, 2387 + .parent_data = gcc_pxo_pll8, 2476 2388 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 2477 2389 .ops = &clk_rcg_ops, 2478 2390 .flags = CLK_SET_RATE_GATE, 2479 2391 }, 2480 2392 } 2481 2393 }; 2482 - 2483 - static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; 2484 2394 2485 2395 static struct clk_branch usb_fs2_xcvr_fs_clk = { 2486 2396 .halt_reg = 0x2fcc, ··· 2488 2402 .enable_mask = BIT(9), 2489 2403 .hw.init = &(struct clk_init_data){ 2490 2404 .name = "usb_fs2_xcvr_fs_clk", 2491 - .parent_names = usb_fs2_xcvr_fs_src_p, 2492 - .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 2405 + .parent_hws = (const struct clk_hw*[]){ 2406 + &usb_fs2_xcvr_fs_src.clkr.hw, 2407 + }, 2408 + .num_parents = 1, 2493 2409 .ops = &clk_branch_ops, 2494 2410 .flags = CLK_SET_RATE_PARENT, 2495 2411 }, ··· 2506 2418 .enable_mask = BIT(4), 2507 2419 .hw.init = &(struct clk_init_data){ 2508 2420 .name = "usb_fs2_system_clk", 2509 - .parent_names = usb_fs2_xcvr_fs_src_p, 2510 - .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 2421 + .parent_hws = (const struct clk_hw*[]){ 2422 + &usb_fs2_xcvr_fs_src.clkr.hw, 2423 + }, 2424 + .num_parents = 1, 2511 2425 .ops = &clk_branch_ops, 2512 2426 .flags = CLK_SET_RATE_PARENT, 2513 2427 }, ··· 2962 2872 .enable_mask = BIT(7), 2963 2873 .hw.init = &(struct clk_init_data){ 2964 2874 .name = "ce3_src", 2965 - .parent_names = gcc_pxo_pll8_pll3, 2875 + .parent_data = gcc_pxo_pll8_pll3, 2966 2876 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3), 2967 2877 .ops = &clk_rcg_ops, 2968 2878 .flags = CLK_SET_RATE_GATE, ··· 2978 2888 .enable_mask = BIT(4), 2979 2889 .hw.init = &(struct clk_init_data){ 2980 2890 .name = "ce3_core_clk", 2981 - .parent_names = (const char *[]){ "ce3_src" }, 2891 + .parent_hws = (const struct clk_hw*[]){ 2892 + &ce3_src.clkr.hw 2893 + }, 2982 2894 .num_parents = 1, 2983 2895 .ops = &clk_branch_ops, 2984 2896 .flags = CLK_SET_RATE_PARENT, ··· 2996 2904 .enable_mask = BIT(4), 2997 2905 .hw.init = &(struct clk_init_data){ 2998 2906 .name = "ce3_h_clk", 2999 - .parent_names = (const char *[]){ "ce3_src" }, 2907 + .parent_hws = (const struct clk_hw*[]){ 2908 + &ce3_src.clkr.hw 2909 + }, 3000 2910 .num_parents = 1, 3001 2911 .ops = &clk_branch_ops, 3002 2912 .flags = CLK_SET_RATE_PARENT, ··· 3028 2934 .enable_mask = BIT(7), 3029 2935 .hw.init = &(struct clk_init_data){ 3030 2936 .name = "sata_clk_src", 3031 - .parent_names = gcc_pxo_pll8_pll3, 2937 + .parent_data = gcc_pxo_pll8_pll3, 3032 2938 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3), 3033 2939 .ops = &clk_rcg_ops, 3034 2940 .flags = CLK_SET_RATE_GATE, ··· 3044 2950 .enable_mask = BIT(4), 3045 2951 .hw.init = &(struct clk_init_data){ 3046 2952 .name = "sata_rxoob_clk", 3047 - .parent_names = (const char *[]){ "sata_clk_src" }, 2953 + .parent_hws = (const struct clk_hw*[]){ 2954 + &sata_clk_src.clkr.hw, 2955 + }, 3048 2956 .num_parents = 1, 3049 2957 .ops = &clk_branch_ops, 3050 2958 .flags = CLK_SET_RATE_PARENT, ··· 3062 2966 .enable_mask = BIT(4), 3063 2967 .hw.init = &(struct clk_init_data){ 3064 2968 .name = "sata_pmalive_clk", 3065 - .parent_names = (const char *[]){ "sata_clk_src" }, 2969 + .parent_hws = (const struct clk_hw*[]){ 2970 + &sata_clk_src.clkr.hw, 2971 + }, 3066 2972 .num_parents = 1, 3067 2973 .ops = &clk_branch_ops, 3068 2974 .flags = CLK_SET_RATE_PARENT, ··· 3080 2982 .enable_mask = BIT(4), 3081 2983 .hw.init = &(struct clk_init_data){ 3082 2984 .name = "sata_phy_ref_clk", 3083 - .parent_names = (const char *[]){ "pxo" }, 2985 + .parent_data = &(const struct clk_parent_data){ 2986 + .fw_name = "pxo", .name = "pxo_board", 2987 + }, 3084 2988 .num_parents = 1, 3085 2989 .ops = &clk_branch_ops, 3086 2990 },