Merge branch 'net-fec-do-some-cleanup-for-the-driver'

+32 -68

2 changed files

expand all

drivers

net

ethernet

freescale

fec.h

fec_main.c

+2 -28

drivers/net/ethernet/freescale/fec.h

··· 24 24 #include <linux/timecounter.h> 25 25 #include <net/xdp.h> 26 26 27 - #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 28 - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 29 - defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 27 + #if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 30 28 /* 31 29 * Just figures, Motorola would have to change the offsets for 32 30 * registers in the same peripheral device on different models ··· 239 241 __fec32 ts; 240 242 __fec16 res0[4]; 241 243 }; 242 - 243 - /* 244 - * The following definitions courtesy of commproc.h, which where 245 - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 246 - */ 247 - #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 248 - #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 249 - #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 250 - #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 251 - #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 252 - #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 253 - #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 254 - #define BD_SC_BR ((ushort)0x0020) /* Break received */ 255 - #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 256 - #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 257 - #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 258 - #define BD_SC_CD ((ushort)0x0001) /* ?? */ 259 244 260 245 /* Buffer descriptor control/status used by Ethernet receive. 261 246 */ ··· 511 530 unsigned char dsize_log2; 512 531 }; 513 532 514 - struct fec_enet_priv_txrx_info { 515 - int offset; 516 - struct page *page; 517 - struct sk_buff *skb; 518 - }; 519 - 520 533 enum { 521 534 RX_XDP_REDIRECT = 0, 522 535 RX_XDP_PASS, ··· 550 575 551 576 struct fec_enet_priv_rx_q { 552 577 struct bufdesc_prop bd; 553 - struct fec_enet_priv_txrx_info rx_skb_info[RX_RING_SIZE]; 578 + struct page *rx_buf[RX_RING_SIZE]; 554 579 555 580 /* page_pool */ 556 581 struct page_pool *page_pool; ··· 643 668 struct pm_qos_request pm_qos_req; 644 669 645 670 unsigned int tx_align; 646 - unsigned int rx_align; 647 671 648 672 /* hw interrupt coalesce */ 649 673 unsigned int rx_pkts_itr;

+30 -40

drivers/net/ethernet/freescale/fec_main.c

··· 253 253 * size bits. Other FEC hardware does not, so we need to take that into 254 254 * account when setting it. 255 255 */ 256 - #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 257 - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 258 - defined(CONFIG_ARM64) 256 + #ifndef CONFIG_M5272 259 257 #define OPT_ARCH_HAS_MAX_FL 1 260 258 #else 261 259 #define OPT_ARCH_HAS_MAX_FL 0 ··· 1010 1012 1011 1013 /* Set the last buffer to wrap */ 1012 1014 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1013 - bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1015 + bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 1014 1016 1015 1017 rxq->bd.cur = rxq->bd.base; 1016 1018 } ··· 1060 1062 1061 1063 /* Set the last buffer to wrap */ 1062 1064 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1063 - bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 1065 + bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 1064 1066 txq->dirty_tx = bdp; 1065 1067 } 1066 1068 } ··· 1655 1657 if (unlikely(!new_page)) 1656 1658 return -ENOMEM; 1657 1659 1658 - rxq->rx_skb_info[index].page = new_page; 1659 - rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM; 1660 + rxq->rx_buf[index] = new_page; 1660 1661 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1661 1662 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1662 1663 ··· 1770 1773 __fec32 cbd_bufaddr; 1771 1774 u32 sub_len = 4; 1772 1775 1773 - #if !defined(CONFIG_M5272) 1774 1776 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1775 1777 * FEC_RACC_SHIFT16 is set by default in the probe function. 1776 1778 */ ··· 1777 1781 data_start += 2; 1778 1782 sub_len += 2; 1779 1783 } 1780 - #endif 1781 1784 1782 1785 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1783 1786 /* ··· 1835 1840 ndev->stats.rx_bytes -= 2; 1836 1841 1837 1842 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1838 - page = rxq->rx_skb_info[index].page; 1843 + page = rxq->rx_buf[index]; 1839 1844 cbd_bufaddr = bdp->cbd_bufaddr; 1840 1845 if (fec_enet_update_cbd(rxq, bdp, index)) { 1841 1846 ndev->stats.rx_dropped++; ··· 2512 2517 phy_set_max_speed(phy_dev, 1000); 2513 2518 phy_remove_link_mode(phy_dev, 2514 2519 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2515 - #if !defined(CONFIG_M5272) 2516 2520 phy_support_sym_pause(phy_dev); 2517 - #endif 2518 2521 } 2519 2522 else 2520 2523 phy_set_max_speed(phy_dev, 100); ··· 2703 2710 } 2704 2711 2705 2712 /* List of registers that can be safety be read to dump them with ethtool */ 2706 - #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2707 - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2708 - defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2713 + #if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2709 2714 static __u32 fec_enet_register_version = 2; 2710 2715 static u32 fec_enet_register_offset[] = { 2711 2716 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, ··· 2777 2786 static void fec_enet_get_regs(struct net_device *ndev, 2778 2787 struct ethtool_regs *regs, void *regbuf) 2779 2788 { 2789 + u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2780 2790 struct fec_enet_private *fep = netdev_priv(ndev); 2781 2791 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2792 + u32 *reg_list = fec_enet_register_offset; 2782 2793 struct device *dev = &fep->pdev->dev; 2783 2794 u32 *buf = (u32 *)regbuf; 2784 2795 u32 i, off; 2785 2796 int ret; 2786 - #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2787 - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2788 - defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2789 - u32 *reg_list; 2790 - u32 reg_cnt; 2791 2797 2792 - if (!of_machine_is_compatible("fsl,imx6ul")) { 2793 - reg_list = fec_enet_register_offset; 2794 - reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2795 - } else { 2798 + #if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2799 + if (of_machine_is_compatible("fsl,imx6ul")) { 2796 2800 reg_list = fec_enet_register_offset_6ul; 2797 2801 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2798 2802 } 2799 - #else 2800 - /* coldfire */ 2801 - static u32 *reg_list = fec_enet_register_offset; 2802 - static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2803 2803 #endif 2804 + 2804 2805 ret = pm_runtime_resume_and_get(dev); 2805 2806 if (ret < 0) 2806 2807 return; ··· 3311 3328 for (q = 0; q < fep->num_rx_queues; q++) { 3312 3329 rxq = fep->rx_queue[q]; 3313 3330 for (i = 0; i < rxq->bd.ring_size; i++) 3314 - page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false); 3331 + page_pool_put_full_page(rxq->page_pool, rxq->rx_buf[i], 3332 + false); 3315 3333 3316 3334 for (i = 0; i < XDP_STATS_TOTAL; i++) 3317 3335 rxq->stats[i] = 0; ··· 3438 3454 return err; 3439 3455 } 3440 3456 3457 + /* Some platforms require the RX buffer must be 64 bytes alignment. 3458 + * Some platforms require 16 bytes alignment. And some platforms 3459 + * require 4 bytes alignment. But since the page pool have been 3460 + * introduced into the driver, the address of RX buffer is always 3461 + * the page address plus FEC_ENET_XDP_HEADROOM, and 3462 + * FEC_ENET_XDP_HEADROOM is 256 bytes. Therefore, this address can 3463 + * satisfy all platforms. To prevent future modifications to 3464 + * FEC_ENET_XDP_HEADROOM from ignoring this hardware limitation, a 3465 + * BUILD_BUG_ON() test has been added, which ensures that 3466 + * FEC_ENET_XDP_HEADROOM provides the required alignment. 3467 + */ 3468 + BUILD_BUG_ON(FEC_ENET_XDP_HEADROOM & 0x3f); 3469 + 3441 3470 for (i = 0; i < rxq->bd.ring_size; i++) { 3442 3471 page = page_pool_dev_alloc_pages(rxq->page_pool); 3443 3472 if (!page) ··· 3459 3462 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3460 3463 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3461 3464 3462 - rxq->rx_skb_info[i].page = page; 3463 - rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM; 3465 + rxq->rx_buf[i] = page; 3464 3466 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3465 3467 3466 3468 if (fep->bufdesc_ex) { ··· 3472 3476 3473 3477 /* Set the last buffer to wrap. */ 3474 3478 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3475 - bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3479 + bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 3476 3480 return 0; 3477 3481 3478 3482 err_alloc: ··· 3508 3512 3509 3513 /* Set the last buffer to wrap. */ 3510 3514 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3511 - bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 3515 + bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 3512 3516 3513 3517 return 0; 3514 3518 ··· 4085 4089 4086 4090 WARN_ON(dsize != (1 << dsize_log2)); 4087 4091 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4088 - fep->rx_align = 0xf; 4089 4092 fep->tx_align = 0xf; 4090 4093 #else 4091 - fep->rx_align = 0x3; 4092 4094 fep->tx_align = 0x3; 4093 4095 #endif 4094 4096 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; ··· 4175 4181 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4176 4182 } 4177 4183 4178 - if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 4184 + if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) 4179 4185 fep->tx_align = 0; 4180 - fep->rx_align = 0x3f; 4181 - } 4182 4186 4183 4187 ndev->hw_features = ndev->features; 4184 4188 ··· 4394 4402 fep->num_rx_queues = num_rx_qs; 4395 4403 fep->num_tx_queues = num_tx_qs; 4396 4404 4397 - #if !defined(CONFIG_M5272) 4398 4405 /* default enable pause frame auto negotiation */ 4399 4406 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4400 4407 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4401 - #endif 4402 4408 4403 4409 /* Select default pin state */ 4404 4410 pinctrl_pm_select_default_state(&pdev->dev);

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