Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/ras: adapt page retirement process for pmfw eeprom
read bad page data from pmfw eeprom when retirement
is triggered, use timestamp read from eeprom
Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Gangliang Xie
and committed by
Alex Deucher
72289903
42c46be2
+65
-9
+20
-9
drivers/gpu/drm/amd/ras/rascore/ras_aca.c
+20
-9
drivers/gpu/drm/amd/ras/rascore/ras_aca.c
···
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bank_ecc->de_count) {
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struct ras_bank_ecc ras_ecc = {0};
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-
ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core);
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-
ras_ecc.addr = bank_ecc->bank_info.addr;
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-
ras_ecc.ipid = bank_ecc->bank_info.ipid;
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-
ras_ecc.status = bank_ecc->bank_info.status;
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-
ras_ecc.seq_no = bank->seq_no;
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+
if (ras_fw_eeprom_supported(ras_core)) {
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ret = ras_fw_eeprom_update_record(ras_core, &ras_ecc);
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if (!ret) {
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ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core);
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ras_ecc.status = bank_ecc->bank_info.status;
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ras_ecc.seq_no = bank->seq_no;
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}
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} else {
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ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core);
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ras_ecc.addr = bank_ecc->bank_info.addr;
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ras_ecc.ipid = bank_ecc->bank_info.ipid;
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ras_ecc.status = bank_ecc->bank_info.status;
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ras_ecc.seq_no = bank->seq_no;
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}
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-
if (ras_core_gpu_in_reset(ras_core))
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ras_umc_log_bad_bank_pending(ras_core, &ras_ecc);
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-
else
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ras_umc_log_bad_bank(ras_core, &ras_ecc);
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+
if (!ret) {
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if (ras_core_gpu_in_reset(ras_core))
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ras_umc_log_bad_bank_pending(ras_core, &ras_ecc);
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else
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ras_umc_log_bad_bank(ras_core, &ras_ecc);
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}
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}
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aca_report_ecc_info(ras_core,
+40
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+40
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
···
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#include "ras.h"
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+
#define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */
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+
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void ras_fw_init_feature_flags(struct ras_core_context *ras_core)
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{
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struct ras_mp1 *mp1 = &ras_core->ras_mp1;
···
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return 0;
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return ras_core->ras_fw_eeprom.ras_num_recs;
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+
}
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int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
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struct ras_bank_ecc *ras_ecc)
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{
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struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
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int ret, retry = 20;
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u32 recs_num_new = control->ras_num_recs;
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+
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do {
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/* 1000ms timeout is long enough, smu_get_badpage_count won't
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* return -EBUSY before timeout.
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*/
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ret = ras_fw_get_badpage_count(ras_core,
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&recs_num_new, RAS_SMU_MESSAGE_TIMEOUT_MS);
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if (!ret &&
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(recs_num_new == control->ras_num_recs)) {
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/* record number update in PMFW needs some time,
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* smu_get_badpage_count may return immediately without
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* count update, sleep for a while and retry again.
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*/
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msleep(50);
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retry--;
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} else {
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break;
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}
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} while (retry);
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if (ret)
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return ret;
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+
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if (recs_num_new > control->ras_num_recs)
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ret = ras_fw_eeprom_read_idx(ras_core, 0,
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ras_ecc, control->ras_num_recs, 1);
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else
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ret = -EINVAL;
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return ret;
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}
+2
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+2
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+3
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
+3
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
···
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ACA_ADDR_2_ERR_ADDR(bank->addr), ACA_IPID_2_UMC_INST(bank->ipid),
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&nps_addr, bank->nps, record);
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if (ras_fw_eeprom_supported(ras_core) && bank->ts)
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record->ts = bank->ts;
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+
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lookup_bad_pages_in_a_row(ras_core, record,
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bank->nps, NULL, 0, bank->seq_no, true);
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