Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/tidss: Add OLDI bridge support
The AM62x and AM62Px SoCs feature 2 OLDI TXes each, which makes it
possible to connect them in dual-link or cloned single-link OLDI display
modes. The current OLDI support in tidss_dispc.c can only support for
a single OLDI TX, connected to a VP and doesn't really support
configuration of OLDIs in the other modes. The current OLDI support in
tidss_dispc.c also works on the principle that the OLDI output can only
be served by one, and only one, DSS video-port. This isn't the case in
the AM62Px SoC, where there are 2 DSS controllers present that share the
OLDI TXes.
Having their own devicetree and their own bridge entity will help
support the various display modes and sharing possiblilities of the OLDI
hardware.
For all these reasons, add support for the OLDI TXes as DRM bridges.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
Tested-by: Michael Walle <mwalle@kernel.org> # on am67a
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://lore.kernel.org/r/20250528122544.817829-5-aradhya.bhatia@linux.dev
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
authored by
Aradhya Bhatia
and committed by
Tomi Valkeinen
7246e092
d18bf712
+699
-2
+2
-1
drivers/gpu/drm/tidss/Makefile
+2
-1
drivers/gpu/drm/tidss/Makefile
+23
-1
drivers/gpu/drm/tidss/tidss_dispc.c
+23
-1
drivers/gpu/drm/tidss/tidss_dispc.c
···
566
566
return ioread32(base + reg);
567
567
}
568
568
569
+
int tidss_configure_oldi(struct tidss_device *tidss, u32 hw_videoport,
570
+
u32 oldi_cfg)
571
+
{
572
+
u32 count = 0;
573
+
u32 oldi_reset_bit = BIT(5 + hw_videoport);
574
+
575
+
dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
576
+
577
+
while (!(oldi_reset_bit & dispc_read(tidss->dispc, DSS_SYSSTATUS)) &&
578
+
count < 10000)
579
+
count++;
580
+
581
+
if (!(oldi_reset_bit & dispc_read(tidss->dispc, DSS_SYSSTATUS)))
582
+
return -ETIMEDOUT;
583
+
584
+
return 0;
585
+
}
586
+
587
+
void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport)
588
+
{
589
+
dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
590
+
}
591
+
569
592
/*
570
593
* TRM gives bitfields as start:end, where start is the higher bit
571
594
* number. For example 7:0
···
1441
1418
* Calculate the percentage difference between the requested pixel clock rate
1442
1419
* and the effective rate resulting from calculating the clock divider value.
1443
1420
*/
1444
-
static
1445
1421
unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
1446
1422
{
1447
1423
int r = rate / 100, rr = real_rate / 100;
+5
drivers/gpu/drm/tidss/tidss_dispc.h
+5
drivers/gpu/drm/tidss/tidss_dispc.h
···
101
101
extern const struct dispc_features dispc_am65x_feats;
102
102
extern const struct dispc_features dispc_j721e_feats;
103
103
104
+
int tidss_configure_oldi(struct tidss_device *tidss, u32 hw_videoport,
105
+
u32 oldi_cfg);
106
+
void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport);
107
+
unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate);
108
+
104
109
void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
105
110
dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
106
111
+14
drivers/gpu/drm/tidss/tidss_dispc_regs.h
+14
drivers/gpu/drm/tidss/tidss_dispc_regs.h
···
226
226
#define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */
227
227
#define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */
228
228
229
+
/* OLDI Config Bits (DISPC_VP_DSS_OLDI_CFG) */
230
+
#define OLDI_ENABLE BIT(0)
231
+
#define OLDI_MAP (BIT(1) | BIT(2) | BIT(3))
232
+
#define OLDI_SRC BIT(4)
233
+
#define OLDI_CLONE_MODE BIT(5)
234
+
#define OLDI_MASTERSLAVE BIT(6)
235
+
#define OLDI_DEPOL BIT(7)
236
+
#define OLDI_MSB BIT(8)
237
+
#define OLDI_LBEN BIT(9)
238
+
#define OLDI_LBDATA BIT(10)
239
+
#define OLDI_DUALMODESYNC BIT(11)
240
+
#define OLDI_SOFTRST BIT(12)
241
+
#define OLDI_TPATCFG BIT(13)
242
+
229
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/* LVDS Format values for OLDI_MAP field in DISPC_VP_OLDI_CFG register */
230
244
enum oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 };
231
245
+9
drivers/gpu/drm/tidss/tidss_drv.c
+9
drivers/gpu/drm/tidss/tidss_drv.c
···
24
24
#include "tidss_drv.h"
25
25
#include "tidss_kms.h"
26
26
#include "tidss_irq.h"
27
+
#include "tidss_oldi.h"
27
28
28
29
/* Power management */
29
30
···
148
147
return ret;
149
148
}
150
149
150
+
ret = tidss_oldi_init(tidss);
151
+
if (ret)
152
+
return dev_err_probe(dev, ret, "failed to init OLDI\n");
153
+
151
154
pm_runtime_enable(dev);
152
155
153
156
pm_runtime_set_autosuspend_delay(dev, 1000);
···
208
203
pm_runtime_dont_use_autosuspend(dev);
209
204
pm_runtime_disable(dev);
210
205
206
+
tidss_oldi_deinit(tidss);
207
+
211
208
return ret;
212
209
}
213
210
···
233
226
#endif
234
227
pm_runtime_dont_use_autosuspend(dev);
235
228
pm_runtime_disable(dev);
229
+
230
+
tidss_oldi_deinit(tidss);
236
231
237
232
/* devm allocated dispc goes away with the dev so mark it NULL */
238
233
dispc_remove(tidss);
+5
drivers/gpu/drm/tidss/tidss_drv.h
+5
drivers/gpu/drm/tidss/tidss_drv.h
···
11
11
12
12
#define TIDSS_MAX_PORTS 4
13
13
#define TIDSS_MAX_PLANES 4
14
+
#define TIDSS_MAX_OLDI_TXES 2
14
15
15
16
typedef u32 dispc_irq_t;
17
+
struct tidss_oldi;
16
18
17
19
struct tidss_device {
18
20
struct drm_device ddev; /* DRM device for DSS */
···
28
26
29
27
unsigned int num_planes;
30
28
struct drm_plane *planes[TIDSS_MAX_PLANES];
29
+
30
+
unsigned int num_oldis;
31
+
struct tidss_oldi *oldis[TIDSS_MAX_OLDI_TXES];
31
32
32
33
unsigned int irq;
33
34
+598
drivers/gpu/drm/tidss/tidss_oldi.c
+598
drivers/gpu/drm/tidss/tidss_oldi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Copyright (C) 2025 - Texas Instruments Incorporated
4
+
*
5
+
* Aradhya Bhatia <a-bhatia1@ti.com>
6
+
*/
7
+
8
+
#include <linux/clk.h>
9
+
#include <linux/of.h>
10
+
#include <linux/of_graph.h>
11
+
#include <linux/mfd/syscon.h>
12
+
#include <linux/media-bus-format.h>
13
+
#include <linux/regmap.h>
14
+
15
+
#include <drm/drm_atomic_helper.h>
16
+
#include <drm/drm_bridge.h>
17
+
#include <drm/drm_of.h>
18
+
19
+
#include "tidss_dispc.h"
20
+
#include "tidss_dispc_regs.h"
21
+
#include "tidss_oldi.h"
22
+
23
+
struct tidss_oldi {
24
+
struct tidss_device *tidss;
25
+
struct device *dev;
26
+
27
+
struct drm_bridge bridge;
28
+
struct drm_bridge *next_bridge;
29
+
30
+
enum tidss_oldi_link_type link_type;
31
+
const struct oldi_bus_format *bus_format;
32
+
u32 oldi_instance;
33
+
int companion_instance; /* -1 when OLDI TX operates in Single-Link */
34
+
u32 parent_vp;
35
+
36
+
struct clk *serial;
37
+
struct regmap *io_ctrl;
38
+
};
39
+
40
+
struct oldi_bus_format {
41
+
u32 bus_fmt;
42
+
u32 data_width;
43
+
enum oldi_mode_reg_val oldi_mode_reg_val;
44
+
u32 input_bus_fmt;
45
+
};
46
+
47
+
static const struct oldi_bus_format oldi_bus_formats[] = {
48
+
{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, SPWG_18, MEDIA_BUS_FMT_RGB666_1X18 },
49
+
{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, SPWG_24, MEDIA_BUS_FMT_RGB888_1X24 },
50
+
{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, JEIDA_24, MEDIA_BUS_FMT_RGB888_1X24 },
51
+
};
52
+
53
+
#define OLDI_IDLE_CLK_HZ 25000000 /*25 MHz */
54
+
55
+
static inline struct tidss_oldi *
56
+
drm_bridge_to_tidss_oldi(struct drm_bridge *bridge)
57
+
{
58
+
return container_of(bridge, struct tidss_oldi, bridge);
59
+
}
60
+
61
+
static int tidss_oldi_bridge_attach(struct drm_bridge *bridge,
62
+
struct drm_encoder *encoder,
63
+
enum drm_bridge_attach_flags flags)
64
+
{
65
+
struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
66
+
67
+
if (!oldi->next_bridge) {
68
+
dev_err(oldi->dev,
69
+
"%s: OLDI%u Failure attach next bridge\n",
70
+
__func__, oldi->oldi_instance);
71
+
return -ENODEV;
72
+
}
73
+
74
+
if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
75
+
dev_err(oldi->dev,
76
+
"%s: OLDI%u DRM_BRIDGE_ATTACH_NO_CONNECTOR is mandatory.\n",
77
+
__func__, oldi->oldi_instance);
78
+
return -EINVAL;
79
+
}
80
+
81
+
return drm_bridge_attach(encoder, oldi->next_bridge, bridge, flags);
82
+
}
83
+
84
+
static int
85
+
tidss_oldi_set_serial_clk(struct tidss_oldi *oldi, unsigned long rate)
86
+
{
87
+
unsigned long new_rate;
88
+
int ret;
89
+
90
+
ret = clk_set_rate(oldi->serial, rate);
91
+
if (ret) {
92
+
dev_err(oldi->dev,
93
+
"OLDI%u: failed to set serial clk rate to %lu Hz\n",
94
+
oldi->oldi_instance, rate);
95
+
return ret;
96
+
}
97
+
98
+
new_rate = clk_get_rate(oldi->serial);
99
+
100
+
if (dispc_pclk_diff(rate, new_rate) > 5)
101
+
dev_warn(oldi->dev,
102
+
"OLDI%u Clock rate %lu differs over 5%% from requested %lu\n",
103
+
oldi->oldi_instance, new_rate, rate);
104
+
105
+
dev_dbg(oldi->dev, "OLDI%u: new rate %lu Hz (requested %lu Hz)\n",
106
+
oldi->oldi_instance, clk_get_rate(oldi->serial), rate);
107
+
108
+
return 0;
109
+
}
110
+
111
+
static void tidss_oldi_tx_power(struct tidss_oldi *oldi, bool enable)
112
+
{
113
+
u32 mask;
114
+
115
+
/*
116
+
* The power control bits are Active Low, and remain powered off by
117
+
* default. That is, the bits are set to 1. To power on the OLDI TXes,
118
+
* the bits must be cleared to 0. Since there are cases where not all
119
+
* OLDI TXes are being used, the power logic selectively powers them
120
+
* on.
121
+
* Setting the variable 'val' to particular bit masks, makes sure that
122
+
* the undesired OLDI TXes remain powered off.
123
+
*/
124
+
125
+
if (enable) {
126
+
switch (oldi->link_type) {
127
+
case OLDI_MODE_SINGLE_LINK:
128
+
/* Power-on only the required OLDI TX's IO*/
129
+
mask = OLDI_PWRDOWN_TX(oldi->oldi_instance) | OLDI_PWRDN_BG;
130
+
break;
131
+
case OLDI_MODE_CLONE_SINGLE_LINK:
132
+
case OLDI_MODE_DUAL_LINK:
133
+
/* Power-on both the OLDI TXes' IOs */
134
+
mask = OLDI_PWRDOWN_TX(oldi->oldi_instance) |
135
+
OLDI_PWRDOWN_TX(oldi->companion_instance) |
136
+
OLDI_PWRDN_BG;
137
+
break;
138
+
default:
139
+
/*
140
+
* This code execution should never reach here as any
141
+
* OLDI with an unsupported OLDI mode would never get
142
+
* registered in the first place.
143
+
* However, power-off the OLDI in concern just in case.
144
+
*/
145
+
mask = OLDI_PWRDOWN_TX(oldi->oldi_instance);
146
+
enable = false;
147
+
break;
148
+
}
149
+
} else {
150
+
switch (oldi->link_type) {
151
+
case OLDI_MODE_CLONE_SINGLE_LINK:
152
+
case OLDI_MODE_DUAL_LINK:
153
+
mask = OLDI_PWRDOWN_TX(oldi->oldi_instance) |
154
+
OLDI_PWRDOWN_TX(oldi->companion_instance) |
155
+
OLDI_PWRDN_BG;
156
+
break;
157
+
case OLDI_MODE_SINGLE_LINK:
158
+
default:
159
+
mask = OLDI_PWRDOWN_TX(oldi->oldi_instance);
160
+
break;
161
+
}
162
+
}
163
+
164
+
regmap_update_bits(oldi->io_ctrl, OLDI_PD_CTRL, mask, enable ? 0 : mask);
165
+
}
166
+
167
+
static int tidss_oldi_config(struct tidss_oldi *oldi)
168
+
{
169
+
const struct oldi_bus_format *bus_fmt = NULL;
170
+
u32 oldi_cfg = 0;
171
+
int ret;
172
+
173
+
bus_fmt = oldi->bus_format;
174
+
175
+
/*
176
+
* MASTERSLAVE and SRC bits of OLDI Config are always set to 0.
177
+
*/
178
+
179
+
if (bus_fmt->data_width == 24)
180
+
oldi_cfg |= OLDI_MSB;
181
+
else if (bus_fmt->data_width != 18)
182
+
dev_warn(oldi->dev,
183
+
"OLDI%u: DSS port width %d not supported\n",
184
+
oldi->oldi_instance, bus_fmt->data_width);
185
+
186
+
oldi_cfg |= OLDI_DEPOL;
187
+
188
+
oldi_cfg = (oldi_cfg & (~OLDI_MAP)) | (bus_fmt->oldi_mode_reg_val << 1);
189
+
190
+
oldi_cfg |= OLDI_SOFTRST;
191
+
192
+
oldi_cfg |= OLDI_ENABLE;
193
+
194
+
switch (oldi->link_type) {
195
+
case OLDI_MODE_SINGLE_LINK:
196
+
/* All configuration is done for this mode. */
197
+
break;
198
+
199
+
case OLDI_MODE_CLONE_SINGLE_LINK:
200
+
oldi_cfg |= OLDI_CLONE_MODE;
201
+
break;
202
+
203
+
case OLDI_MODE_DUAL_LINK:
204
+
/* data-mapping field also indicates dual-link mode */
205
+
oldi_cfg |= BIT(3);
206
+
oldi_cfg |= OLDI_DUALMODESYNC;
207
+
break;
208
+
209
+
default:
210
+
dev_err(oldi->dev, "OLDI%u: Unsupported mode.\n",
211
+
oldi->oldi_instance);
212
+
return -EINVAL;
213
+
}
214
+
215
+
ret = tidss_configure_oldi(oldi->tidss, oldi->parent_vp, oldi_cfg);
216
+
if (ret == -ETIMEDOUT)
217
+
dev_warn(oldi->dev, "OLDI%u: timeout waiting for OLDI reset done.\n",
218
+
oldi->oldi_instance);
219
+
220
+
return ret;
221
+
}
222
+
223
+
static void tidss_oldi_atomic_pre_enable(struct drm_bridge *bridge,
224
+
struct drm_atomic_state *state)
225
+
{
226
+
struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
227
+
struct drm_connector *connector;
228
+
struct drm_connector_state *conn_state;
229
+
struct drm_crtc_state *crtc_state;
230
+
struct drm_display_mode *mode;
231
+
232
+
if (oldi->link_type == OLDI_MODE_SECONDARY_CLONE_SINGLE_LINK)
233
+
return;
234
+
235
+
connector = drm_atomic_get_new_connector_for_encoder(state,
236
+
bridge->encoder);
237
+
if (WARN_ON(!connector))
238
+
return;
239
+
240
+
conn_state = drm_atomic_get_new_connector_state(state, connector);
241
+
if (WARN_ON(!conn_state))
242
+
return;
243
+
244
+
crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
245
+
if (WARN_ON(!crtc_state))
246
+
return;
247
+
248
+
mode = &crtc_state->adjusted_mode;
249
+
250
+
/* Configure the OLDI params*/
251
+
tidss_oldi_config(oldi);
252
+
253
+
/* Set the OLDI serial clock (7 times the pixel clock) */
254
+
tidss_oldi_set_serial_clk(oldi, mode->clock * 7 * 1000);
255
+
256
+
/* Enable OLDI IO power */
257
+
tidss_oldi_tx_power(oldi, true);
258
+
}
259
+
260
+
static void tidss_oldi_atomic_post_disable(struct drm_bridge *bridge,
261
+
struct drm_atomic_state *state)
262
+
{
263
+
struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
264
+
265
+
if (oldi->link_type == OLDI_MODE_SECONDARY_CLONE_SINGLE_LINK)
266
+
return;
267
+
268
+
/* Disable OLDI IO power */
269
+
tidss_oldi_tx_power(oldi, false);
270
+
271
+
/* Set the OLDI serial clock to IDLE Frequency */
272
+
tidss_oldi_set_serial_clk(oldi, OLDI_IDLE_CLK_HZ);
273
+
274
+
/* Clear OLDI Config */
275
+
tidss_disable_oldi(oldi->tidss, oldi->parent_vp);
276
+
}
277
+
278
+
#define MAX_INPUT_SEL_FORMATS 1
279
+
280
+
static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
281
+
struct drm_bridge_state *bridge_state,
282
+
struct drm_crtc_state *crtc_state,
283
+
struct drm_connector_state *conn_state,
284
+
u32 output_fmt,
285
+
unsigned int *num_input_fmts)
286
+
{
287
+
struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
288
+
u32 *input_fmts;
289
+
int i;
290
+
291
+
*num_input_fmts = 0;
292
+
293
+
for (i = 0; i < ARRAY_SIZE(oldi_bus_formats); i++)
294
+
if (oldi_bus_formats[i].bus_fmt == output_fmt)
295
+
break;
296
+
297
+
if (i == ARRAY_SIZE(oldi_bus_formats))
298
+
return NULL;
299
+
300
+
input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
301
+
GFP_KERNEL);
302
+
if (!input_fmts)
303
+
return NULL;
304
+
305
+
*num_input_fmts = 1;
306
+
input_fmts[0] = oldi_bus_formats[i].input_bus_fmt;
307
+
oldi->bus_format = &oldi_bus_formats[i];
308
+
309
+
return input_fmts;
310
+
}
311
+
312
+
static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
313
+
.attach = tidss_oldi_bridge_attach,
314
+
.atomic_pre_enable = tidss_oldi_atomic_pre_enable,
315
+
.atomic_post_disable = tidss_oldi_atomic_post_disable,
316
+
.atomic_get_input_bus_fmts = tidss_oldi_atomic_get_input_bus_fmts,
317
+
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
318
+
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
319
+
.atomic_reset = drm_atomic_helper_bridge_reset,
320
+
};
321
+
322
+
static int get_oldi_mode(struct device_node *oldi_tx, int *companion_instance)
323
+
{
324
+
struct device_node *companion;
325
+
struct device_node *port0, *port1;
326
+
u32 companion_reg;
327
+
bool secondary_oldi = false;
328
+
int pixel_order;
329
+
330
+
/*
331
+
* Find if the OLDI is paired with another OLDI for combined OLDI
332
+
* operation (dual-link or clone).
333
+
*/
334
+
companion = of_parse_phandle(oldi_tx, "ti,companion-oldi", 0);
335
+
if (!companion)
336
+
/*
337
+
* The OLDI TX does not have a companion, nor is it a
338
+
* secondary OLDI. It will operate independently.
339
+
*/
340
+
return OLDI_MODE_SINGLE_LINK;
341
+
342
+
if (of_property_read_u32(companion, "reg", &companion_reg))
343
+
return OLDI_MODE_UNSUPPORTED;
344
+
345
+
if (companion_reg > (TIDSS_MAX_OLDI_TXES - 1))
346
+
/* Invalid companion OLDI reg value. */
347
+
return OLDI_MODE_UNSUPPORTED;
348
+
349
+
*companion_instance = (int)companion_reg;
350
+
351
+
if (of_property_read_bool(oldi_tx, "ti,secondary-oldi"))
352
+
secondary_oldi = true;
353
+
354
+
/*
355
+
* We need to work out if the sink is expecting us to function in
356
+
* dual-link mode. We do this by looking at the DT port nodes, the
357
+
* OLDI TX ports are connected to. If they are marked as expecting
358
+
* even pixels and odd pixels, then we need to enable dual-link.
359
+
*/
360
+
port0 = of_graph_get_port_by_id(oldi_tx, 1);
361
+
port1 = of_graph_get_port_by_id(companion, 1);
362
+
pixel_order = drm_of_lvds_get_dual_link_pixel_order(port0, port1);
363
+
of_node_put(port0);
364
+
of_node_put(port1);
365
+
of_node_put(companion);
366
+
367
+
switch (pixel_order) {
368
+
case -EINVAL:
369
+
/*
370
+
* The dual-link properties were not found in at least
371
+
* one of the sink nodes. Since 2 OLDI ports are present
372
+
* in the DT, it can be safely assumed that the required
373
+
* configuration is Clone Mode.
374
+
*/
375
+
return (secondary_oldi ? OLDI_MODE_SECONDARY_CLONE_SINGLE_LINK :
376
+
OLDI_MODE_CLONE_SINGLE_LINK);
377
+
378
+
case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
379
+
/*
380
+
* Primary OLDI can only support "ODD" pixels. So, from its
381
+
* perspective, the pixel order has to be ODD-EVEN.
382
+
*/
383
+
return (secondary_oldi ? OLDI_MODE_UNSUPPORTED :
384
+
OLDI_MODE_DUAL_LINK);
385
+
386
+
case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
387
+
/*
388
+
* Secondary OLDI can only support "EVEN" pixels. So, from its
389
+
* perspective, the pixel order has to be EVEN-ODD.
390
+
*/
391
+
return (secondary_oldi ? OLDI_MODE_SECONDARY_DUAL_LINK :
392
+
OLDI_MODE_UNSUPPORTED);
393
+
394
+
default:
395
+
return OLDI_MODE_UNSUPPORTED;
396
+
}
397
+
}
398
+
399
+
static int get_parent_dss_vp(struct device_node *oldi_tx, u32 *parent_vp)
400
+
{
401
+
struct device_node *ep, *dss_port;
402
+
int ret;
403
+
404
+
ep = of_graph_get_endpoint_by_regs(oldi_tx, OLDI_INPUT_PORT, -1);
405
+
if (ep) {
406
+
dss_port = of_graph_get_remote_port(ep);
407
+
if (!dss_port) {
408
+
ret = -ENODEV;
409
+
goto err_return_ep_port;
410
+
}
411
+
412
+
ret = of_property_read_u32(dss_port, "reg", parent_vp);
413
+
414
+
of_node_put(dss_port);
415
+
err_return_ep_port:
416
+
of_node_put(ep);
417
+
return ret;
418
+
}
419
+
420
+
return -ENODEV;
421
+
}
422
+
423
+
static const struct drm_bridge_timings default_tidss_oldi_timings = {
424
+
.input_bus_flags = DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
425
+
| DRM_BUS_FLAG_DE_HIGH,
426
+
};
427
+
428
+
void tidss_oldi_deinit(struct tidss_device *tidss)
429
+
{
430
+
for (int i = 0; i < tidss->num_oldis; i++) {
431
+
if (tidss->oldis[i]) {
432
+
drm_bridge_remove(&tidss->oldis[i]->bridge);
433
+
tidss->oldis[i] = NULL;
434
+
}
435
+
}
436
+
}
437
+
438
+
int tidss_oldi_init(struct tidss_device *tidss)
439
+
{
440
+
struct tidss_oldi *oldi;
441
+
struct device_node *child;
442
+
struct drm_bridge *bridge;
443
+
u32 parent_vp, oldi_instance;
444
+
int companion_instance = -1;
445
+
enum tidss_oldi_link_type link_type = OLDI_MODE_UNSUPPORTED;
446
+
struct device_node *oldi_parent;
447
+
int ret = 0;
448
+
449
+
tidss->num_oldis = 0;
450
+
451
+
oldi_parent = of_get_child_by_name(tidss->dev->of_node, "oldi-transmitters");
452
+
if (!oldi_parent)
453
+
/* Return gracefully */
454
+
return 0;
455
+
456
+
for_each_available_child_of_node(oldi_parent, child) {
457
+
ret = get_parent_dss_vp(child, &parent_vp);
458
+
if (ret) {
459
+
if (ret == -ENODEV) {
460
+
/*
461
+
* ENODEV means that this particular OLDI node
462
+
* is not connected with the DSS, which is not
463
+
* a harmful case. There could be another OLDI
464
+
* which may still be connected.
465
+
* Continue to search for that.
466
+
*/
467
+
ret = 0;
468
+
continue;
469
+
}
470
+
goto err_put_node;
471
+
}
472
+
473
+
ret = of_property_read_u32(child, "reg", &oldi_instance);
474
+
if (ret)
475
+
goto err_put_node;
476
+
477
+
/*
478
+
* Now that it's confirmed that OLDI is connected with DSS,
479
+
* let's continue getting the OLDI sinks ahead and other OLDI
480
+
* properties.
481
+
*/
482
+
bridge = devm_drm_of_get_bridge(tidss->dev, child,
483
+
OLDI_OUTPUT_PORT, 0);
484
+
if (IS_ERR(bridge)) {
485
+
/*
486
+
* Either there was no OLDI sink in the devicetree, or
487
+
* the OLDI sink has not been added yet. In any case,
488
+
* return.
489
+
* We don't want to have an OLDI node connected to DSS
490
+
* but not to any sink.
491
+
*/
492
+
ret = dev_err_probe(tidss->dev, PTR_ERR(bridge),
493
+
"no panel/bridge for OLDI%u.\n",
494
+
oldi_instance);
495
+
goto err_put_node;
496
+
}
497
+
498
+
link_type = get_oldi_mode(child, &companion_instance);
499
+
if (link_type == OLDI_MODE_UNSUPPORTED) {
500
+
ret = dev_err_probe(tidss->dev, -EINVAL,
501
+
"OLDI%u: Unsupported OLDI connection.\n",
502
+
oldi_instance);
503
+
goto err_put_node;
504
+
} else if ((link_type == OLDI_MODE_SECONDARY_CLONE_SINGLE_LINK) ||
505
+
(link_type == OLDI_MODE_CLONE_SINGLE_LINK)) {
506
+
/*
507
+
* The OLDI driver cannot support OLDI clone mode
508
+
* properly at present.
509
+
* The clone mode requires 2 working encoder-bridge
510
+
* pipelines, generating from the same crtc. The DRM
511
+
* framework does not support this at present. If
512
+
* there were to be, say, 2 OLDI sink bridges each
513
+
* connected to an OLDI TXes, they couldn't both be
514
+
* supported simultaneously.
515
+
* This driver still has some code pertaining to OLDI
516
+
* clone mode configuration in DSS hardware for future,
517
+
* when there is a better infrastructure in the DRM
518
+
* framework to support 2 encoder-bridge pipelines
519
+
* simultaneously.
520
+
* Till that time, this driver shall error out if it
521
+
* detects a clone mode configuration.
522
+
*/
523
+
ret = dev_err_probe(tidss->dev, -EOPNOTSUPP,
524
+
"The OLDI driver does not support Clone Mode at present.\n");
525
+
goto err_put_node;
526
+
} else if (link_type == OLDI_MODE_SECONDARY_DUAL_LINK) {
527
+
/*
528
+
* This is the secondary OLDI node, which serves as a
529
+
* companion to the primary OLDI, when it is configured
530
+
* for the dual-link mode. Since the primary OLDI will
531
+
* be a part of bridge chain, no need to put this one
532
+
* too. Continue onto the next OLDI node.
533
+
*/
534
+
continue;
535
+
}
536
+
537
+
oldi = devm_kzalloc(tidss->dev, sizeof(*oldi), GFP_KERNEL);
538
+
if (!oldi) {
539
+
ret = -ENOMEM;
540
+
goto err_put_node;
541
+
}
542
+
543
+
oldi->parent_vp = parent_vp;
544
+
oldi->oldi_instance = oldi_instance;
545
+
oldi->companion_instance = companion_instance;
546
+
oldi->link_type = link_type;
547
+
oldi->dev = tidss->dev;
548
+
oldi->next_bridge = bridge;
549
+
550
+
/*
551
+
* Only the primary OLDI needs to reference the io-ctrl system
552
+
* registers, and the serial clock.
553
+
* We don't require a check for secondary OLDI in dual-link mode
554
+
* because the driver will not create a drm_bridge instance.
555
+
* But the driver will need to create a drm_bridge instance,
556
+
* for secondary OLDI in clone mode (once it is supported).
557
+
*/
558
+
if (link_type != OLDI_MODE_SECONDARY_CLONE_SINGLE_LINK) {
559
+
oldi->io_ctrl = syscon_regmap_lookup_by_phandle(child,
560
+
"ti,oldi-io-ctrl");
561
+
if (IS_ERR(oldi->io_ctrl)) {
562
+
ret = dev_err_probe(oldi->dev, PTR_ERR(oldi->io_ctrl),
563
+
"OLDI%u: syscon_regmap_lookup_by_phandle failed.\n",
564
+
oldi_instance);
565
+
goto err_put_node;
566
+
}
567
+
568
+
oldi->serial = of_clk_get_by_name(child, "serial");
569
+
if (IS_ERR(oldi->serial)) {
570
+
ret = dev_err_probe(oldi->dev, PTR_ERR(oldi->serial),
571
+
"OLDI%u: Failed to get serial clock.\n",
572
+
oldi_instance);
573
+
goto err_put_node;
574
+
}
575
+
}
576
+
577
+
/* Register the bridge. */
578
+
oldi->bridge.of_node = child;
579
+
oldi->bridge.driver_private = oldi;
580
+
oldi->bridge.funcs = &tidss_oldi_bridge_funcs;
581
+
oldi->bridge.timings = &default_tidss_oldi_timings;
582
+
583
+
tidss->oldis[tidss->num_oldis++] = oldi;
584
+
oldi->tidss = tidss;
585
+
586
+
drm_bridge_add(&oldi->bridge);
587
+
}
588
+
589
+
of_node_put(child);
590
+
of_node_put(oldi_parent);
591
+
592
+
return 0;
593
+
594
+
err_put_node:
595
+
of_node_put(child);
596
+
of_node_put(oldi_parent);
597
+
return ret;
598
+
}
+43
drivers/gpu/drm/tidss/tidss_oldi.h
+43
drivers/gpu/drm/tidss/tidss_oldi.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* Copyright (C) 2025 - Texas Instruments Incorporated
4
+
*
5
+
* Aradhya Bhatia <a-bhatia1@ti.com>
6
+
*/
7
+
8
+
#ifndef __TIDSS_OLDI_H__
9
+
#define __TIDSS_OLDI_H__
10
+
11
+
#include "tidss_drv.h"
12
+
13
+
struct tidss_oldi;
14
+
15
+
/* OLDI PORTS */
16
+
#define OLDI_INPUT_PORT 0
17
+
#define OLDI_OUTPUT_PORT 1
18
+
19
+
/* Control MMR Registers */
20
+
21
+
/* Register offsets */
22
+
#define OLDI_PD_CTRL 0x100
23
+
#define OLDI_LB_CTRL 0x104
24
+
25
+
/* Power control bits */
26
+
#define OLDI_PWRDOWN_TX(n) BIT(n)
27
+
28
+
/* LVDS Bandgap reference Enable/Disable */
29
+
#define OLDI_PWRDN_BG BIT(8)
30
+
31
+
enum tidss_oldi_link_type {
32
+
OLDI_MODE_UNSUPPORTED,
33
+
OLDI_MODE_SINGLE_LINK,
34
+
OLDI_MODE_CLONE_SINGLE_LINK,
35
+
OLDI_MODE_SECONDARY_CLONE_SINGLE_LINK,
36
+
OLDI_MODE_DUAL_LINK,
37
+
OLDI_MODE_SECONDARY_DUAL_LINK,
38
+
};
39
+
40
+
int tidss_oldi_init(struct tidss_device *tidss);
41
+
void tidss_oldi_deinit(struct tidss_device *tidss);
42
+
43
+
#endif /* __TIDSS_OLDI_H__ */