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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: samsung: exynos5260: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+28
-13
+28
-13
drivers/clk/samsung/clk-exynos5260.c
+28
-13
drivers/clk/samsung/clk-exynos5260.c
···
15
15
16
16
#include <dt-bindings/clock/exynos5260-clk.h>
17
17
18
+
/* NOTE: Must be equal to the last clock ID increased by one */
19
+
#define CLKS_NR_TOP (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
20
+
#define CLKS_NR_EGL (EGL_DOUT_EGL1 + 1)
21
+
#define CLKS_NR_KFC (KFC_DOUT_KFC1 + 1)
22
+
#define CLKS_NR_MIF (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
23
+
#define CLKS_NR_G3D (G3D_CLK_G3D + 1)
24
+
#define CLKS_NR_AUD (AUD_SCLK_I2S + 1)
25
+
#define CLKS_NR_MFC (MFC_CLK_SMMU2_MFCM0 + 1)
26
+
#define CLKS_NR_GSCL (GSCL_SCLK_CSIS0_WRAP + 1)
27
+
#define CLKS_NR_FSYS (FSYS_PHYCLK_USBHOST20 + 1)
28
+
#define CLKS_NR_PERI (PERI_SCLK_PCM1 + 1)
29
+
#define CLKS_NR_DISP (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
30
+
#define CLKS_NR_G2D (G2D_CLK_SMMU3_G2D + 1)
31
+
#define CLKS_NR_ISP (ISP_SCLK_UART_EXT + 1)
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+
18
33
/*
19
34
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
20
35
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
···
150
135
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
151
136
.gate_clks = aud_gate_clks,
152
137
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
153
-
.nr_clk_ids = AUD_NR_CLK,
138
+
.nr_clk_ids = CLKS_NR_AUD,
154
139
.clk_regs = aud_clk_regs,
155
140
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
156
141
};
···
340
325
.nr_div_clks = ARRAY_SIZE(disp_div_clks),
341
326
.gate_clks = disp_gate_clks,
342
327
.nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
343
-
.nr_clk_ids = DISP_NR_CLK,
328
+
.nr_clk_ids = CLKS_NR_DISP,
344
329
.clk_regs = disp_clk_regs,
345
330
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
346
331
};
···
404
389
.nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
405
390
.div_clks = egl_div_clks,
406
391
.nr_div_clks = ARRAY_SIZE(egl_div_clks),
407
-
.nr_clk_ids = EGL_NR_CLK,
392
+
.nr_clk_ids = CLKS_NR_EGL,
408
393
.clk_regs = egl_clk_regs,
409
394
.nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
410
395
};
···
504
489
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
505
490
.gate_clks = fsys_gate_clks,
506
491
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
507
-
.nr_clk_ids = FSYS_NR_CLK,
492
+
.nr_clk_ids = CLKS_NR_FSYS,
508
493
.clk_regs = fsys_clk_regs,
509
494
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
510
495
};
···
595
580
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
596
581
.gate_clks = g2d_gate_clks,
597
582
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
598
-
.nr_clk_ids = G2D_NR_CLK,
583
+
.nr_clk_ids = CLKS_NR_G2D,
599
584
.clk_regs = g2d_clk_regs,
600
585
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
601
586
};
···
658
643
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
659
644
.gate_clks = g3d_gate_clks,
660
645
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
661
-
.nr_clk_ids = G3D_NR_CLK,
646
+
.nr_clk_ids = CLKS_NR_G3D,
662
647
.clk_regs = g3d_clk_regs,
663
648
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
664
649
};
···
791
776
.nr_div_clks = ARRAY_SIZE(gscl_div_clks),
792
777
.gate_clks = gscl_gate_clks,
793
778
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
794
-
.nr_clk_ids = GSCL_NR_CLK,
779
+
.nr_clk_ids = CLKS_NR_GSCL,
795
780
.clk_regs = gscl_clk_regs,
796
781
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
797
782
};
···
910
895
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
911
896
.gate_clks = isp_gate_clks,
912
897
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
913
-
.nr_clk_ids = ISP_NR_CLK,
898
+
.nr_clk_ids = CLKS_NR_ISP,
914
899
.clk_regs = isp_clk_regs,
915
900
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
916
901
};
···
974
959
.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
975
960
.div_clks = kfc_div_clks,
976
961
.nr_div_clks = ARRAY_SIZE(kfc_div_clks),
977
-
.nr_clk_ids = KFC_NR_CLK,
962
+
.nr_clk_ids = CLKS_NR_KFC,
978
963
.clk_regs = kfc_clk_regs,
979
964
.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
980
965
};
···
1030
1015
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
1031
1016
.gate_clks = mfc_gate_clks,
1032
1017
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
1033
-
.nr_clk_ids = MFC_NR_CLK,
1018
+
.nr_clk_ids = CLKS_NR_MFC,
1034
1019
.clk_regs = mfc_clk_regs,
1035
1020
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
1036
1021
};
···
1179
1164
.nr_div_clks = ARRAY_SIZE(mif_div_clks),
1180
1165
.gate_clks = mif_gate_clks,
1181
1166
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1182
-
.nr_clk_ids = MIF_NR_CLK,
1167
+
.nr_clk_ids = CLKS_NR_MIF,
1183
1168
.clk_regs = mif_clk_regs,
1184
1169
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1185
1170
};
···
1385
1370
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
1386
1371
.gate_clks = peri_gate_clks,
1387
1372
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
1388
-
.nr_clk_ids = PERI_NR_CLK,
1373
+
.nr_clk_ids = CLKS_NR_PERI,
1389
1374
.clk_regs = peri_clk_regs,
1390
1375
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
1391
1376
};
···
1841
1826
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
1842
1827
.fixed_clks = fixed_rate_clks,
1843
1828
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
1844
-
.nr_clk_ids = TOP_NR_CLK,
1829
+
.nr_clk_ids = CLKS_NR_TOP,
1845
1830
.clk_regs = top_clk_regs,
1846
1831
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1847
1832
};