drm/amdgpu: Add audio method to register block

+4 -6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 914 914 amdgpu_wreg64_t pcie_wreg64; 915 915 amdgpu_rreg64_ext_t pcie_rreg64_ext; 916 916 amdgpu_wreg64_ext_t pcie_wreg64_ext; 917 - /* protects concurrent ENDPOINT (audio) register access */ 918 - spinlock_t audio_endpt_idx_lock; 919 - amdgpu_block_rreg_t audio_endpt_rreg; 920 - amdgpu_block_wreg_t audio_endpt_wreg; 921 917 struct amdgpu_doorbell doorbell; 922 918 923 919 /* clock/pll info */ ··· 1328 1332 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1329 1333 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1330 1334 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1331 - #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1332 - #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1335 + #define RREG32_AUDIO_ENDPT(block, reg) \ 1336 + amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1337 + #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1338 + amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1333 1339 #define WREG32_P(reg, val, mask) \ 1334 1340 do { \ 1335 1341 uint32_t tmp_ = RREG32(reg); \

-45

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 959 959 BUG(); 960 960 } 961 961 962 - /** 963 - * amdgpu_block_invalid_rreg - dummy reg read function 964 - * 965 - * @adev: amdgpu_device pointer 966 - * @block: offset of instance 967 - * @reg: offset of register 968 - * 969 - * Dummy register read function. Used for register blocks 970 - * that certain asics don't have (all asics). 971 - * Returns the value in the register. 972 - */ 973 - static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, 974 - uint32_t block, uint32_t reg) 975 - { 976 - dev_err(adev->dev, 977 - "Invalid callback to read register 0x%04X in block 0x%04X\n", 978 - reg, block); 979 - BUG(); 980 - return 0; 981 - } 982 - 983 - /** 984 - * amdgpu_block_invalid_wreg - dummy reg write function 985 - * 986 - * @adev: amdgpu_device pointer 987 - * @block: offset of instance 988 - * @reg: offset of register 989 - * @v: value to write to the register 990 - * 991 - * Dummy register read function. Used for register blocks 992 - * that certain asics don't have (all asics). 993 - */ 994 - static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, 995 - uint32_t block, 996 - uint32_t reg, uint32_t v) 997 - { 998 - dev_err(adev->dev, 999 - "Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", 1000 - reg, block, v); 1001 - BUG(); 1002 - } 1003 - 1004 962 static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev) 1005 963 { 1006 964 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) ··· 3800 3842 adev->pcie_wreg64 = &amdgpu_invalid_wreg64; 3801 3843 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; 3802 3844 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; 3803 - adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; 3804 - adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; 3805 3845 3806 3846 dev_info( 3807 3847 adev->dev, ··· 3845 3889 3846 3890 spin_lock_init(&adev->mmio_idx_lock); 3847 3891 spin_lock_init(&adev->pcie_idx_lock); 3848 - spin_lock_init(&adev->audio_endpt_idx_lock); 3849 3892 spin_lock_init(&adev->mm_stats.lock); 3850 3893 spin_lock_init(&adev->virt.rlcg_reg_lock); 3851 3894 spin_lock_init(&adev->wb.lock);

+26

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

··· 54 54 spin_lock_init(&adev->reg.se_cac.lock); 55 55 adev->reg.se_cac.rreg = NULL; 56 56 adev->reg.se_cac.wreg = NULL; 57 + 58 + spin_lock_init(&adev->reg.audio_endpt.lock); 59 + adev->reg.audio_endpt.rreg = NULL; 60 + adev->reg.audio_endpt.wreg = NULL; 57 61 } 58 62 59 63 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) ··· 155 151 return; 156 152 } 157 153 adev->reg.se_cac.wreg(adev, reg, v); 154 + } 155 + 156 + uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, 157 + uint32_t reg) 158 + { 159 + if (!adev->reg.audio_endpt.rreg) { 160 + dev_err_once(adev->dev, 161 + "AUDIO_ENDPT register read not supported\n"); 162 + return 0; 163 + } 164 + return adev->reg.audio_endpt.rreg(adev, block, reg); 165 + } 166 + 167 + void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, 168 + uint32_t reg, uint32_t v) 169 + { 170 + if (!adev->reg.audio_endpt.wreg) { 171 + dev_err_once(adev->dev, 172 + "AUDIO_ENDPT register write not supported\n"); 173 + return; 174 + } 175 + adev->reg.audio_endpt.wreg(adev, block, reg, v); 158 176 } 159 177 160 178 /*

+16 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

··· 32 32 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); 33 33 typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); 34 34 35 + typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, 36 + uint32_t); 37 + typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, 38 + uint32_t); 39 + 35 40 struct amdgpu_reg_ind { 36 41 spinlock_t lock; 37 42 amdgpu_rreg_t rreg; 38 43 amdgpu_wreg_t wreg; 44 + }; 45 + 46 + struct amdgpu_reg_ind_blk { 47 + spinlock_t lock; 48 + amdgpu_block_rreg_t rreg; 49 + amdgpu_block_wreg_t wreg; 39 50 }; 40 51 41 52 struct amdgpu_reg_access { ··· 55 44 struct amdgpu_reg_ind didt; 56 45 struct amdgpu_reg_ind gc_cac; 57 46 struct amdgpu_reg_ind se_cac; 47 + struct amdgpu_reg_ind_blk audio_endpt; 58 48 }; 59 49 60 50 void amdgpu_reg_access_init(struct amdgpu_device *adev); ··· 71 59 uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 72 60 void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 73 61 uint32_t v); 62 + uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, 63 + uint32_t reg); 64 + void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, 65 + uint32_t reg, uint32_t v); 74 66 75 67 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); 76 68 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); ··· 84 68 85 69 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); 86 70 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); 87 - 88 - typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, 89 - uint32_t); 90 - typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, 91 - uint32_t); 92 71 93 72 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, 94 73 uint32_t acc_flags);

+6 -6

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

··· 175 175 unsigned long flags; 176 176 u32 r; 177 177 178 - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 178 + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 179 179 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 180 180 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 181 - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 181 + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 182 182 183 183 return r; 184 184 } ··· 188 188 { 189 189 unsigned long flags; 190 190 191 - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 191 + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 192 192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 193 193 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 194 - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 194 + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 195 195 } 196 196 197 197 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) ··· 2750 2750 { 2751 2751 struct amdgpu_device *adev = ip_block->adev; 2752 2752 2753 - adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; 2754 - adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; 2753 + adev->reg.audio_endpt.rreg = &dce_v10_0_audio_endpt_rreg; 2754 + adev->reg.audio_endpt.wreg = &dce_v10_0_audio_endpt_wreg; 2755 2755 2756 2756 dce_v10_0_set_display_funcs(adev); 2757 2757

+6 -6

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

··· 138 138 unsigned long flags; 139 139 u32 r; 140 140 141 - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 141 + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 142 142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 143 143 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 144 - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 144 + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 145 145 146 146 return r; 147 147 } ··· 151 151 { 152 152 unsigned long flags; 153 153 154 - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 154 + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 155 155 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 156 156 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 157 157 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 158 - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 158 + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 159 159 } 160 160 161 161 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) ··· 2697 2697 { 2698 2698 struct amdgpu_device *adev = ip_block->adev; 2699 2699 2700 - adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2701 - adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2700 + adev->reg.audio_endpt.rreg = &dce_v6_0_audio_endpt_rreg; 2701 + adev->reg.audio_endpt.wreg = &dce_v6_0_audio_endpt_wreg; 2702 2702 2703 2703 dce_v6_0_set_display_funcs(adev); 2704 2704

+6 -6

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

··· 126 126 unsigned long flags; 127 127 u32 r; 128 128 129 - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 129 + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 130 130 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 131 131 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 132 - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 132 + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 133 133 134 134 return r; 135 135 } ··· 139 139 { 140 140 unsigned long flags; 141 141 142 - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 142 + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 143 143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 144 144 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 145 - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 145 + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 146 146 } 147 147 148 148 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) ··· 2655 2655 { 2656 2656 struct amdgpu_device *adev = ip_block->adev; 2657 2657 2658 - adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; 2659 - adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; 2658 + adev->reg.audio_endpt.rreg = &dce_v8_0_audio_endpt_rreg; 2659 + adev->reg.audio_endpt.wreg = &dce_v8_0_audio_endpt_wreg; 2660 2660 2661 2661 dce_v8_0_set_display_funcs(adev); 2662 2662

+2 -2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 5968 5968 adev->mode_info.funcs = &dm_display_funcs; 5969 5969 5970 5970 /* 5971 - * Note: Do NOT change adev->audio_endpt_rreg and 5972 - * adev->audio_endpt_wreg because they are initialised in 5971 + * Note: Do NOT change adev->reg.audio_endpt.rreg and 5972 + * adev->reg.audio_endpt.wreg because they are initialised in 5973 5973 * amdgpu_device_init() 5974 5974 */ 5975 5975 #if defined(CONFIG_DEBUG_KERNEL_DC)

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