+2 -6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 914 914 amdgpu_wreg64_t pcie_wreg64; 915 915 amdgpu_rreg64_ext_t pcie_rreg64_ext; 916 916 amdgpu_wreg64_ext_t pcie_wreg64_ext; 917 917 - /* protects concurrent se_cac register access */ 918 918 - spinlock_t se_cac_idx_lock; 919 919 - amdgpu_rreg_t se_cac_rreg; 920 920 - amdgpu_wreg_t se_cac_wreg; 921 917 /* protects concurrent ENDPOINT (audio) register access */ 922 918 spinlock_t audio_endpt_idx_lock; 923 919 amdgpu_block_rreg_t audio_endpt_rreg; ··· 1330 1334 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1331 1335 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1332 1336 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1333 1333 - #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1334 1334 - #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1337 1337 + #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1338 1338 + #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1335 1339 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1336 1340 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1337 1341 #define WREG32_P(reg, val, mask) \

-1

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 3889 3889 3890 3890 spin_lock_init(&adev->mmio_idx_lock); 3891 3891 spin_lock_init(&adev->pcie_idx_lock); 3892 3892 - spin_lock_init(&adev->se_cac_idx_lock); 3893 3892 spin_lock_init(&adev->audio_endpt_idx_lock); 3894 3893 spin_lock_init(&adev->mm_stats.lock); 3895 3894 spin_lock_init(&adev->virt.rlcg_reg_lock);

+24

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

reviewed

··· 50 50 spin_lock_init(&adev->reg.gc_cac.lock); 51 51 adev->reg.gc_cac.rreg = NULL; 52 52 adev->reg.gc_cac.wreg = NULL; 53 53 + 54 54 + spin_lock_init(&adev->reg.se_cac.lock); 55 55 + adev->reg.se_cac.rreg = NULL; 56 56 + adev->reg.se_cac.wreg = NULL; 53 57 } 54 58 55 59 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) ··· 131 127 return; 132 128 } 133 129 adev->reg.gc_cac.wreg(adev, reg, v); 130 130 + } 131 131 + 132 132 + uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg) 133 133 + { 134 134 + if (!adev->reg.se_cac.rreg) { 135 135 + dev_err_once(adev->dev, "SE_CAC register read not supported\n"); 136 136 + return 0; 137 137 + } 138 138 + return adev->reg.se_cac.rreg(adev, reg); 139 139 + } 140 140 + 141 141 + void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 142 142 + uint32_t v) 143 143 + { 144 144 + if (!adev->reg.se_cac.wreg) { 145 145 + dev_err_once(adev->dev, 146 146 + "SE_CAC register write not supported\n"); 147 147 + return; 148 148 + } 149 149 + adev->reg.se_cac.wreg(adev, reg, v); 134 150 } 135 151 136 152 /*

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

reviewed

··· 43 43 struct amdgpu_reg_ind uvd_ctx; 44 44 struct amdgpu_reg_ind didt; 45 45 struct amdgpu_reg_ind gc_cac; 46 46 + struct amdgpu_reg_ind se_cac; 46 47 }; 47 48 48 49 void amdgpu_reg_access_init(struct amdgpu_device *adev); ··· 55 54 void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 56 55 uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 57 56 void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 57 57 + uint32_t v); 58 58 + uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 59 59 + void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 58 60 uint32_t v); 59 61 60 62 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t);

+6 -6

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 320 320 unsigned long flags; 321 321 u32 r; 322 322 323 323 - spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 323 323 + spin_lock_irqsave(&adev->reg.se_cac.lock, flags); 324 324 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 325 325 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 326 326 - spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 326 326 + spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); 327 327 return r; 328 328 } 329 329 ··· 331 331 { 332 332 unsigned long flags; 333 333 334 334 - spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 334 334 + spin_lock_irqsave(&adev->reg.se_cac.lock, flags); 335 335 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 336 336 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 337 337 - spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 337 337 + spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); 338 338 } 339 339 340 340 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) ··· 975 975 adev->reg.didt.wreg = &soc15_didt_wreg; 976 976 adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg; 977 977 adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg; 978 978 - adev->se_cac_rreg = &soc15_se_cac_rreg; 979 979 - adev->se_cac_wreg = &soc15_se_cac_wreg; 978 978 + adev->reg.se_cac.rreg = &soc15_se_cac_rreg; 979 979 + adev->reg.se_cac.wreg = &soc15_se_cac_wreg; 980 980 981 981 adev->rev_id = amdgpu_device_get_rev_id(adev); 982 982 adev->external_rev_id = 0xFF;