Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6:
mtd/nand_ids: Fix buswidth
mtd/m25p80: fix test for end of loop
mtd/m25p80: retlen is never NULL
MIPS: Fix gen_nand probe structures contents
gen_nand: Test if nr_chips field is valid
BFIN: Fix gen_nand probe structures contents
nand/denali: move all hardware initialization work to denali_hw_init
nand/denali: Add a page check in denali_read_page & denali_read_page_raw
nand/denali: use cpu_relax() while waiting for hardware interrupt
nand/denali: change read_status function method
nand/denali: Fixed check patch warnings
ARM: Fix gen_nand probe structures contents
mtd/nand_base: fix kernel-doc warnings & typos
nand/denali: use dev_xx debug function to replace nand_dbg_print and some printk
nand/denali: Fixed handle ECC error bugs
nand/denali: use iowrite32() to replace denali_write32()
nand/denali: Fixed probe function bugs
+211
-331
+1
arch/arm/mach-ixp4xx/ixdp425-setup.c
+1
arch/arm/mach-ixp4xx/ixdp425-setup.c
+1
arch/arm/mach-mx3/mach-qong.c
+1
arch/arm/mach-mx3/mach-qong.c
+1
arch/arm/mach-orion5x/ts78xx-setup.c
+1
arch/arm/mach-orion5x/ts78xx-setup.c
+1
arch/blackfin/mach-bf537/boards/stamp.c
+1
arch/blackfin/mach-bf537/boards/stamp.c
+1
arch/blackfin/mach-bf561/boards/acvilon.c
+1
arch/blackfin/mach-bf561/boards/acvilon.c
+1
arch/mips/pnx833x/common/platform.c
+1
arch/mips/pnx833x/common/platform.c
+5
-9
drivers/mtd/devices/m25p80.c
+5
-9
drivers/mtd/devices/m25p80.c
···
347
347
spi_message_add_tail(&t[1], &m);
348
348
349
349
/* Byte count starts at zero. */
350
-
if (retlen)
351
-
*retlen = 0;
350
+
*retlen = 0;
352
351
353
352
mutex_lock(&flash->lock);
354
353
···
393
394
dev_name(&flash->spi->dev), __func__, "to",
394
395
(u32)to, len);
395
396
396
-
if (retlen)
397
-
*retlen = 0;
397
+
*retlen = 0;
398
398
399
399
/* sanity checks */
400
400
if (!len)
···
464
466
465
467
spi_sync(flash->spi, &m);
466
468
467
-
if (retlen)
468
-
*retlen += m.actual_length - m25p_cmdsz(flash);
469
+
*retlen += m.actual_length - m25p_cmdsz(flash);
469
470
}
470
471
}
471
472
···
482
485
size_t actual;
483
486
int cmd_sz, ret;
484
487
485
-
if (retlen)
486
-
*retlen = 0;
488
+
*retlen = 0;
487
489
488
490
/* sanity checks */
489
491
if (!len)
···
793
797
break;
794
798
}
795
799
796
-
if (plat_id)
800
+
if (i < ARRAY_SIZE(m25p_ids) - 1)
797
801
id = plat_id;
798
802
else
799
803
dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
+194
-303
drivers/mtd/nand/denali.c
+194
-303
drivers/mtd/nand/denali.c
···
56
56
INTR_STATUS0__ERASE_COMP)
57
57
58
58
/* indicates whether or not the internal value for the flash bank is
59
-
valid or not */
59
+
* valid or not */
60
60
#define CHIP_SELECT_INVALID -1
61
61
62
62
#define SUPPORT_8BITECC 1
···
71
71
#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
72
72
73
73
/* These constants are defined by the driver to enable common driver
74
-
configuration options. */
74
+
* configuration options. */
75
75
#define SPARE_ACCESS 0x41
76
76
#define MAIN_ACCESS 0x42
77
77
#define MAIN_SPARE_ACCESS 0x43
···
97
97
98
98
99
99
/* these are static lookup tables that give us easy access to
100
-
registers in the NAND controller.
100
+
* registers in the NAND controller.
101
101
*/
102
102
static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
103
103
INTR_STATUS1,
···
119
119
INTR_STATUS2__RST_COMP,
120
120
INTR_STATUS3__RST_COMP};
121
121
122
-
/* specifies the debug level of the driver */
123
-
static int nand_debug_level;
124
-
125
122
/* forward declarations */
126
123
static void clear_interrupts(struct denali_nand_info *denali);
127
124
static uint32_t wait_for_irq(struct denali_nand_info *denali,
···
126
129
static void denali_irq_enable(struct denali_nand_info *denali,
127
130
uint32_t int_mask);
128
131
static uint32_t read_interrupt_status(struct denali_nand_info *denali);
129
-
130
-
#define DEBUG_DENALI 0
131
-
132
-
/* This is a wrapper for writing to the denali registers.
133
-
* this allows us to create debug information so we can
134
-
* observe how the driver is programming the device.
135
-
* it uses standard linux convention for (val, addr) */
136
-
static void denali_write32(uint32_t value, void *addr)
137
-
{
138
-
iowrite32(value, addr);
139
-
140
-
#if DEBUG_DENALI
141
-
printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value,
142
-
(uint32_t)((uint32_t)addr & 0x1fff));
143
-
#endif
144
-
}
145
132
146
133
/* Certain operations for the denali NAND controller use
147
134
* an indexed mode to read/write data. The operation is
···
136
155
static void index_addr(struct denali_nand_info *denali,
137
156
uint32_t address, uint32_t data)
138
157
{
139
-
denali_write32(address, denali->flash_mem);
140
-
denali_write32(data, denali->flash_mem + 0x10);
158
+
iowrite32(address, denali->flash_mem);
159
+
iowrite32(data, denali->flash_mem + 0x10);
141
160
}
142
161
143
162
/* Perform an indexed read of the device */
144
163
static void index_addr_read_data(struct denali_nand_info *denali,
145
164
uint32_t address, uint32_t *pdata)
146
165
{
147
-
denali_write32(address, denali->flash_mem);
166
+
iowrite32(address, denali->flash_mem);
148
167
*pdata = ioread32(denali->flash_mem + 0x10);
149
168
}
150
169
···
169
188
/* initialize the data buffer to store status */
170
189
reset_buf(denali);
171
190
172
-
/* initiate a device status read */
173
-
cmd = MODE_11 | BANK(denali->flash_bank);
174
-
index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
175
-
denali_write32(cmd | STATUS_CYCLE, denali->flash_mem);
176
-
177
-
/* update buffer with status value */
178
-
write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
179
-
180
-
#if DEBUG_DENALI
181
-
printk(KERN_INFO "device reporting status value of 0x%2x\n",
182
-
denali->buf.buf[0]);
183
-
#endif
191
+
cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
192
+
if (cmd)
193
+
write_byte_to_buf(denali, NAND_STATUS_WP);
194
+
else
195
+
write_byte_to_buf(denali, 0);
184
196
}
185
197
186
198
/* resets a specific device connected to the core */
···
187
213
clear_interrupts(denali);
188
214
189
215
bank = device_reset_banks[denali->flash_bank];
190
-
denali_write32(bank, denali->flash_reg + DEVICE_RESET);
216
+
iowrite32(bank, denali->flash_reg + DEVICE_RESET);
191
217
192
218
irq_status = wait_for_irq(denali, irq_mask);
193
219
194
220
if (irq_status & operation_timeout[denali->flash_bank])
195
-
printk(KERN_ERR "reset bank failed.\n");
221
+
dev_err(&denali->dev->dev, "reset bank failed.\n");
196
222
}
197
223
198
224
/* Reset the flash controller */
···
200
226
{
201
227
uint32_t i;
202
228
203
-
nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
229
+
dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
204
230
__FILE__, __LINE__, __func__);
205
231
206
232
for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
207
-
denali_write32(reset_complete[i] | operation_timeout[i],
233
+
iowrite32(reset_complete[i] | operation_timeout[i],
208
234
denali->flash_reg + intr_status_addresses[i]);
209
235
210
236
for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
211
-
denali_write32(device_reset_banks[i],
237
+
iowrite32(device_reset_banks[i],
212
238
denali->flash_reg + DEVICE_RESET);
213
239
while (!(ioread32(denali->flash_reg +
214
-
intr_status_addresses[i]) &
240
+
intr_status_addresses[i]) &
215
241
(reset_complete[i] | operation_timeout[i])))
216
-
;
242
+
cpu_relax();
217
243
if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
218
244
operation_timeout[i])
219
-
nand_dbg_print(NAND_DBG_WARN,
245
+
dev_dbg(&denali->dev->dev,
220
246
"NAND Reset operation timed out on bank %d\n", i);
221
247
}
222
248
223
249
for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
224
-
denali_write32(reset_complete[i] | operation_timeout[i],
250
+
iowrite32(reset_complete[i] | operation_timeout[i],
225
251
denali->flash_reg + intr_status_addresses[i]);
226
252
227
253
return PASS;
···
254
280
uint16_t acc_clks;
255
281
uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
256
282
257
-
nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
283
+
dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
258
284
__FILE__, __LINE__, __func__);
259
285
260
286
en_lo = CEIL_DIV(Trp[mode], CLK_X);
···
291
317
acc_clks++;
292
318
293
319
if ((data_invalid - acc_clks * CLK_X) < 2)
294
-
nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n",
320
+
dev_warn(&denali->dev->dev, "%s, Line %d: Warning!\n",
295
321
__FILE__, __LINE__);
296
322
297
323
addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
···
319
345
(ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
320
346
acc_clks = 6;
321
347
322
-
denali_write32(acc_clks, denali->flash_reg + ACC_CLKS);
323
-
denali_write32(re_2_we, denali->flash_reg + RE_2_WE);
324
-
denali_write32(re_2_re, denali->flash_reg + RE_2_RE);
325
-
denali_write32(we_2_re, denali->flash_reg + WE_2_RE);
326
-
denali_write32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
327
-
denali_write32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
328
-
denali_write32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
329
-
denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
348
+
iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
349
+
iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
350
+
iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
351
+
iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
352
+
iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
353
+
iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
354
+
iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
355
+
iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
330
356
}
331
357
332
358
/* queries the NAND device to see what ONFI modes it supports. */
···
361
387
{
362
388
if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
363
389
/* Set timing register values according to datasheet */
364
-
denali_write32(5, denali->flash_reg + ACC_CLKS);
365
-
denali_write32(20, denali->flash_reg + RE_2_WE);
366
-
denali_write32(12, denali->flash_reg + WE_2_RE);
367
-
denali_write32(14, denali->flash_reg + ADDR_2_DATA);
368
-
denali_write32(3, denali->flash_reg + RDWR_EN_LO_CNT);
369
-
denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT);
370
-
denali_write32(2, denali->flash_reg + CS_SETUP_CNT);
390
+
iowrite32(5, denali->flash_reg + ACC_CLKS);
391
+
iowrite32(20, denali->flash_reg + RE_2_WE);
392
+
iowrite32(12, denali->flash_reg + WE_2_RE);
393
+
iowrite32(14, denali->flash_reg + ADDR_2_DATA);
394
+
iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
395
+
iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
396
+
iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
371
397
}
372
398
}
373
399
···
379
405
/* spare area size for some kind of Toshiba NAND device */
380
406
if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
381
407
(ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
382
-
denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
408
+
iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
383
409
tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
384
410
ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
385
-
denali_write32(tmp,
411
+
iowrite32(tmp,
386
412
denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
387
413
#if SUPPORT_15BITECC
388
-
denali_write32(15, denali->flash_reg + ECC_CORRECTION);
414
+
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
389
415
#elif SUPPORT_8BITECC
390
-
denali_write32(8, denali->flash_reg + ECC_CORRECTION);
416
+
iowrite32(8, denali->flash_reg + ECC_CORRECTION);
391
417
#endif
392
418
}
393
419
}
···
400
426
switch (device_id) {
401
427
case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
402
428
case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
403
-
denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK);
404
-
denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
405
-
denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
429
+
iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
430
+
iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
431
+
iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
406
432
main_size = 4096 *
407
433
ioread32(denali->flash_reg + DEVICES_CONNECTED);
408
434
spare_size = 224 *
409
435
ioread32(denali->flash_reg + DEVICES_CONNECTED);
410
-
denali_write32(main_size,
436
+
iowrite32(main_size,
411
437
denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
412
-
denali_write32(spare_size,
438
+
iowrite32(spare_size,
413
439
denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
414
-
denali_write32(0, denali->flash_reg + DEVICE_WIDTH);
440
+
iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
415
441
#if SUPPORT_15BITECC
416
-
denali_write32(15, denali->flash_reg + ECC_CORRECTION);
442
+
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
417
443
#elif SUPPORT_8BITECC
418
-
denali_write32(8, denali->flash_reg + ECC_CORRECTION);
444
+
iowrite32(8, denali->flash_reg + ECC_CORRECTION);
419
445
#endif
420
446
break;
421
447
default:
422
-
nand_dbg_print(NAND_DBG_WARN,
448
+
dev_warn(&denali->dev->dev,
423
449
"Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
424
450
"Will use default parameter values instead.\n",
425
451
device_id);
···
427
453
}
428
454
429
455
/* determines how many NAND chips are connected to the controller. Note for
430
-
Intel CE4100 devices we don't support more than one device.
456
+
* Intel CE4100 devices we don't support more than one device.
431
457
*/
432
458
static void find_valid_banks(struct denali_nand_info *denali)
433
459
{
···
441
467
index_addr_read_data(denali,
442
468
(uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
443
469
444
-
nand_dbg_print(NAND_DBG_DEBUG,
470
+
dev_dbg(&denali->dev->dev,
445
471
"Return 1st ID for bank[%d]: %x\n", i, id[i]);
446
472
447
473
if (i == 0) {
···
461
487
* Multichip support is not enabled.
462
488
*/
463
489
if (denali->total_used_banks != 1) {
464
-
printk(KERN_ERR "Sorry, Intel CE4100 only supports "
490
+
dev_err(&denali->dev->dev,
491
+
"Sorry, Intel CE4100 only supports "
465
492
"a single NAND device.\n");
466
493
BUG();
467
494
}
468
495
}
469
-
nand_dbg_print(NAND_DBG_DEBUG,
496
+
dev_dbg(&denali->dev->dev,
470
497
"denali->total_used_banks: %d\n", denali->total_used_banks);
471
498
}
472
499
···
501
526
uint32_t id_bytes[5], addr;
502
527
uint8_t i, maf_id, device_id;
503
528
504
-
nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
505
-
__FILE__, __LINE__, __func__);
529
+
dev_dbg(&denali->dev->dev,
530
+
"%s, Line %d, Function: %s\n",
531
+
__FILE__, __LINE__, __func__);
506
532
507
533
/* Use read id method to get device ID and other
508
534
* params. For some NAND chips, controller can't
···
530
554
get_hynix_nand_para(denali, device_id);
531
555
}
532
556
533
-
nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
534
-
"acc_clks: %d, re_2_we: %d, we_2_re: %d,"
535
-
"addr_2_data: %d, rdwr_en_lo_cnt: %d, "
557
+
dev_info(&denali->dev->dev,
558
+
"Dump timing register values:"
559
+
"acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
560
+
"we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
536
561
"rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
537
562
ioread32(denali->flash_reg + ACC_CLKS),
538
563
ioread32(denali->flash_reg + RE_2_WE),
564
+
ioread32(denali->flash_reg + RE_2_RE),
539
565
ioread32(denali->flash_reg + WE_2_RE),
540
566
ioread32(denali->flash_reg + ADDR_2_DATA),
541
567
ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
···
560
582
static void denali_set_intr_modes(struct denali_nand_info *denali,
561
583
uint16_t INT_ENABLE)
562
584
{
563
-
nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
585
+
dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
564
586
__FILE__, __LINE__, __func__);
565
587
566
588
if (INT_ENABLE)
567
-
denali_write32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
589
+
iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
568
590
else
569
-
denali_write32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
591
+
iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
570
592
}
571
593
572
594
/* validation function to verify that the controlling software is making
573
-
a valid request
595
+
* a valid request
574
596
*/
575
597
static inline bool is_flash_bank_valid(int flash_bank)
576
598
{
···
587
609
int_mask = DENALI_IRQ_ALL;
588
610
589
611
/* Clear all status bits */
590
-
denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS0);
591
-
denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS1);
592
-
denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS2);
593
-
denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS3);
612
+
iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS0);
613
+
iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS1);
614
+
iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS2);
615
+
iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS3);
594
616
595
617
denali_irq_enable(denali, int_mask);
596
618
}
···
604
626
static void denali_irq_enable(struct denali_nand_info *denali,
605
627
uint32_t int_mask)
606
628
{
607
-
denali_write32(int_mask, denali->flash_reg + INTR_EN0);
608
-
denali_write32(int_mask, denali->flash_reg + INTR_EN1);
609
-
denali_write32(int_mask, denali->flash_reg + INTR_EN2);
610
-
denali_write32(int_mask, denali->flash_reg + INTR_EN3);
629
+
iowrite32(int_mask, denali->flash_reg + INTR_EN0);
630
+
iowrite32(int_mask, denali->flash_reg + INTR_EN1);
631
+
iowrite32(int_mask, denali->flash_reg + INTR_EN2);
632
+
iowrite32(int_mask, denali->flash_reg + INTR_EN3);
611
633
}
612
634
613
635
/* This function only returns when an interrupt that this driver cares about
···
626
648
627
649
intr_status_reg = intr_status_addresses[denali->flash_bank];
628
650
629
-
denali_write32(irq_mask, denali->flash_reg + intr_status_reg);
651
+
iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
630
652
}
631
653
632
654
static void clear_interrupts(struct denali_nand_info *denali)
···
635
657
spin_lock_irq(&denali->irq_lock);
636
658
637
659
status = read_interrupt_status(denali);
638
-
639
-
#if DEBUG_DENALI
640
-
denali->irq_debug_array[denali->idx++] = 0x30000000 | status;
641
-
denali->idx %= 32;
642
-
#endif
660
+
clear_interrupt(denali, status);
643
661
644
662
denali->irq_status = 0x0;
645
663
spin_unlock_irq(&denali->irq_lock);
···
649
675
650
676
return ioread32(denali->flash_reg + intr_status_reg);
651
677
}
652
-
653
-
#if DEBUG_DENALI
654
-
static void print_irq_log(struct denali_nand_info *denali)
655
-
{
656
-
int i = 0;
657
-
658
-
printk(KERN_INFO "ISR debug log index = %X\n", denali->idx);
659
-
for (i = 0; i < 32; i++)
660
-
printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]);
661
-
}
662
-
#endif
663
678
664
679
/* This is the interrupt service routine. It handles all interrupts
665
680
* sent to this device. Note that on CE4100, this is a shared
···
670
707
* the interrupt, since this is a shared interrupt */
671
708
irq_status = denali_irq_detected(denali);
672
709
if (irq_status != 0) {
673
-
#if DEBUG_DENALI
674
-
denali->irq_debug_array[denali->idx++] =
675
-
0x10000000 | irq_status;
676
-
denali->idx %= 32;
677
-
678
-
printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
679
-
#endif
680
710
/* handle interrupt */
681
711
/* first acknowledge it */
682
712
clear_interrupt(denali, irq_status);
···
695
739
unsigned long timeout = msecs_to_jiffies(1000);
696
740
697
741
do {
698
-
#if DEBUG_DENALI
699
-
printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
700
-
#endif
701
742
comp_res =
702
743
wait_for_completion_timeout(&denali->complete, timeout);
703
744
spin_lock_irq(&denali->irq_lock);
704
745
intr_status = denali->irq_status;
705
746
706
-
#if DEBUG_DENALI
707
-
denali->irq_debug_array[denali->idx++] =
708
-
0x20000000 | (irq_mask << 16) | intr_status;
709
-
denali->idx %= 32;
710
-
#endif
711
-
712
747
if (intr_status & irq_mask) {
713
748
denali->irq_status &= ~irq_mask;
714
749
spin_unlock_irq(&denali->irq_lock);
715
-
#if DEBUG_DENALI
716
-
if (retry)
717
-
printk(KERN_INFO "status on retry = 0x%x\n",
718
-
intr_status);
719
-
#endif
720
750
/* our interrupt was detected */
721
751
break;
722
752
} else {
723
753
/* these are not the interrupts you are looking for -
724
754
* need to wait again */
725
755
spin_unlock_irq(&denali->irq_lock);
726
-
#if DEBUG_DENALI
727
-
print_irq_log(denali);
728
-
printk(KERN_INFO "received irq nobody cared:"
729
-
" irq_status = 0x%x, irq_mask = 0x%x,"
730
-
" timeout = %ld\n", intr_status,
731
-
irq_mask, comp_res);
732
-
#endif
733
756
retry = true;
734
757
}
735
758
} while (comp_res != 0);
···
724
789
}
725
790
726
791
/* This helper function setups the registers for ECC and whether or not
727
-
the spare area will be transfered. */
792
+
* the spare area will be transfered. */
728
793
static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
729
794
bool transfer_spare)
730
795
{
···
735
800
transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
736
801
737
802
/* Enable spare area/ECC per user's request. */
738
-
denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
739
-
denali_write32(transfer_spare_flag,
803
+
iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
804
+
iowrite32(transfer_spare_flag,
740
805
denali->flash_reg + TRANSFER_SPARE_REG);
741
806
}
742
807
743
808
/* sends a pipeline command operation to the controller. See the Denali NAND
744
-
controller's user guide for more information (section 4.2.3.6).
809
+
* controller's user guide for more information (section 4.2.3.6).
745
810
*/
746
811
static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
747
812
bool ecc_en,
···
762
827
763
828
setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
764
829
765
-
#if DEBUG_DENALI
766
-
spin_lock_irq(&denali->irq_lock);
767
-
denali->irq_debug_array[denali->idx++] =
768
-
0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
769
-
(access_type << 4);
770
-
denali->idx %= 32;
771
-
spin_unlock_irq(&denali->irq_lock);
772
-
#endif
773
-
774
-
775
830
/* clear interrupts */
776
831
clear_interrupts(denali);
777
832
···
769
844
770
845
if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
771
846
cmd = MODE_01 | addr;
772
-
denali_write32(cmd, denali->flash_mem);
847
+
iowrite32(cmd, denali->flash_mem);
773
848
} else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
774
849
/* read spare area */
775
850
cmd = MODE_10 | addr;
776
851
index_addr(denali, (uint32_t)cmd, access_type);
777
852
778
853
cmd = MODE_01 | addr;
779
-
denali_write32(cmd, denali->flash_mem);
854
+
iowrite32(cmd, denali->flash_mem);
780
855
} else if (op == DENALI_READ) {
781
856
/* setup page read request for access type */
782
857
cmd = MODE_10 | addr;
···
788
863
*/
789
864
if (access_type == SPARE_ACCESS) {
790
865
cmd = MODE_01 | addr;
791
-
denali_write32(cmd, denali->flash_mem);
866
+
iowrite32(cmd, denali->flash_mem);
792
867
} else {
793
868
index_addr(denali, (uint32_t)cmd,
794
869
0x2000 | op | page_count);
···
800
875
irq_status = wait_for_irq(denali, irq_mask);
801
876
802
877
if (irq_status == 0) {
803
-
printk(KERN_ERR "cmd, page, addr on timeout "
804
-
"(0x%x, 0x%x, 0x%x)\n", cmd,
805
-
denali->page, addr);
878
+
dev_err(&denali->dev->dev,
879
+
"cmd, page, addr on timeout "
880
+
"(0x%x, 0x%x, 0x%x)\n",
881
+
cmd, denali->page, addr);
806
882
status = FAIL;
807
883
} else {
808
884
cmd = MODE_01 | addr;
809
-
denali_write32(cmd, denali->flash_mem);
885
+
iowrite32(cmd, denali->flash_mem);
810
886
}
811
887
}
812
888
}
···
828
902
/* write the data to the flash memory */
829
903
buf32 = (uint32_t *)buf;
830
904
for (i = 0; i < len / 4; i++)
831
-
denali_write32(*buf32++, denali->flash_mem + 0x10);
905
+
iowrite32(*buf32++, denali->flash_mem + 0x10);
832
906
return i*4; /* intent is to return the number of bytes read */
833
907
}
834
908
···
871
945
DENALI_WRITE) == PASS) {
872
946
write_data_to_flash_mem(denali, buf, mtd->oobsize);
873
947
874
-
#if DEBUG_DENALI
875
-
spin_lock_irq(&denali->irq_lock);
876
-
denali->irq_debug_array[denali->idx++] =
877
-
0x80000000 | mtd->oobsize;
878
-
denali->idx %= 32;
879
-
spin_unlock_irq(&denali->irq_lock);
880
-
#endif
881
-
882
-
883
948
/* wait for operation to complete */
884
949
irq_status = wait_for_irq(denali, irq_mask);
885
950
886
951
if (irq_status == 0) {
887
-
printk(KERN_ERR "OOB write failed\n");
952
+
dev_err(&denali->dev->dev, "OOB write failed\n");
888
953
status = -EIO;
889
954
}
890
955
} else {
891
-
printk(KERN_ERR "unable to send pipeline command\n");
956
+
dev_err(&denali->dev->dev, "unable to send pipeline command\n");
892
957
status = -EIO;
893
958
}
894
959
return status;
···
894
977
895
978
denali->page = page;
896
979
897
-
#if DEBUG_DENALI
898
-
printk(KERN_INFO "read_oob %d\n", page);
899
-
#endif
900
980
if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
901
981
DENALI_READ) == PASS) {
902
982
read_data_from_flash_mem(denali, buf, mtd->oobsize);
···
904
990
irq_status = wait_for_irq(denali, irq_mask);
905
991
906
992
if (irq_status == 0)
907
-
printk(KERN_ERR "page on OOB timeout %d\n",
993
+
dev_err(&denali->dev->dev, "page on OOB timeout %d\n",
908
994
denali->page);
909
995
910
996
/* We set the device back to MAIN_ACCESS here as I observed
···
916
1002
addr = BANK(denali->flash_bank) | denali->page;
917
1003
cmd = MODE_10 | addr;
918
1004
index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
919
-
920
-
#if DEBUG_DENALI
921
-
spin_lock_irq(&denali->irq_lock);
922
-
denali->irq_debug_array[denali->idx++] =
923
-
0x60000000 | mtd->oobsize;
924
-
denali->idx %= 32;
925
-
spin_unlock_irq(&denali->irq_lock);
926
-
#endif
927
1005
}
928
1006
}
929
1007
···
935
1029
#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
936
1030
#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
937
1031
#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
938
-
#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO))
939
-
#define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8)
1032
+
#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
1033
+
#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
940
1034
#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
941
1035
942
1036
static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
943
-
uint8_t *oobbuf, uint32_t irq_status)
1037
+
uint32_t irq_status)
944
1038
{
945
1039
bool check_erased_page = false;
946
1040
···
949
1043
uint32_t err_address = 0, err_correction_info = 0;
950
1044
uint32_t err_byte = 0, err_sector = 0, err_device = 0;
951
1045
uint32_t err_correction_value = 0;
1046
+
denali_set_intr_modes(denali, false);
952
1047
953
1048
do {
954
1049
err_address = ioread32(denali->flash_reg +
955
1050
ECC_ERROR_ADDRESS);
956
1051
err_sector = ECC_SECTOR(err_address);
957
1052
err_byte = ECC_BYTE(err_address);
958
-
959
1053
960
1054
err_correction_info = ioread32(denali->flash_reg +
961
1055
ERR_CORRECTION_INFO);
···
964
1058
err_device = ECC_ERR_DEVICE(err_correction_info);
965
1059
966
1060
if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
967
-
/* offset in our buffer is computed as:
968
-
sector number * sector size + offset in
969
-
sector
970
-
*/
971
-
int offset = err_sector * ECC_SECTOR_SIZE +
972
-
err_byte;
973
-
if (offset < denali->mtd.writesize) {
1061
+
/* If err_byte is larger than ECC_SECTOR_SIZE,
1062
+
* means error happend in OOB, so we ignore
1063
+
* it. It's no need for us to correct it
1064
+
* err_device is represented the NAND error
1065
+
* bits are happened in if there are more
1066
+
* than one NAND connected.
1067
+
* */
1068
+
if (err_byte < ECC_SECTOR_SIZE) {
1069
+
int offset;
1070
+
offset = (err_sector *
1071
+
ECC_SECTOR_SIZE +
1072
+
err_byte) *
1073
+
denali->devnum +
1074
+
err_device;
974
1075
/* correct the ECC error */
975
1076
buf[offset] ^= err_correction_value;
976
1077
denali->mtd.ecc_stats.corrected++;
977
-
} else {
978
-
/* bummer, couldn't correct the error */
979
-
printk(KERN_ERR "ECC offset invalid\n");
980
-
denali->mtd.ecc_stats.failed++;
981
1078
}
982
1079
} else {
983
1080
/* if the error is not correctable, need to
···
989
1080
* */
990
1081
check_erased_page = true;
991
1082
}
992
-
993
-
#if DEBUG_DENALI
994
-
printk(KERN_INFO "Detected ECC error in page %d:"
995
-
" err_addr = 0x%08x, info to fix is"
996
-
" 0x%08x\n", denali->page, err_address,
997
-
err_correction_info);
998
-
#endif
999
1083
} while (!ECC_LAST_ERR(err_correction_info));
1084
+
/* Once handle all ecc errors, controller will triger
1085
+
* a ECC_TRANSACTION_DONE interrupt, so here just wait
1086
+
* for a while for this interrupt
1087
+
* */
1088
+
while (!(read_interrupt_status(denali) &
1089
+
INTR_STATUS0__ECC_TRANSACTION_DONE))
1090
+
cpu_relax();
1091
+
clear_interrupts(denali);
1092
+
denali_set_intr_modes(denali, true);
1000
1093
}
1001
1094
return check_erased_page;
1002
1095
}
···
1011
1100
if (en)
1012
1101
reg_val = DMA_ENABLE__FLAG;
1013
1102
1014
-
denali_write32(reg_val, denali->flash_reg + DMA_ENABLE);
1103
+
iowrite32(reg_val, denali->flash_reg + DMA_ENABLE);
1015
1104
ioread32(denali->flash_reg + DMA_ENABLE);
1016
1105
}
1017
1106
···
1040
1129
}
1041
1130
1042
1131
/* writes a page. user specifies type, and this function handles the
1043
-
configuration details. */
1132
+
* configuration details. */
1044
1133
static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1045
1134
const uint8_t *buf, bool raw_xfer)
1046
1135
{
···
1082
1171
irq_status = wait_for_irq(denali, irq_mask);
1083
1172
1084
1173
if (irq_status == 0) {
1085
-
printk(KERN_ERR "timeout on write_page"
1086
-
" (type = %d)\n", raw_xfer);
1174
+
dev_err(&denali->dev->dev,
1175
+
"timeout on write_page (type = %d)\n",
1176
+
raw_xfer);
1087
1177
denali->status =
1088
1178
(irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1089
1179
NAND_STATUS_FAIL : PASS;
···
1097
1185
/* NAND core entry points */
1098
1186
1099
1187
/* this is the callback that the NAND core calls to write a page. Since
1100
-
writing a page with ECC or without is similar, all the work is done
1101
-
by write_page above. */
1188
+
* writing a page with ECC or without is similar, all the work is done
1189
+
* by write_page above.
1190
+
* */
1102
1191
static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1103
1192
const uint8_t *buf)
1104
1193
{
···
1109
1196
}
1110
1197
1111
1198
/* This is the callback that the NAND core calls to write a page without ECC.
1112
-
raw access is similiar to ECC page writes, so all the work is done in the
1113
-
write_page() function above.
1199
+
* raw access is similiar to ECC page writes, so all the work is done in the
1200
+
* write_page() function above.
1114
1201
*/
1115
1202
static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1116
1203
const uint8_t *buf)
···
1149
1236
INTR_STATUS0__ECC_ERR;
1150
1237
bool check_erased_page = false;
1151
1238
1239
+
if (page != denali->page) {
1240
+
dev_err(&denali->dev->dev, "IN %s: page %d is not"
1241
+
" equal to denali->page %d, investigate!!",
1242
+
__func__, page, denali->page);
1243
+
BUG();
1244
+
}
1245
+
1152
1246
setup_ecc_for_xfer(denali, true, false);
1153
1247
1154
1248
denali_enable_dma(denali, true);
···
1171
1251
1172
1252
memcpy(buf, denali->buf.buf, mtd->writesize);
1173
1253
1174
-
check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status);
1254
+
check_erased_page = handle_ecc(denali, buf, irq_status);
1175
1255
denali_enable_dma(denali, false);
1176
1256
1177
1257
if (check_erased_page) {
···
1199
1279
1200
1280
uint32_t irq_status = 0;
1201
1281
uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
1282
+
1283
+
if (page != denali->page) {
1284
+
dev_err(&denali->dev->dev, "IN %s: page %d is not"
1285
+
" equal to denali->page %d, investigate!!",
1286
+
__func__, page, denali->page);
1287
+
BUG();
1288
+
}
1202
1289
1203
1290
setup_ecc_for_xfer(denali, false, true);
1204
1291
denali_enable_dma(denali, true);
···
1236
1309
if (denali->buf.head < denali->buf.tail)
1237
1310
result = denali->buf.buf[denali->buf.head++];
1238
1311
1239
-
#if DEBUG_DENALI
1240
-
printk(KERN_INFO "read byte -> 0x%02x\n", result);
1241
-
#endif
1242
1312
return result;
1243
1313
}
1244
1314
1245
1315
static void denali_select_chip(struct mtd_info *mtd, int chip)
1246
1316
{
1247
1317
struct denali_nand_info *denali = mtd_to_denali(mtd);
1248
-
#if DEBUG_DENALI
1249
-
printk(KERN_INFO "denali select chip %d\n", chip);
1250
-
#endif
1318
+
1251
1319
spin_lock_irq(&denali->irq_lock);
1252
1320
denali->flash_bank = chip;
1253
1321
spin_unlock_irq(&denali->irq_lock);
···
1254
1332
int status = denali->status;
1255
1333
denali->status = 0;
1256
1334
1257
-
#if DEBUG_DENALI
1258
-
printk(KERN_INFO "waitfunc %d\n", status);
1259
-
#endif
1260
1335
return status;
1261
1336
}
1262
1337
···
1263
1344
1264
1345
uint32_t cmd = 0x0, irq_status = 0;
1265
1346
1266
-
#if DEBUG_DENALI
1267
-
printk(KERN_INFO "erase page: %d\n", page);
1268
-
#endif
1269
1347
/* clear interrupts */
1270
1348
clear_interrupts(denali);
1271
1349
···
1285
1369
uint32_t addr, id;
1286
1370
int i;
1287
1371
1288
-
#if DEBUG_DENALI
1289
-
printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page);
1290
-
#endif
1291
1372
switch (cmd) {
1292
1373
case NAND_CMD_PAGEPROG:
1293
1374
break;
···
1328
1415
static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1329
1416
uint8_t *ecc_code)
1330
1417
{
1331
-
printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
1418
+
struct denali_nand_info *denali = mtd_to_denali(mtd);
1419
+
dev_err(&denali->dev->dev,
1420
+
"denali_ecc_calculate called unexpectedly\n");
1332
1421
BUG();
1333
1422
return -EIO;
1334
1423
}
···
1338
1423
static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1339
1424
uint8_t *read_ecc, uint8_t *calc_ecc)
1340
1425
{
1341
-
printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
1426
+
struct denali_nand_info *denali = mtd_to_denali(mtd);
1427
+
dev_err(&denali->dev->dev,
1428
+
"denali_ecc_correct called unexpectedly\n");
1342
1429
BUG();
1343
1430
return -EIO;
1344
1431
}
1345
1432
1346
1433
static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1347
1434
{
1348
-
printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n");
1435
+
struct denali_nand_info *denali = mtd_to_denali(mtd);
1436
+
dev_err(&denali->dev->dev,
1437
+
"denali_ecc_hwctl called unexpectedly\n");
1349
1438
BUG();
1350
1439
}
1351
1440
/* end NAND core entry points */
···
1364
1445
* */
1365
1446
denali->bbtskipbytes = ioread32(denali->flash_reg +
1366
1447
SPARE_AREA_SKIP_BYTES);
1367
-
denali_irq_init(denali);
1368
1448
denali_nand_reset(denali);
1369
-
denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1370
-
denali_write32(CHIP_EN_DONT_CARE__FLAG,
1449
+
iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1450
+
iowrite32(CHIP_EN_DONT_CARE__FLAG,
1371
1451
denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1372
1452
1373
-
denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1374
-
denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1453
+
iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1375
1454
1376
1455
/* Should set value for these registers when init */
1377
-
denali_write32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1378
-
denali_write32(1, denali->flash_reg + ECC_ENABLE);
1456
+
iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1457
+
iowrite32(1, denali->flash_reg + ECC_ENABLE);
1458
+
denali_nand_timing_set(denali);
1459
+
denali_irq_init(denali);
1379
1460
}
1380
1461
1381
1462
/* Althogh controller spec said SLC ECC is forceb to be 4bit,
···
1445
1526
unsigned long csr_len, mem_len;
1446
1527
struct denali_nand_info *denali;
1447
1528
1448
-
nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
1449
-
__FILE__, __LINE__, __func__);
1450
-
1451
1529
denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1452
1530
if (!denali)
1453
1531
return -ENOMEM;
···
1452
1536
ret = pci_enable_device(dev);
1453
1537
if (ret) {
1454
1538
printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
1455
-
goto failed_enable;
1539
+
goto failed_alloc_memery;
1456
1540
}
1457
1541
1458
1542
if (id->driver_data == INTEL_CE4100) {
···
1463
1547
printk(KERN_ERR "Intel CE4100 only supports"
1464
1548
" ONFI timing mode 1 or below\n");
1465
1549
ret = -EINVAL;
1466
-
goto failed_enable;
1550
+
goto failed_enable_dev;
1467
1551
}
1468
1552
denali->platform = INTEL_CE4100;
1469
1553
mem_base = pci_resource_start(dev, 0);
···
1473
1557
} else {
1474
1558
denali->platform = INTEL_MRST;
1475
1559
csr_base = pci_resource_start(dev, 0);
1476
-
csr_len = pci_resource_start(dev, 0);
1560
+
csr_len = pci_resource_len(dev, 0);
1477
1561
mem_base = pci_resource_start(dev, 1);
1478
1562
mem_len = pci_resource_len(dev, 1);
1479
1563
if (!mem_len) {
1480
1564
mem_base = csr_base + csr_len;
1481
1565
mem_len = csr_len;
1482
-
nand_dbg_print(NAND_DBG_WARN,
1483
-
"Spectra: No second"
1484
-
" BAR for PCI device;"
1485
-
" assuming %08Lx\n",
1486
-
(uint64_t)csr_base);
1487
1566
}
1488
1567
}
1489
1568
···
1487
1576
1488
1577
if (ret) {
1489
1578
printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1490
-
goto failed_enable;
1579
+
goto failed_enable_dev;
1491
1580
}
1492
1581
denali->buf.dma_buf =
1493
1582
pci_map_single(dev, denali->buf.buf,
···
1495
1584
PCI_DMA_BIDIRECTIONAL);
1496
1585
1497
1586
if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
1498
-
printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
1499
-
goto failed_enable;
1587
+
dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
1588
+
goto failed_enable_dev;
1500
1589
}
1501
1590
1502
1591
pci_set_master(dev);
1503
1592
denali->dev = dev;
1593
+
denali->mtd.dev.parent = &dev->dev;
1504
1594
1505
1595
ret = pci_request_regions(dev, DENALI_NAND_NAME);
1506
1596
if (ret) {
1507
1597
printk(KERN_ERR "Spectra: Unable to request memory regions\n");
1508
-
goto failed_req_csr;
1598
+
goto failed_dma_map;
1509
1599
}
1510
1600
1511
1601
denali->flash_reg = ioremap_nocache(csr_base, csr_len);
1512
1602
if (!denali->flash_reg) {
1513
1603
printk(KERN_ERR "Spectra: Unable to remap memory region\n");
1514
1604
ret = -ENOMEM;
1515
-
goto failed_remap_csr;
1605
+
goto failed_req_regions;
1516
1606
}
1517
-
nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n",
1518
-
(uint64_t)csr_base, denali->flash_reg, csr_len);
1519
1607
1520
1608
denali->flash_mem = ioremap_nocache(mem_base, mem_len);
1521
1609
if (!denali->flash_mem) {
1522
1610
printk(KERN_ERR "Spectra: ioremap_nocache failed!");
1523
-
iounmap(denali->flash_reg);
1524
1611
ret = -ENOMEM;
1525
-
goto failed_remap_csr;
1612
+
goto failed_remap_reg;
1526
1613
}
1527
-
1528
-
nand_dbg_print(NAND_DBG_WARN,
1529
-
"Spectra: Remapped flash base address: "
1530
-
"0x%p, len: %ld\n",
1531
-
denali->flash_mem, csr_len);
1532
1614
1533
1615
denali_hw_init(denali);
1534
1616
denali_drv_init(denali);
1535
1617
1536
-
nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq);
1618
+
/* denali_isr register is done after all the hardware
1619
+
* initilization is finished*/
1537
1620
if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
1538
1621
DENALI_NAND_NAME, denali)) {
1539
1622
printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
1540
1623
ret = -ENODEV;
1541
-
goto failed_request_irq;
1624
+
goto failed_remap_mem;
1542
1625
}
1543
1626
1544
1627
/* now that our ISR is registered, we can enable interrupts */
···
1540
1635
1541
1636
pci_set_drvdata(dev, denali);
1542
1637
1543
-
denali_nand_timing_set(denali);
1544
-
1545
-
nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
1546
-
"acc_clks: %d, re_2_we: %d, we_2_re: %d,"
1547
-
"addr_2_data: %d, rdwr_en_lo_cnt: %d, "
1548
-
"rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
1549
-
ioread32(denali->flash_reg + ACC_CLKS),
1550
-
ioread32(denali->flash_reg + RE_2_WE),
1551
-
ioread32(denali->flash_reg + WE_2_RE),
1552
-
ioread32(denali->flash_reg + ADDR_2_DATA),
1553
-
ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
1554
-
ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
1555
-
ioread32(denali->flash_reg + CS_SETUP_CNT));
1556
-
1557
-
denali->mtd.name = "Denali NAND";
1638
+
denali->mtd.name = "denali-nand";
1558
1639
denali->mtd.owner = THIS_MODULE;
1559
1640
denali->mtd.priv = &denali->nand;
1560
1641
···
1555
1664
* with the nand subsystem */
1556
1665
if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
1557
1666
ret = -ENXIO;
1558
-
goto failed_nand;
1667
+
goto failed_req_irq;
1559
1668
}
1560
1669
1561
1670
/* MTD supported page sizes vary by kernel. We validate our
···
1565
1674
ret = -ENODEV;
1566
1675
printk(KERN_ERR "Spectra: device size not supported by this "
1567
1676
"version of MTD.");
1568
-
goto failed_nand;
1677
+
goto failed_req_irq;
1569
1678
}
1570
1679
1571
1680
/* support for multi nand
···
1610
1719
/* if MLC OOB size is large enough, use 15bit ECC*/
1611
1720
denali->nand.ecc.layout = &nand_15bit_oob;
1612
1721
denali->nand.ecc.bytes = ECC_15BITS;
1613
-
denali_write32(15, denali->flash_reg + ECC_CORRECTION);
1722
+
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1614
1723
} else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1615
1724
ECC_8BITS * (denali->mtd.writesize /
1616
1725
ECC_SECTOR_SIZE))) {
1617
1726
printk(KERN_ERR "Your NAND chip OOB is not large enough to"
1618
1727
" contain 8bit ECC correction codes");
1619
-
goto failed_nand;
1728
+
goto failed_req_irq;
1620
1729
} else {
1621
1730
denali->nand.ecc.layout = &nand_8bit_oob;
1622
1731
denali->nand.ecc.bytes = ECC_8BITS;
1623
-
denali_write32(8, denali->flash_reg + ECC_CORRECTION);
1732
+
iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1624
1733
}
1625
1734
1626
1735
denali->nand.ecc.bytes *= denali->devnum;
···
1660
1769
1661
1770
if (nand_scan_tail(&denali->mtd)) {
1662
1771
ret = -ENXIO;
1663
-
goto failed_nand;
1772
+
goto failed_req_irq;
1664
1773
}
1665
1774
1666
1775
ret = add_mtd_device(&denali->mtd);
1667
1776
if (ret) {
1668
-
printk(KERN_ERR "Spectra: Failed to register"
1669
-
" MTD device: %d\n", ret);
1670
-
goto failed_nand;
1777
+
dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
1778
+
ret);
1779
+
goto failed_req_irq;
1671
1780
}
1672
1781
return 0;
1673
1782
1674
-
failed_nand:
1783
+
failed_req_irq:
1675
1784
denali_irq_cleanup(dev->irq, denali);
1676
-
failed_request_irq:
1677
-
iounmap(denali->flash_reg);
1785
+
failed_remap_mem:
1678
1786
iounmap(denali->flash_mem);
1679
-
failed_remap_csr:
1787
+
failed_remap_reg:
1788
+
iounmap(denali->flash_reg);
1789
+
failed_req_regions:
1680
1790
pci_release_regions(dev);
1681
-
failed_req_csr:
1791
+
failed_dma_map:
1682
1792
pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1683
1793
PCI_DMA_BIDIRECTIONAL);
1684
-
failed_enable:
1794
+
failed_enable_dev:
1795
+
pci_disable_device(dev);
1796
+
failed_alloc_memery:
1685
1797
kfree(denali);
1686
1798
return ret;
1687
1799
}
···
1693
1799
static void denali_pci_remove(struct pci_dev *dev)
1694
1800
{
1695
1801
struct denali_nand_info *denali = pci_get_drvdata(dev);
1696
-
1697
-
nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n",
1698
-
__FILE__, __LINE__, __func__);
1699
1802
1700
1803
nand_release(&denali->mtd);
1701
1804
del_mtd_device(&denali->mtd);
-18
drivers/mtd/nand/denali.h
-18
drivers/mtd/nand/denali.h
···
635
635
#define CLK_X 5
636
636
#define CLK_MULTI 4
637
637
638
-
/* ffsport.h */
639
-
#define VERBOSE 1
640
-
641
-
#define NAND_DBG_WARN 1
642
-
#define NAND_DBG_DEBUG 2
643
-
#define NAND_DBG_TRACE 3
644
-
645
-
#ifdef VERBOSE
646
-
#define nand_dbg_print(level, args...) \
647
-
do { \
648
-
if (level <= nand_debug_level) \
649
-
printk(KERN_ALERT args); \
650
-
} while (0)
651
-
#else
652
-
#define nand_dbg_print(level, args...)
653
-
#endif
654
-
655
-
656
638
/* spectraswconfig.h */
657
639
#define CMD_DMA 0
658
640
+1
-1
drivers/mtd/nand/nand_ids.c
+1
-1
drivers/mtd/nand/nand_ids.c
···
112
112
{"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
113
113
114
114
/* 32 Gigabit */
115
-
{"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 4096, 0, LP_OPTIONS16},
115
+
{"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 4096, 0, LP_OPTIONS},
116
116
117
117
/*
118
118
* Renesas AND 1 Gigabit. Those chips do not support extended id and
+5
drivers/mtd/nand/plat_nand.c
+5
drivers/mtd/nand/plat_nand.c