Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Update HFI definitions
Update the HFI definitions to support additional GMU based power
features.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714671/
Message-ID: <20260327-a8xx-gpu-batch2-v2-10-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Akhil P Oommen
and committed by
Rob Clark
742b4e88
29c1d7e5
+111
-5
-3
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
-3
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
···
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return a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NULL, 0);
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}
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-
#define HFI_FEATURE_IFPC 9
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#define IFPC_LONG_HYST 0x1680
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static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu)
···
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return a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFPC, 1, IFPC_LONG_HYST);
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}
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-
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-
#define HFI_FEATURE_ACD 12
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static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu)
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{
+111
-2
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
+111
-2
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
···
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u32 data[16 * MAX_ACD_STRIDE];
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} __packed;
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+
#define CLX_DATA(irated, num_phases, clx_path, extd_intf) \
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((extd_intf << 29) | \
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(clx_path << 28) | \
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(num_phases << 22) | \
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(irated << 16))
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+
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struct a6xx_hfi_clx_domain_v2 {
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/**
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* @data: BITS[0:15] Migration time
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* BITS[16:21] Current rating
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* BITS[22:27] Phases for domain
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* BITS[28:28] Path notification
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* BITS[29:31] Extra features
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*/
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u32 data;
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/** @clxt: CLX time in microseconds */
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u32 clxt;
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/** @clxh: CLH time in microseconds */
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u32 clxh;
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/** @urg_mode: Urgent HW throttle mode of operation */
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u32 urg_mode;
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/** @lkg_en: Enable leakage current estimate */
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u32 lkg_en;
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/** curr_budget: Current Budget */
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u32 curr_budget;
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} __packed;
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+
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#define HFI_H2F_MSG_CLX_TBL 8
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+
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#define MAX_CLX_DOMAINS 2
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struct a6xx_hfi_clx_table_v2_cmd {
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u32 hdr;
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u32 version;
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struct a6xx_hfi_clx_domain_v2 domain[MAX_CLX_DOMAINS];
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} __packed;
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+
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#define HFI_H2F_MSG_START 10
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struct a6xx_hfi_msg_start {
···
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struct a6xx_hfi_msg_feature_ctrl {
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u32 header;
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u32 feature;
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#define HFI_FEATURE_DCVS 0
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#define HFI_FEATURE_HWSCHED 1
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#define HFI_FEATURE_PREEMPTION 2
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#define HFI_FEATURE_CLOCKS_ON 3
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#define HFI_FEATURE_BUS_ON 4
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#define HFI_FEATURE_RAIL_ON 5
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#define HFI_FEATURE_HWCG 6
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#define HFI_FEATURE_LM 7
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#define HFI_FEATURE_THROTTLE 8
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#define HFI_FEATURE_IFPC 9
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#define HFI_FEATURE_NAP 10
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#define HFI_FEATURE_BCL 11
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#define HFI_FEATURE_ACD 12
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#define HFI_FEATURE_DIDT 13
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#define HFI_FEATURE_DEPRECATED 14
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#define HFI_FEATURE_CB 15
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#define HFI_FEATURE_KPROF 16
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#define HFI_FEATURE_BAIL_OUT_TIMER 17
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#define HFI_FEATURE_GMU_STATS 18
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#define HFI_FEATURE_DBQ 19
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#define HFI_FEATURE_MINBW 20
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#define HFI_FEATURE_CLX 21
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#define HFI_FEATURE_LSR 23
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#define HFI_FEATURE_LPAC 24
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#define HFI_FEATURE_HW_FENCE 25
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#define HFI_FEATURE_PERF_NORETAIN 26
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#define HFI_FEATURE_DMS 27
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#define HFI_FEATURE_THERMAL 28
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#define HFI_FEATURE_AQE 29
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#define HFI_FEATURE_TDCVS 30
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#define HFI_FEATURE_DCE 31
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#define HFI_FEATURE_IFF_PCLX 32
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#define HFI_FEATURE_SOFT_RESET 0x10000001
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#define HFI_FEATURE_DCVS_PROFILE 0x10000002
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#define HFI_FEATURE_FAST_CTX_DESTROY 0x10000003
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u32 enable;
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u32 data;
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} __packed;
···
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u32 header;
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u32 version;
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u32 type;
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-
#define HFI_TABLE_BW_VOTE 0
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-
#define HFI_TABLE_GPU_PERF 1
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#define HFI_TABLE_BW_VOTE 0
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#define HFI_TABLE_GPU_PERF 1
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#define HFI_TABLE_DIDT 2
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#define HFI_TABLE_ACD 3
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#define HFI_TABLE_CLX_V1 4 /* Unused */
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#define HFI_TABLE_CLX_V2 5
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#define HFI_TABLE_THERM 6
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#define HFI_TABLE_DCVS 7
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#define HFI_TABLE_SYS_TIME 8
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#define HFI_TABLE_GMU_DCVS 9
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#define HFI_TABLE_LIMITS_MIT 10
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struct a6xx_hfi_table_entry entry[];
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} __packed;
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···
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u32 header;
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u32 bw;
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u32 freq;
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} __packed;
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struct a6xx_hfi_limits_cfg {
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u32 enable;
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u32 msg_path;
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u32 lkg_en;
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/*
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* BIT[0]: 0 = (static) throttle to fixed sid level
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* 1 = (dynamic) throttle to sid level calculated by HW
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* BIT[1]: 0 = Mx
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* 1 = Bx
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*/
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u32 mode;
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u32 sid;
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/* Mitigation time in microseconds */
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u32 mit_time;
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/* Max current in mA during mitigation */
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u32 curr_limit;
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} __packed;
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struct a6xx_hfi_limits_tbl {
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u8 feature_id;
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#define GMU_MIT_IFF 0
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#define GMU_MIT_PCLX 1
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u8 domain;
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#define GMU_GX_DOMAIN 0
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#define GMU_MX_DOMAIN 1
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u16 feature_rev;
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struct a6xx_hfi_limits_cfg cfg;
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} __packed;
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#endif