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clk: qcom: gcc-msm8994: Add missing NoC clocks

Add necessary NoC clocks to provide frequency sources for
relevant branch clocks.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-4-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Konrad Dybcio and committed by
Stephen Boyd 74a33fac 80863521

+92 -12
+89 -12
drivers/clk/qcom/gcc-msm8994.c
··· 106 106 { .hw = &gpll4.clkr.hw }, 107 107 }; 108 108 109 + static struct clk_rcg2 system_noc_clk_src = { 110 + .cmd_rcgr = 0x0120, 111 + .hid_width = 5, 112 + .parent_map = gcc_xo_gpll0_map, 113 + .clkr.hw.init = &(struct clk_init_data){ 114 + .name = "system_noc_clk_src", 115 + .parent_data = gcc_xo_gpll0, 116 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 117 + .ops = &clk_rcg2_ops, 118 + }, 119 + }; 120 + 121 + static struct clk_rcg2 config_noc_clk_src = { 122 + .cmd_rcgr = 0x0150, 123 + .hid_width = 5, 124 + .parent_map = gcc_xo_gpll0_map, 125 + .clkr.hw.init = &(struct clk_init_data){ 126 + .name = "config_noc_clk_src", 127 + .parent_data = gcc_xo_gpll0, 128 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 129 + .ops = &clk_rcg2_ops, 130 + }, 131 + }; 132 + 133 + static struct clk_rcg2 periph_noc_clk_src = { 134 + .cmd_rcgr = 0x0190, 135 + .hid_width = 5, 136 + .parent_map = gcc_xo_gpll0_map, 137 + .clkr.hw.init = &(struct clk_init_data){ 138 + .name = "periph_noc_clk_src", 139 + .parent_data = gcc_xo_gpll0, 140 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 141 + .ops = &clk_rcg2_ops, 142 + }, 143 + }; 144 + 109 145 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 110 146 F(50000000, P_GPLL0, 12, 0, 0), 111 147 F(100000000, P_GPLL0, 6, 0, 0), ··· 1125 1089 .enable_mask = BIT(17), 1126 1090 .hw.init = &(struct clk_init_data){ 1127 1091 .name = "gcc_blsp1_ahb_clk", 1092 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1093 + .num_parents = 1, 1128 1094 .ops = &clk_branch2_ops, 1129 1095 }, 1130 1096 }, ··· 1410 1372 .enable_mask = BIT(15), 1411 1373 .hw.init = &(struct clk_init_data){ 1412 1374 .name = "gcc_blsp2_ahb_clk", 1375 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1376 + .num_parents = 1, 1413 1377 .ops = &clk_branch2_ops, 1414 1378 }, 1415 1379 }, ··· 1739 1699 .enable_mask = BIT(0), 1740 1700 .hw.init = &(struct clk_init_data){ 1741 1701 .name = "gcc_lpass_q6_axi_clk", 1702 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1703 + .num_parents = 1, 1742 1704 .ops = &clk_branch2_ops, 1743 1705 }, 1744 1706 }, ··· 1753 1711 .enable_mask = BIT(0), 1754 1712 .hw.init = &(struct clk_init_data){ 1755 1713 .name = "gcc_mss_q6_bimc_axi_clk", 1714 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1715 + .num_parents = 1, 1756 1716 .ops = &clk_branch2_ops, 1757 1717 }, 1758 1718 }, ··· 1782 1738 .enable_mask = BIT(0), 1783 1739 .hw.init = &(struct clk_init_data){ 1784 1740 .name = "gcc_pcie_0_cfg_ahb_clk", 1741 + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1742 + .num_parents = 1, 1743 + .flags = CLK_SET_RATE_PARENT, 1785 1744 .ops = &clk_branch2_ops, 1786 1745 }, 1787 1746 }, ··· 1797 1750 .enable_mask = BIT(0), 1798 1751 .hw.init = &(struct clk_init_data){ 1799 1752 .name = "gcc_pcie_0_mstr_axi_clk", 1753 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1754 + .num_parents = 1, 1755 + .flags = CLK_SET_RATE_PARENT, 1800 1756 .ops = &clk_branch2_ops, 1801 1757 }, 1802 1758 }, ··· 1829 1779 .enable_mask = BIT(0), 1830 1780 .hw.init = &(struct clk_init_data){ 1831 1781 .name = "gcc_pcie_0_slv_axi_clk", 1782 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1783 + .num_parents = 1, 1784 + .flags = CLK_SET_RATE_PARENT, 1832 1785 .ops = &clk_branch2_ops, 1833 1786 }, 1834 1787 }, ··· 1859 1806 .enable_mask = BIT(0), 1860 1807 .hw.init = &(struct clk_init_data){ 1861 1808 .name = "gcc_pcie_1_cfg_ahb_clk", 1809 + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1810 + .num_parents = 1, 1811 + .flags = CLK_SET_RATE_PARENT, 1862 1812 .ops = &clk_branch2_ops, 1863 1813 }, 1864 1814 }, ··· 1874 1818 .enable_mask = BIT(0), 1875 1819 .hw.init = &(struct clk_init_data){ 1876 1820 .name = "gcc_pcie_1_mstr_axi_clk", 1821 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1822 + .num_parents = 1, 1823 + .flags = CLK_SET_RATE_PARENT, 1877 1824 .ops = &clk_branch2_ops, 1878 1825 }, 1879 1826 }, ··· 1905 1846 .enable_mask = BIT(0), 1906 1847 .hw.init = &(struct clk_init_data){ 1907 1848 .name = "gcc_pcie_1_slv_axi_clk", 1849 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1850 + .num_parents = 1, 1851 + .flags = CLK_SET_RATE_PARENT, 1908 1852 .ops = &clk_branch2_ops, 1909 1853 }, 1910 1854 }, ··· 1935 1873 .enable_mask = BIT(0), 1936 1874 .hw.init = &(struct clk_init_data){ 1937 1875 .name = "gcc_pdm_ahb_clk", 1876 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1877 + .num_parents = 1, 1938 1878 .ops = &clk_branch2_ops, 1939 1879 }, 1940 1880 }, ··· 1964 1900 .enable_mask = BIT(0), 1965 1901 .hw.init = &(struct clk_init_data){ 1966 1902 .name = "gcc_sdcc1_ahb_clk", 1967 - .parent_names = (const char *[]){ 1968 - "periph_noc_clk_src", 1969 - }, 1903 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1970 1904 .num_parents = 1, 1905 + .flags = CLK_SET_RATE_PARENT, 1971 1906 .ops = &clk_branch2_ops, 1972 1907 }, 1973 1908 }, ··· 1979 1916 .enable_mask = BIT(0), 1980 1917 .hw.init = &(struct clk_init_data){ 1981 1918 .name = "gcc_sdcc2_ahb_clk", 1982 - .parent_names = (const char *[]){ 1983 - "periph_noc_clk_src", 1984 - }, 1919 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1985 1920 .num_parents = 1, 1921 + .flags = CLK_SET_RATE_PARENT, 1986 1922 .ops = &clk_branch2_ops, 1987 1923 }, 1988 1924 }, ··· 2009 1947 .enable_mask = BIT(0), 2010 1948 .hw.init = &(struct clk_init_data){ 2011 1949 .name = "gcc_sdcc3_ahb_clk", 2012 - .parent_names = (const char *[]){ 2013 - "periph_noc_clk_src", 2014 - }, 1950 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2015 1951 .num_parents = 1, 1952 + .flags = CLK_SET_RATE_PARENT, 2016 1953 .ops = &clk_branch2_ops, 2017 1954 }, 2018 1955 }, ··· 2039 1978 .enable_mask = BIT(0), 2040 1979 .hw.init = &(struct clk_init_data){ 2041 1980 .name = "gcc_sdcc4_ahb_clk", 2042 - .parent_names = (const char *[]){ 2043 - "periph_noc_clk_src", 2044 - }, 1981 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2045 1982 .num_parents = 1, 1983 + .flags = CLK_SET_RATE_PARENT, 2046 1984 .ops = &clk_branch2_ops, 2047 1985 }, 2048 1986 }, ··· 2099 2039 .enable_mask = BIT(0), 2100 2040 .hw.init = &(struct clk_init_data){ 2101 2041 .name = "gcc_tsif_ahb_clk", 2042 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2043 + .num_parents = 1, 2102 2044 .ops = &clk_branch2_ops, 2103 2045 }, 2104 2046 }, ··· 2128 2066 .enable_mask = BIT(0), 2129 2067 .hw.init = &(struct clk_init_data){ 2130 2068 .name = "gcc_ufs_ahb_clk", 2069 + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2070 + .num_parents = 1, 2131 2071 .ops = &clk_branch2_ops, 2132 2072 }, 2133 2073 }, ··· 2173 2109 .enable_mask = BIT(0), 2174 2110 .hw.init = &(struct clk_init_data){ 2175 2111 .name = "gcc_ufs_rx_symbol_0_clk", 2112 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2113 + .num_parents = 1, 2176 2114 .ops = &clk_branch2_ops, 2177 2115 }, 2178 2116 }, ··· 2188 2122 .enable_mask = BIT(0), 2189 2123 .hw.init = &(struct clk_init_data){ 2190 2124 .name = "gcc_ufs_rx_symbol_1_clk", 2125 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2126 + .num_parents = 1, 2191 2127 .ops = &clk_branch2_ops, 2192 2128 }, 2193 2129 }, ··· 2218 2150 .enable_mask = BIT(0), 2219 2151 .hw.init = &(struct clk_init_data){ 2220 2152 .name = "gcc_ufs_tx_symbol_0_clk", 2153 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2154 + .num_parents = 1, 2221 2155 .ops = &clk_branch2_ops, 2222 2156 }, 2223 2157 }, ··· 2233 2163 .enable_mask = BIT(0), 2234 2164 .hw.init = &(struct clk_init_data){ 2235 2165 .name = "gcc_ufs_tx_symbol_1_clk", 2166 + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2167 + .num_parents = 1, 2236 2168 .ops = &clk_branch2_ops, 2237 2169 }, 2238 2170 }, ··· 2326 2254 .enable_mask = BIT(0), 2327 2255 .hw.init = &(struct clk_init_data){ 2328 2256 .name = "gcc_usb_hs_ahb_clk", 2257 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2258 + .num_parents = 1, 2329 2259 .ops = &clk_branch2_ops, 2330 2260 }, 2331 2261 }, ··· 2405 2331 [GPLL0] = &gpll0.clkr, 2406 2332 [GPLL4_EARLY] = &gpll4_early.clkr, 2407 2333 [GPLL4] = &gpll4.clkr, 2334 + [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2335 + [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2336 + [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2408 2337 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2409 2338 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2410 2339 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+3
include/dt-bindings/clock/qcom,gcc-msm8994.h
··· 148 148 #define GCC_USB30_SLEEP_CLK 138 149 149 #define GCC_USB_HS_AHB_CLK 139 150 150 #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 151 + #define CONFIG_NOC_CLK_SRC 141 152 + #define PERIPH_NOC_CLK_SRC 142 153 + #define SYSTEM_NOC_CLK_SRC 143 151 154 152 155 /* GDSCs */ 153 156 #define PCIE_GDSC 0