Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: gcc-msm8994: Fix up SPI QUP clocks
Fix up SPI QUP freq tables to account for the fact
that not every QUP can run at the same set of frequencies.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-3-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Konrad Dybcio
and committed by
Stephen Boyd
80863521
0519d1d0
+105
-13
+105
-13
drivers/clk/qcom/gcc-msm8994.c
+105
-13
drivers/clk/qcom/gcc-msm8994.c
···
169
169
},
170
170
};
171
171
172
-
static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
172
+
static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
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F(960000, P_XO, 10, 1, 2),
174
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F(4800000, P_XO, 4, 0, 0),
175
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F(9600000, P_XO, 2, 0, 0),
···
187
187
.mnd_width = 8,
188
188
.hid_width = 5,
189
189
.parent_map = gcc_xo_gpll0_map,
190
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
190
+
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
191
191
.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup1_spi_apps_clk_src",
193
193
.parent_data = gcc_xo_gpll0,
···
209
209
},
210
210
};
211
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212
+
static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
213
+
F(960000, P_XO, 10, 1, 2),
214
+
F(4800000, P_XO, 4, 0, 0),
215
+
F(9600000, P_XO, 2, 0, 0),
216
+
F(15000000, P_GPLL0, 10, 1, 4),
217
+
F(19200000, P_XO, 1, 0, 0),
218
+
F(24000000, P_GPLL0, 12.5, 1, 2),
219
+
F(25000000, P_GPLL0, 12, 1, 2),
220
+
F(42860000, P_GPLL0, 14, 0, 0),
221
+
F(46150000, P_GPLL0, 13, 0, 0),
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+
{ }
223
+
};
224
+
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static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
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.cmd_rcgr = 0x06cc,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
217
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
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+
.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
219
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.name = "blsp1_qup2_spi_apps_clk_src",
220
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.parent_data = gcc_xo_gpll0,
···
249
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},
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};
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+
static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
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+
F(960000, P_XO, 10, 1, 2),
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+
F(4800000, P_XO, 4, 0, 0),
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+
F(9600000, P_XO, 2, 0, 0),
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+
F(15000000, P_GPLL0, 10, 1, 4),
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+
F(19200000, P_XO, 1, 0, 0),
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+
F(24000000, P_GPLL0, 12.5, 1, 2),
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+
F(25000000, P_GPLL0, 12, 1, 2),
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+
F(42860000, P_GPLL0, 14, 0, 0),
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+
F(44440000, P_GPLL0, 13.5, 0, 0),
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+
{ }
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+
};
251
+
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static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
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.cmd_rcgr = 0x074c,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
257
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
257
+
.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup3_spi_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
···
294
268
.mnd_width = 8,
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.hid_width = 5,
296
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.parent_map = gcc_xo_gpll0_map,
297
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
271
+
.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
298
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.clkr.hw.init = &(struct clk_init_data){
299
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.name = "blsp1_qup4_spi_apps_clk_src",
300
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.parent_data = gcc_xo_gpll0,
···
316
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},
317
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};
318
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+
static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
294
+
F(960000, P_XO, 10, 1, 2),
295
+
F(4800000, P_XO, 4, 0, 0),
296
+
F(9600000, P_XO, 2, 0, 0),
297
+
F(15000000, P_GPLL0, 10, 1, 4),
298
+
F(19200000, P_XO, 1, 0, 0),
299
+
F(24000000, P_GPLL0, 12.5, 1, 2),
300
+
F(25000000, P_GPLL0, 12, 1, 2),
301
+
F(40000000, P_GPLL0, 15, 0, 0),
302
+
F(42860000, P_GPLL0, 14, 0, 0),
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+
{ }
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+
};
305
+
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static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
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.cmd_rcgr = 0x084c,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
324
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
311
+
.freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup5_spi_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
···
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317
},
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};
358
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+
static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
321
+
F(960000, P_XO, 10, 1, 2),
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+
F(4800000, P_XO, 4, 0, 0),
323
+
F(9600000, P_XO, 2, 0, 0),
324
+
F(15000000, P_GPLL0, 10, 1, 4),
325
+
F(19200000, P_XO, 1, 0, 0),
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+
F(24000000, P_GPLL0, 12.5, 1, 2),
327
+
F(27906976, P_GPLL0, 1, 2, 43),
328
+
F(41380000, P_GPLL0, 15, 0, 0),
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+
F(42860000, P_GPLL0, 14, 0, 0),
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{ }
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+
};
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+
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static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
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.cmd_rcgr = 0x08cc,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
364
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
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+
.freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup6_spi_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
···
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447
},
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};
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+
static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
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F(960000, P_XO, 10, 1, 2),
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+
F(4800000, P_XO, 4, 0, 0),
453
+
F(9600000, P_XO, 2, 0, 0),
454
+
F(15000000, P_GPLL0, 10, 1, 4),
455
+
F(19200000, P_XO, 1, 0, 0),
456
+
F(24000000, P_GPLL0, 12.5, 1, 2),
457
+
F(25000000, P_GPLL0, 12, 1, 2),
458
+
F(42860000, P_GPLL0, 14, 0, 0),
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F(44440000, P_GPLL0, 13.5, 0, 0),
460
+
{ }
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+
};
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+
502
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static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
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.cmd_rcgr = 0x098c,
504
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.mnd_width = 8,
505
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.hid_width = 5,
506
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.parent_map = gcc_xo_gpll0_map,
507
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
468
+
.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
508
469
.clkr.hw.init = &(struct clk_init_data){
509
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.name = "blsp2_qup1_spi_apps_clk_src",
510
471
.parent_data = gcc_xo_gpll0,
···
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
547
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
482
+
.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
549
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.name = "blsp2_qup2_spi_apps_clk_src",
550
485
.parent_data = gcc_xo_gpll0,
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486
.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
489
+
};
490
+
491
+
static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
492
+
F(960000, P_XO, 10, 1, 2),
493
+
F(4800000, P_XO, 4, 0, 0),
494
+
F(9600000, P_XO, 2, 0, 0),
495
+
F(15000000, P_GPLL0, 10, 1, 4),
496
+
F(19200000, P_XO, 1, 0, 0),
497
+
F(24000000, P_GPLL0, 12.5, 1, 2),
498
+
F(25000000, P_GPLL0, 12, 1, 2),
499
+
F(42860000, P_GPLL0, 14, 0, 0),
500
+
F(48000000, P_GPLL0, 12.5, 0, 0),
501
+
{ }
554
502
};
555
503
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504
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
···
584
506
.mnd_width = 8,
585
507
.hid_width = 5,
586
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.parent_map = gcc_xo_gpll0_map,
587
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
509
+
.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
588
510
.clkr.hw.init = &(struct clk_init_data){
589
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.name = "blsp2_qup3_spi_apps_clk_src",
590
512
.parent_data = gcc_xo_gpll0,
···
611
533
.mnd_width = 8,
612
534
.hid_width = 5,
613
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.parent_map = gcc_xo_gpll0_map,
614
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
536
+
.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
615
537
.clkr.hw.init = &(struct clk_init_data){
616
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.name = "blsp2_qup4_spi_apps_clk_src",
617
539
.parent_data = gcc_xo_gpll0,
···
638
560
.mnd_width = 8,
639
561
.hid_width = 5,
640
562
.parent_map = gcc_xo_gpll0_map,
641
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
563
+
/* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
564
+
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
642
565
.clkr.hw.init = &(struct clk_init_data){
643
566
.name = "blsp2_qup5_spi_apps_clk_src",
644
567
.parent_data = gcc_xo_gpll0,
···
661
582
},
662
583
};
663
584
585
+
static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
586
+
F(960000, P_XO, 10, 1, 2),
587
+
F(4800000, P_XO, 4, 0, 0),
588
+
F(9600000, P_XO, 2, 0, 0),
589
+
F(15000000, P_GPLL0, 10, 1, 4),
590
+
F(19200000, P_XO, 1, 0, 0),
591
+
F(24000000, P_GPLL0, 12.5, 1, 2),
592
+
F(25000000, P_GPLL0, 12, 1, 2),
593
+
F(44440000, P_GPLL0, 13.5, 0, 0),
594
+
F(48000000, P_GPLL0, 12.5, 0, 0),
595
+
{ }
596
+
};
597
+
664
598
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
665
599
.cmd_rcgr = 0x0c0c,
666
600
.mnd_width = 8,
667
601
.hid_width = 5,
668
602
.parent_map = gcc_xo_gpll0_map,
669
-
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
603
+
.freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
670
604
.clkr.hw.init = &(struct clk_init_data){
671
605
.name = "blsp2_qup6_spi_apps_clk_src",
672
606
.parent_data = gcc_xo_gpll0,