Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: get rid of DPU_CTL_VM_CFG
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655385/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-12-3b2085a07884@oss.qualcomm.com
authored by
Dmitry Baryshkov
and committed by
Dmitry Baryshkov
74e1b428
20d36dae
+1
-58
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
···
31
31
{
32
32
.name = "ctl_0", .id = CTL_0,
33
33
.base = 0x15000, .len = 0x1000,
34
-
.features = CTL_SC7280_MASK,
35
34
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36
35
}, {
37
36
.name = "ctl_1", .id = CTL_1,
38
37
.base = 0x16000, .len = 0x1000,
39
-
.features = CTL_SC7280_MASK,
40
38
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41
39
}, {
42
40
.name = "ctl_2", .id = CTL_2,
43
41
.base = 0x17000, .len = 0x1000,
44
-
.features = CTL_SC7280_MASK,
45
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
46
43
}, {
47
44
.name = "ctl_3", .id = CTL_3,
48
45
.base = 0x18000, .len = 0x1000,
49
-
.features = CTL_SC7280_MASK,
50
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
51
47
}, {
52
48
.name = "ctl_4", .id = CTL_4,
53
49
.base = 0x19000, .len = 0x1000,
54
-
.features = CTL_SC7280_MASK,
55
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
56
51
}, {
57
52
.name = "ctl_5", .id = CTL_5,
58
53
.base = 0x1a000, .len = 0x1000,
59
-
.features = CTL_SC7280_MASK,
60
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
61
55
},
62
56
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
···
39
39
{
40
40
.name = "ctl_0", .id = CTL_0,
41
41
.base = 0x15000, .len = 0x1e8,
42
-
.features = CTL_SC7280_MASK,
43
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44
43
}, {
45
44
.name = "ctl_1", .id = CTL_1,
46
45
.base = 0x16000, .len = 0x1e8,
47
-
.features = CTL_SC7280_MASK,
48
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49
47
}, {
50
48
.name = "ctl_2", .id = CTL_2,
51
49
.base = 0x17000, .len = 0x1e8,
52
-
.features = CTL_SC7280_MASK,
53
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54
51
}, {
55
52
.name = "ctl_3", .id = CTL_3,
56
53
.base = 0x18000, .len = 0x1e8,
57
-
.features = CTL_SC7280_MASK,
58
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
59
55
}, {
60
56
.name = "ctl_4", .id = CTL_4,
61
57
.base = 0x19000, .len = 0x1e8,
62
-
.features = CTL_SC7280_MASK,
63
58
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
64
59
}, {
65
60
.name = "ctl_5", .id = CTL_5,
66
61
.base = 0x1a000, .len = 0x1e8,
67
-
.features = CTL_SC7280_MASK,
68
62
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
69
63
},
70
64
};
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
···
32
32
{
33
33
.name = "ctl_0", .id = CTL_0,
34
34
.base = 0x15000, .len = 0x1e8,
35
-
.features = CTL_SC7280_MASK,
36
35
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
37
36
}, {
38
37
.name = "ctl_1", .id = CTL_1,
39
38
.base = 0x16000, .len = 0x1e8,
40
-
.features = CTL_SC7280_MASK,
41
39
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
42
40
}, {
43
41
.name = "ctl_2", .id = CTL_2,
44
42
.base = 0x17000, .len = 0x1e8,
45
-
.features = CTL_SC7280_MASK,
46
43
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
47
44
}, {
48
45
.name = "ctl_3", .id = CTL_3,
49
46
.base = 0x18000, .len = 0x1e8,
50
-
.features = CTL_SC7280_MASK,
51
47
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
52
48
},
53
49
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
···
39
39
{
40
40
.name = "ctl_0", .id = CTL_0,
41
41
.base = 0x15000, .len = 0x204,
42
-
.features = CTL_SC7280_MASK,
43
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44
43
}, {
45
44
.name = "ctl_1", .id = CTL_1,
46
45
.base = 0x16000, .len = 0x204,
47
-
.features = CTL_SC7280_MASK,
48
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49
47
}, {
50
48
.name = "ctl_2", .id = CTL_2,
51
49
.base = 0x17000, .len = 0x204,
52
-
.features = CTL_SC7280_MASK,
53
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54
51
}, {
55
52
.name = "ctl_3", .id = CTL_3,
56
53
.base = 0x18000, .len = 0x204,
57
-
.features = CTL_SC7280_MASK,
58
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
59
55
}, {
60
56
.name = "ctl_4", .id = CTL_4,
61
57
.base = 0x19000, .len = 0x204,
62
-
.features = CTL_SC7280_MASK,
63
58
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
64
59
}, {
65
60
.name = "ctl_5", .id = CTL_5,
66
61
.base = 0x1a000, .len = 0x204,
67
-
.features = CTL_SC7280_MASK,
68
62
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
69
63
},
70
64
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
···
40
40
{
41
41
.name = "ctl_0", .id = CTL_0,
42
42
.base = 0x15000, .len = 0x204,
43
-
.features = CTL_SC7280_MASK,
44
43
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
45
44
}, {
46
45
.name = "ctl_1", .id = CTL_1,
47
46
.base = 0x16000, .len = 0x204,
48
-
.features = CTL_SC7280_MASK,
49
47
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
50
48
}, {
51
49
.name = "ctl_2", .id = CTL_2,
52
50
.base = 0x17000, .len = 0x204,
53
-
.features = CTL_SC7280_MASK,
54
51
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
55
52
}, {
56
53
.name = "ctl_3", .id = CTL_3,
57
54
.base = 0x18000, .len = 0x204,
58
-
.features = CTL_SC7280_MASK,
59
55
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
60
56
}, {
61
57
.name = "ctl_4", .id = CTL_4,
62
58
.base = 0x19000, .len = 0x204,
63
-
.features = CTL_SC7280_MASK,
64
59
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
65
60
}, {
66
61
.name = "ctl_5", .id = CTL_5,
67
62
.base = 0x1a000, .len = 0x204,
68
-
.features = CTL_SC7280_MASK,
69
63
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
70
64
},
71
65
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
···
39
39
{
40
40
.name = "ctl_0", .id = CTL_0,
41
41
.base = 0x15000, .len = 0x204,
42
-
.features = CTL_SC7280_MASK,
43
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44
43
}, {
45
44
.name = "ctl_1", .id = CTL_1,
46
45
.base = 0x16000, .len = 0x204,
47
-
.features = CTL_SC7280_MASK,
48
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49
47
}, {
50
48
.name = "ctl_2", .id = CTL_2,
51
49
.base = 0x17000, .len = 0x204,
52
-
.features = CTL_SC7280_MASK,
53
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54
51
}, {
55
52
.name = "ctl_3", .id = CTL_3,
56
53
.base = 0x18000, .len = 0x204,
57
-
.features = CTL_SC7280_MASK,
58
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
59
55
}, {
60
56
.name = "ctl_4", .id = CTL_4,
61
57
.base = 0x19000, .len = 0x204,
62
-
.features = CTL_SC7280_MASK,
63
58
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
64
59
}, {
65
60
.name = "ctl_5", .id = CTL_5,
66
61
.base = 0x1a000, .len = 0x204,
67
-
.features = CTL_SC7280_MASK,
68
62
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
69
63
},
70
64
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
···
31
31
{
32
32
.name = "ctl_0", .id = CTL_0,
33
33
.base = 0x15000, .len = 0x290,
34
-
.features = CTL_SC7280_MASK,
35
34
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36
35
}, {
37
36
.name = "ctl_1", .id = CTL_1,
38
37
.base = 0x16000, .len = 0x290,
39
-
.features = CTL_SC7280_MASK,
40
38
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41
39
}, {
42
40
.name = "ctl_2", .id = CTL_2,
43
41
.base = 0x17000, .len = 0x290,
44
-
.features = CTL_SC7280_MASK,
45
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
46
43
}, {
47
44
.name = "ctl_3", .id = CTL_3,
48
45
.base = 0x18000, .len = 0x290,
49
-
.features = CTL_SC7280_MASK,
50
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
51
47
}, {
52
48
.name = "ctl_4", .id = CTL_4,
53
49
.base = 0x19000, .len = 0x290,
54
-
.features = CTL_SC7280_MASK,
55
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
56
51
}, {
57
52
.name = "ctl_5", .id = CTL_5,
58
53
.base = 0x1a000, .len = 0x290,
59
-
.features = CTL_SC7280_MASK,
60
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
61
55
},
62
56
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
···
31
31
{
32
32
.name = "ctl_0", .id = CTL_0,
33
33
.base = 0x15000, .len = 0x290,
34
-
.features = CTL_SC7280_MASK,
35
34
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36
35
}, {
37
36
.name = "ctl_1", .id = CTL_1,
38
37
.base = 0x16000, .len = 0x290,
39
-
.features = CTL_SC7280_MASK,
40
38
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41
39
}, {
42
40
.name = "ctl_2", .id = CTL_2,
43
41
.base = 0x17000, .len = 0x290,
44
-
.features = CTL_SC7280_MASK,
45
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
46
43
}, {
47
44
.name = "ctl_3", .id = CTL_3,
48
45
.base = 0x18000, .len = 0x290,
49
-
.features = CTL_SC7280_MASK,
50
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
51
47
}, {
52
48
.name = "ctl_4", .id = CTL_4,
53
49
.base = 0x19000, .len = 0x290,
54
-
.features = CTL_SC7280_MASK,
55
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
56
51
}, {
57
52
.name = "ctl_5", .id = CTL_5,
58
53
.base = 0x1a000, .len = 0x290,
59
-
.features = CTL_SC7280_MASK,
60
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
61
55
},
62
56
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
···
30
30
{
31
31
.name = "ctl_0", .id = CTL_0,
32
32
.base = 0x15000, .len = 0x290,
33
-
.features = CTL_SC7280_MASK,
34
33
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
35
34
}, {
36
35
.name = "ctl_1", .id = CTL_1,
37
36
.base = 0x16000, .len = 0x290,
38
-
.features = CTL_SC7280_MASK,
39
37
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
40
38
}, {
41
39
.name = "ctl_2", .id = CTL_2,
42
40
.base = 0x17000, .len = 0x290,
43
-
.features = CTL_SC7280_MASK,
44
41
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
45
42
}, {
46
43
.name = "ctl_3", .id = CTL_3,
47
44
.base = 0x18000, .len = 0x290,
48
-
.features = CTL_SC7280_MASK,
49
45
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
50
46
}, {
51
47
.name = "ctl_4", .id = CTL_4,
52
48
.base = 0x19000, .len = 0x290,
53
-
.features = CTL_SC7280_MASK,
54
49
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
55
50
}, {
56
51
.name = "ctl_5", .id = CTL_5,
57
52
.base = 0x1a000, .len = 0x290,
58
-
.features = CTL_SC7280_MASK,
59
53
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
60
54
},
61
55
};
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
132
132
/**
133
133
* CTL sub-blocks
134
134
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
135
-
* @DPU_CTL_VM_CFG: CTL config to support multiple VMs
136
135
* @DPU_CTL_MAX
137
136
*/
138
137
enum {
139
138
DPU_CTL_SPLIT_DISPLAY = 0x1,
140
-
DPU_CTL_VM_CFG,
141
139
DPU_CTL_MAX
142
140
};
143
141
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
···
575
575
* per VM. Explicitly disable it until VM support is
576
576
* added in SW. Power on reset value is not disable.
577
577
*/
578
-
if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
578
+
if (ctx->mdss_ver->core_major_ver >= 7)
579
579
mode_sel = CTL_DEFAULT_GROUP_ID << 28;
580
580
581
581
if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)