Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'i3c/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
Pull i3c updates from Alexandre Belloni:
"Core:
- avoid possible deadlock on probe
- ensured preferred address is used on hot-join
Drivers:
- dw: add AMD I3C controller support
- mipi-i3c-hci: fix SETDASA, DMA interrupts fixes
- svc: many fixes for IBI and hotjoin"
* tag 'i3c/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux:
i3c: Use i3cdev->desc->info instead of calling i3c_device_get_info() to avoid deadlock
i3c: mipi-i3c-hci: Support SETDASA CCC
i3c: dw: Add quirk to address OD/PP timing issue on AMD platform
i3c: dw: Add support for AMDI0015 ACPI ID
i3c: master: svc: Modify enabled_events bit 7:0 to act as IBI enable counter
i3c: Document I3C_ADDR_SLOT_EXT_STATUS_MASK
i3c: master: svc: Fix pm_runtime_set_suspended() with runtime pm enabled
i3c: mipi-i3c-hci: Handle interrupts according to current specifications
i3c: mipi-i3c-hci: Mask ring interrupts before ring stop request
i3c: master: Fix miss free init_dyn_addr at i3c_master_put_i3c_addrs()
i3c: master: Remove i3c_dev_disable_ibi_locked(olddev) on device hotjoin
i3c: master: svc: fix possible assignment of the same address to two devices
i3c: master: svc: wait for Manual ACK/NACK Done before next step
i3c: master: svc: use spin_lock_irqsave at svc_i3c_master_ibi_work()
i3c: master: svc: need check IBIWON for dynamic address assignment
i3c: master: svc: manually emit NACK/ACK for hotjoin
i3c: master: svc: use repeat start when IBI WIN happens
i3c: master: Fix dynamic address leak when 'assigned-address' is present
i3c: master: Extend address status bit to 4 and add I3C_ADDR_SLOT_EXT_DESIRED
i3c: master: Replace hard code 2 with macro I3C_ADDR_SLOT_STATUS_BITS
+225
-89
+72
-28
drivers/i3c/master.c
+72
-28
drivers/i3c/master.c
···
282
282
struct i3c_device_info devinfo;
283
283
u16 manuf, part, ext;
284
284
285
-
i3c_device_get_info(i3cdev, &devinfo);
285
+
if (i3cdev->desc)
286
+
devinfo = i3cdev->desc->info;
286
287
manuf = I3C_PID_MANUF_ID(devinfo.pid);
287
288
part = I3C_PID_PART_ID(devinfo.pid);
288
289
ext = I3C_PID_EXTRA_INFO(devinfo.pid);
···
346
345
EXPORT_SYMBOL_GPL(i3c_bus_type);
347
346
348
347
static enum i3c_addr_slot_status
349
-
i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr)
348
+
i3c_bus_get_addr_slot_status_mask(struct i3c_bus *bus, u16 addr, u32 mask)
350
349
{
351
350
unsigned long status;
352
-
int bitpos = addr * 2;
351
+
int bitpos = addr * I3C_ADDR_SLOT_STATUS_BITS;
353
352
354
353
if (addr > I2C_MAX_ADDR)
355
354
return I3C_ADDR_SLOT_RSVD;
···
357
356
status = bus->addrslots[bitpos / BITS_PER_LONG];
358
357
status >>= bitpos % BITS_PER_LONG;
359
358
360
-
return status & I3C_ADDR_SLOT_STATUS_MASK;
359
+
return status & mask;
361
360
}
362
361
363
-
static void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
364
-
enum i3c_addr_slot_status status)
362
+
static enum i3c_addr_slot_status
363
+
i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr)
365
364
{
366
-
int bitpos = addr * 2;
365
+
return i3c_bus_get_addr_slot_status_mask(bus, addr, I3C_ADDR_SLOT_STATUS_MASK);
366
+
}
367
+
368
+
static void i3c_bus_set_addr_slot_status_mask(struct i3c_bus *bus, u16 addr,
369
+
enum i3c_addr_slot_status status, u32 mask)
370
+
{
371
+
int bitpos = addr * I3C_ADDR_SLOT_STATUS_BITS;
367
372
unsigned long *ptr;
368
373
369
374
if (addr > I2C_MAX_ADDR)
370
375
return;
371
376
372
377
ptr = bus->addrslots + (bitpos / BITS_PER_LONG);
373
-
*ptr &= ~((unsigned long)I3C_ADDR_SLOT_STATUS_MASK <<
374
-
(bitpos % BITS_PER_LONG));
375
-
*ptr |= (unsigned long)status << (bitpos % BITS_PER_LONG);
378
+
*ptr &= ~((unsigned long)mask << (bitpos % BITS_PER_LONG));
379
+
*ptr |= ((unsigned long)status & mask) << (bitpos % BITS_PER_LONG);
380
+
}
381
+
382
+
static void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
383
+
enum i3c_addr_slot_status status)
384
+
{
385
+
i3c_bus_set_addr_slot_status_mask(bus, addr, status, I3C_ADDR_SLOT_STATUS_MASK);
376
386
}
377
387
378
388
static bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr)
···
395
383
return status == I3C_ADDR_SLOT_FREE;
396
384
}
397
385
386
+
/*
387
+
* ┌────┬─────────────┬───┬─────────┬───┐
388
+
* │S/Sr│ 7'h7E RnW=0 │ACK│ ENTDAA │ T ├────┐
389
+
* └────┴─────────────┴───┴─────────┴───┘ │
390
+
* ┌─────────────────────────────────────────┘
391
+
* │ ┌──┬─────────────┬───┬─────────────────┬────────────────┬───┬─────────┐
392
+
* └─►│Sr│7'h7E RnW=1 │ACK│48bit UID BCR DCR│Assign 7bit Addr│PAR│ ACK/NACK│
393
+
* └──┴─────────────┴───┴─────────────────┴────────────────┴───┴─────────┘
394
+
* Some master controllers (such as HCI) need to prepare the entire above transaction before
395
+
* sending it out to the I3C bus. This means that a 7-bit dynamic address needs to be allocated
396
+
* before knowing the target device's UID information.
397
+
*
398
+
* However, some I3C targets may request specific addresses (called as "init_dyn_addr"), which is
399
+
* typically specified by the DT-'s assigned-address property. Lower addresses having higher IBI
400
+
* priority. If it is available, i3c_bus_get_free_addr() preferably return a free address that is
401
+
* not in the list of desired addresses (called as "init_dyn_addr"). This allows the device with
402
+
* the "init_dyn_addr" to switch to its "init_dyn_addr" when it hot-joins the I3C bus. Otherwise,
403
+
* if the "init_dyn_addr" is already in use by another I3C device, the target device will not be
404
+
* able to switch to its desired address.
405
+
*
406
+
* If the previous step fails, fallback returning one of the remaining unassigned address,
407
+
* regardless of its state in the desired list.
408
+
*/
398
409
static int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr)
399
410
{
400
411
enum i3c_addr_slot_status status;
401
412
u8 addr;
402
413
403
414
for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) {
404
-
status = i3c_bus_get_addr_slot_status(bus, addr);
415
+
status = i3c_bus_get_addr_slot_status_mask(bus, addr,
416
+
I3C_ADDR_SLOT_EXT_STATUS_MASK);
417
+
if (status == I3C_ADDR_SLOT_FREE)
418
+
return addr;
419
+
}
420
+
421
+
for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) {
422
+
status = i3c_bus_get_addr_slot_status_mask(bus, addr,
423
+
I3C_ADDR_SLOT_STATUS_MASK);
405
424
if (status == I3C_ADDR_SLOT_FREE)
406
425
return addr;
407
426
}
···
1460
1417
I3C_ADDR_SLOT_FREE);
1461
1418
1462
1419
if (dev->boardinfo && dev->boardinfo->init_dyn_addr)
1463
-
i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
1420
+
i3c_bus_set_addr_slot_status(&master->bus, dev->boardinfo->init_dyn_addr,
1464
1421
I3C_ADDR_SLOT_FREE);
1465
1422
}
1466
1423
···
1549
1506
u8 old_dyn_addr)
1550
1507
{
1551
1508
struct i3c_master_controller *master = i3c_dev_get_master(dev);
1552
-
enum i3c_addr_slot_status status;
1553
1509
int ret;
1554
1510
1555
-
if (dev->info.dyn_addr != old_dyn_addr &&
1556
-
(!dev->boardinfo ||
1557
-
dev->info.dyn_addr != dev->boardinfo->init_dyn_addr)) {
1558
-
status = i3c_bus_get_addr_slot_status(&master->bus,
1559
-
dev->info.dyn_addr);
1560
-
if (status != I3C_ADDR_SLOT_FREE)
1561
-
return -EBUSY;
1511
+
if (dev->info.dyn_addr != old_dyn_addr) {
1562
1512
i3c_bus_set_addr_slot_status(&master->bus,
1563
1513
dev->info.dyn_addr,
1564
1514
I3C_ADDR_SLOT_I3C_DEV);
···
1954
1918
goto err_rstdaa;
1955
1919
}
1956
1920
1957
-
i3c_bus_set_addr_slot_status(&master->bus,
1958
-
i3cboardinfo->init_dyn_addr,
1959
-
I3C_ADDR_SLOT_I3C_DEV);
1921
+
/* Do not mark as occupied until real device exist in bus */
1922
+
i3c_bus_set_addr_slot_status_mask(&master->bus,
1923
+
i3cboardinfo->init_dyn_addr,
1924
+
I3C_ADDR_SLOT_EXT_DESIRED,
1925
+
I3C_ADDR_SLOT_EXT_STATUS_MASK);
1960
1926
1961
1927
/*
1962
1928
* Only try to create/attach devices that have a static
···
2089
2051
ibireq.max_payload_len = olddev->ibi->max_payload_len;
2090
2052
ibireq.num_slots = olddev->ibi->num_slots;
2091
2053
2092
-
if (olddev->ibi->enabled) {
2054
+
if (olddev->ibi->enabled)
2093
2055
enable_ibi = true;
2094
-
i3c_dev_disable_ibi_locked(olddev);
2095
-
}
2096
-
2056
+
/*
2057
+
* The olddev should not receive any commands on the
2058
+
* i3c bus as it does not exist and has been assigned
2059
+
* a new address. This will result in NACK or timeout.
2060
+
* So, update the olddev->ibi->enabled flag to false
2061
+
* to avoid DISEC with OldAddr.
2062
+
*/
2063
+
olddev->ibi->enabled = false;
2097
2064
i3c_dev_free_ibi_locked(olddev);
2098
2065
}
2099
2066
mutex_unlock(&olddev->ibi_lock);
···
2126
2083
else
2127
2084
expected_dyn_addr = newdev->info.dyn_addr;
2128
2085
2129
-
if (newdev->info.dyn_addr != expected_dyn_addr) {
2086
+
if (newdev->info.dyn_addr != expected_dyn_addr &&
2087
+
i3c_bus_get_addr_slot_status(&master->bus, expected_dyn_addr) == I3C_ADDR_SLOT_FREE) {
2130
2088
/*
2131
2089
* Try to apply the expected dynamic address. If it fails, keep
2132
2090
* the address assigned by the master.
+34
drivers/i3c/master/dw-i3c-master.c
+34
drivers/i3c/master/dw-i3c-master.c
···
220
220
221
221
#define XFER_TIMEOUT (msecs_to_jiffies(1000))
222
222
#define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */
223
+
224
+
/* Timing values to configure 12.5MHz frequency */
225
+
#define AMD_I3C_OD_TIMING 0x4C007C
226
+
#define AMD_I3C_PP_TIMING 0x8001A
227
+
228
+
/* List of quirks */
229
+
#define AMD_I3C_OD_PP_TIMING BIT(1)
230
+
223
231
struct dw_i3c_cmd {
224
232
u32 cmd_lo;
225
233
u32 cmd_hi;
···
802
794
return ret;
803
795
}
804
796
797
+
static void amd_configure_od_pp_quirk(struct dw_i3c_master *master)
798
+
{
799
+
master->i3c_od_timing = AMD_I3C_OD_TIMING;
800
+
master->i3c_pp_timing = AMD_I3C_PP_TIMING;
801
+
}
802
+
805
803
static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
806
804
struct i3c_ccc_cmd *ccc)
807
805
{
···
816
802
817
803
if (ccc->id == I3C_CCC_ENTDAA)
818
804
return -EINVAL;
805
+
806
+
/* AMD platform specific OD and PP timings */
807
+
if (master->quirks & AMD_I3C_OD_PP_TIMING) {
808
+
amd_configure_od_pp_quirk(master);
809
+
writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
810
+
writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
811
+
}
819
812
820
813
ret = pm_runtime_resume_and_get(master->dev);
821
814
if (ret < 0) {
···
1623
1602
master->maxdevs = ret >> 16;
1624
1603
master->free_pos = GENMASK(master->maxdevs - 1, 0);
1625
1604
1605
+
master->quirks = (unsigned long)device_get_match_data(&pdev->dev);
1606
+
1626
1607
INIT_WORK(&master->hj_work, dw_i3c_hj_work);
1627
1608
ret = i3c_master_register(&master->base, &pdev->dev,
1628
1609
&dw_mipi_i3c_ops, false);
···
1698
1675
1699
1676
static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master)
1700
1677
{
1678
+
/* AMD platform specific OD and PP timings */
1679
+
if (master->quirks & AMD_I3C_OD_PP_TIMING)
1680
+
amd_configure_od_pp_quirk(master);
1681
+
1701
1682
writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
1702
1683
writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING);
1703
1684
writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
···
1775
1748
};
1776
1749
MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
1777
1750
1751
+
static const struct acpi_device_id amd_i3c_device_match[] = {
1752
+
{ "AMDI0015", AMD_I3C_OD_PP_TIMING },
1753
+
{ }
1754
+
};
1755
+
MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match);
1756
+
1778
1757
static struct platform_driver dw_i3c_driver = {
1779
1758
.probe = dw_i3c_probe,
1780
1759
.remove_new = dw_i3c_remove,
1781
1760
.driver = {
1782
1761
.name = "dw-i3c-master",
1783
1762
.of_match_table = dw_i3c_master_of_match,
1763
+
.acpi_match_table = amd_i3c_device_match,
1784
1764
.pm = &dw_i3c_pm_ops,
1785
1765
},
1786
1766
};
+1
drivers/i3c/master/dw-i3c-master.h
+1
drivers/i3c/master/dw-i3c-master.h
+5
-14
drivers/i3c/master/mipi-i3c-hci/core.c
+5
-14
drivers/i3c/master/mipi-i3c-hci/core.c
···
80
80
#define INTR_HC_CMD_SEQ_UFLOW_STAT BIT(12) /* Cmd Sequence Underflow */
81
81
#define INTR_HC_RESET_CANCEL BIT(11) /* HC Cancelled Reset */
82
82
#define INTR_HC_INTERNAL_ERR BIT(10) /* HC Internal Error */
83
-
#define INTR_HC_PIO BIT(8) /* cascaded PIO interrupt */
84
-
#define INTR_HC_RINGS GENMASK(7, 0)
85
83
86
84
#define DAT_SECTION 0x30 /* Device Address Table */
87
85
#define DAT_ENTRY_SIZE GENMASK(31, 28)
···
436
438
kfree(dev_data);
437
439
return ret;
438
440
}
439
-
mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, ret, dev->info.dyn_addr);
441
+
mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, ret,
442
+
dev->info.dyn_addr ?: dev->info.static_addr);
440
443
dev_data->dat_idx = ret;
441
444
}
442
445
i3c_dev_set_master_data(dev, dev_data);
···
596
597
597
598
if (val) {
598
599
reg_write(INTR_STATUS, val);
599
-
} else {
600
-
/* v1.0 does not have PIO cascaded notification bits */
601
-
val |= INTR_HC_PIO;
602
600
}
603
601
604
602
if (val & INTR_HC_RESET_CANCEL) {
···
606
610
dev_err(&hci->master.dev, "Host Controller Internal Error\n");
607
611
val &= ~INTR_HC_INTERNAL_ERR;
608
612
}
609
-
if (val & INTR_HC_PIO) {
610
-
hci->io->irq_handler(hci, 0);
611
-
val &= ~INTR_HC_PIO;
612
-
}
613
-
if (val & INTR_HC_RINGS) {
614
-
hci->io->irq_handler(hci, val & INTR_HC_RINGS);
615
-
val &= ~INTR_HC_RINGS;
616
-
}
613
+
614
+
hci->io->irq_handler(hci);
615
+
617
616
if (val)
618
617
dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val);
619
618
else
+3
-7
drivers/i3c/master/mipi-i3c-hci/dma.c
+3
-7
drivers/i3c/master/mipi-i3c-hci/dma.c
···
159
159
for (i = 0; i < rings->total; i++) {
160
160
rh = &rings->headers[i];
161
161
162
+
rh_reg_write(INTR_SIGNAL_ENABLE, 0);
162
163
rh_reg_write(RING_CONTROL, 0);
163
164
rh_reg_write(CR_SETUP, 0);
164
165
rh_reg_write(IBI_SETUP, 0);
165
-
rh_reg_write(INTR_SIGNAL_ENABLE, 0);
166
166
167
167
if (rh->xfer)
168
168
dma_free_coherent(&hci->master.dev,
···
733
733
rh_reg_write(CHUNK_CONTROL, rh_reg_read(CHUNK_CONTROL) + ibi_chunks);
734
734
}
735
735
736
-
static bool hci_dma_irq_handler(struct i3c_hci *hci, unsigned int mask)
736
+
static bool hci_dma_irq_handler(struct i3c_hci *hci)
737
737
{
738
738
struct hci_rings_data *rings = hci->io_data;
739
739
unsigned int i;
740
740
bool handled = false;
741
741
742
-
for (i = 0; mask && i < rings->total; i++) {
742
+
for (i = 0; i < rings->total; i++) {
743
743
struct hci_rh_data *rh;
744
744
u32 status;
745
-
746
-
if (!(mask & BIT(i)))
747
-
continue;
748
-
mask &= ~BIT(i);
749
745
750
746
rh = &rings->headers[i];
751
747
status = rh_reg_read(INTR_STATUS);
+1
-1
drivers/i3c/master/mipi-i3c-hci/hci.h
+1
-1
drivers/i3c/master/mipi-i3c-hci/hci.h
···
115
115
116
116
/* This abstracts PIO vs DMA operations */
117
117
struct hci_io_ops {
118
-
bool (*irq_handler)(struct i3c_hci *hci, unsigned int mask);
118
+
bool (*irq_handler)(struct i3c_hci *hci);
119
119
int (*queue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
120
120
bool (*dequeue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
121
121
int (*request_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
+1
-1
drivers/i3c/master/mipi-i3c-hci/pio.c
+1
-1
drivers/i3c/master/mipi-i3c-hci/pio.c
+100
-36
drivers/i3c/master/svc-i3c-master.c
+100
-36
drivers/i3c/master/svc-i3c-master.c
···
130
130
#define SVC_I3C_PPBAUD_MAX 15
131
131
#define SVC_I3C_QUICK_I2C_CLK 4170000
132
132
133
-
#define SVC_I3C_EVENT_IBI BIT(0)
134
-
#define SVC_I3C_EVENT_HOTJOIN BIT(1)
133
+
#define SVC_I3C_EVENT_IBI GENMASK(7, 0)
134
+
#define SVC_I3C_EVENT_HOTJOIN BIT(31)
135
135
136
136
struct svc_i3c_cmd {
137
137
u8 addr;
···
214
214
spinlock_t lock;
215
215
} ibi;
216
216
struct mutex lock;
217
-
int enabled_events;
217
+
u32 enabled_events;
218
218
u32 mctrl_config;
219
219
};
220
220
···
388
388
return 0;
389
389
}
390
390
391
-
static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master,
391
+
static int svc_i3c_master_ack_ibi(struct svc_i3c_master *master,
392
392
bool mandatory_byte)
393
393
{
394
394
unsigned int ibi_ack_nack;
395
+
u32 reg;
395
396
396
397
ibi_ack_nack = SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK;
397
398
if (mandatory_byte)
···
401
400
ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE;
402
401
403
402
writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL);
403
+
404
+
return readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
405
+
SVC_I3C_MSTATUS_MCTRLDONE(reg), 1, 1000);
406
+
404
407
}
405
408
406
-
static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master)
409
+
static int svc_i3c_master_nack_ibi(struct svc_i3c_master *master)
407
410
{
411
+
int ret;
412
+
u32 reg;
413
+
408
414
writel(SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK |
409
415
SVC_I3C_MCTRL_IBIRESP_NACK,
410
416
master->regs + SVC_I3C_MCTRL);
417
+
418
+
ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
419
+
SVC_I3C_MSTATUS_MCTRLDONE(reg), 1, 1000);
420
+
return ret;
421
+
}
422
+
423
+
static int svc_i3c_master_handle_ibi_won(struct svc_i3c_master *master, u32 mstatus)
424
+
{
425
+
u32 ibitype;
426
+
int ret = 0;
427
+
428
+
ibitype = SVC_I3C_MSTATUS_IBITYPE(mstatus);
429
+
430
+
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
431
+
432
+
/* Hardware can't auto emit NACK for hot join and master request */
433
+
switch (ibitype) {
434
+
case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:
435
+
case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
436
+
ret = svc_i3c_master_nack_ibi(master);
437
+
}
438
+
439
+
return ret;
411
440
}
412
441
413
442
static void svc_i3c_master_ibi_work(struct work_struct *work)
···
449
418
u32 status, val;
450
419
int ret;
451
420
452
-
mutex_lock(&master->lock);
421
+
/*
422
+
* According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5:
423
+
*
424
+
* The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C
425
+
* transfer. But maximum stall time is 100us. The IRQs have to be disabled to prevent
426
+
* schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if
427
+
* any irq or schedule happen during transaction.
428
+
*/
429
+
guard(spinlock_irqsave)(&master->xferqueue.lock);
430
+
453
431
/*
454
432
* IBIWON may be set before SVC_I3C_MCTRL_REQUEST_AUTO_IBI, causing
455
433
* readl_relaxed_poll_timeout() to return immediately. Consequently,
···
478
438
master->regs + SVC_I3C_MCTRL);
479
439
480
440
/* Wait for IBIWON, should take approximately 100us */
481
-
ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
482
-
SVC_I3C_MSTATUS_IBIWON(val), 0, 1000);
441
+
ret = readl_relaxed_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, val,
442
+
SVC_I3C_MSTATUS_IBIWON(val), 0, 100);
483
443
if (ret) {
484
444
dev_err(master->dev, "Timeout when polling for IBIWON\n");
485
445
svc_i3c_master_emit_stop(master);
···
551
511
552
512
reenable_ibis:
553
513
svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
554
-
mutex_unlock(&master->lock);
555
514
}
556
515
557
516
static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
···
893
854
int ret, i;
894
855
895
856
while (true) {
857
+
/* clean SVC_I3C_MINT_IBIWON w1c bits */
858
+
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
859
+
896
860
/* SVC_I3C_MCTRL_REQUEST_PROC_DAA have two mode, ENTER DAA or PROCESS DAA.
897
861
*
898
862
* ENTER DAA:
···
947
905
ret = svc_i3c_master_readb(master, data, 2);
948
906
if (ret)
949
907
break;
908
+
} else if (SVC_I3C_MSTATUS_IBIWON(reg)) {
909
+
ret = svc_i3c_master_handle_ibi_won(master, reg);
910
+
if (ret)
911
+
break;
912
+
continue;
950
913
} else if (SVC_I3C_MSTATUS_MCTRLDONE(reg)) {
951
914
if (SVC_I3C_MSTATUS_STATE_IDLE(reg) &&
952
915
SVC_I3C_MSTATUS_COMPLETE(reg)) {
···
1103
1056
if (ret)
1104
1057
goto rpm_out;
1105
1058
1106
-
/* Register all devices who participated to the core */
1107
-
for (i = 0; i < dev_nb; i++) {
1108
-
ret = i3c_master_add_i3c_dev_locked(m, addrs[i]);
1109
-
if (ret)
1110
-
goto rpm_out;
1111
-
}
1059
+
/*
1060
+
* Register all devices who participated to the core
1061
+
*
1062
+
* If two devices (A and B) are detected in DAA and address 0xa is assigned to
1063
+
* device A and 0xb to device B, a failure in i3c_master_add_i3c_dev_locked()
1064
+
* for device A (addr: 0xa) could prevent device B (addr: 0xb) from being
1065
+
* registered on the bus. The I3C stack might still consider 0xb a free
1066
+
* address. If a subsequent Hotjoin occurs, 0xb might be assigned to Device A,
1067
+
* causing both devices A and B to use the same address 0xb, violating the I3C
1068
+
* specification.
1069
+
*
1070
+
* The return value for i3c_master_add_i3c_dev_locked() should not be checked
1071
+
* because subsequent steps will scan the entire I3C bus, independent of
1072
+
* whether i3c_master_add_i3c_dev_locked() returns success.
1073
+
*
1074
+
* If device A registration fails, there is still a chance to register device
1075
+
* B. i3c_master_add_i3c_dev_locked() can reset DAA if a failure occurs while
1076
+
* retrieving device information.
1077
+
*/
1078
+
for (i = 0; i < dev_nb; i++)
1079
+
i3c_master_add_i3c_dev_locked(m, addrs[i]);
1112
1080
1113
1081
/* Configure IBI auto-rules */
1114
1082
ret = svc_i3c_update_ibirules(master);
···
1225
1163
if (ret)
1226
1164
goto emit_stop;
1227
1165
1166
+
/*
1167
+
* According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a
1168
+
* Frame with I3C Target Address.
1169
+
*
1170
+
* The I3C Controller normally should start a Frame, the Address may be arbitrated,
1171
+
* and so the Controller shall monitor to see whether an In-Band Interrupt request,
1172
+
* a Controller Role Request (i.e., Secondary Controller requests to become the
1173
+
* Active Controller), or a Hot-Join Request has been made.
1174
+
*
1175
+
* If missed IBIWON check, the wrong data will be return. When IBIWON happen, issue
1176
+
* repeat start. Address arbitrate only happen at START, never happen at REPEAT
1177
+
* start.
1178
+
*/
1179
+
if (SVC_I3C_MSTATUS_IBIWON(reg)) {
1180
+
ret = svc_i3c_master_handle_ibi_won(master, reg);
1181
+
if (ret)
1182
+
goto emit_stop;
1183
+
continue;
1184
+
}
1185
+
1228
1186
if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
1229
1187
/*
1230
1188
* According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3.
···
1276
1194
} else {
1277
1195
break;
1278
1196
}
1279
-
}
1280
-
1281
-
/*
1282
-
* According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a Frame
1283
-
* with I3C Target Address.
1284
-
*
1285
-
* The I3C Controller normally should start a Frame, the Address may be arbitrated, and so
1286
-
* the Controller shall monitor to see whether an In-Band Interrupt request, a Controller
1287
-
* Role Request (i.e., Secondary Controller requests to become the Active Controller), or
1288
-
* a Hot-Join Request has been made.
1289
-
*
1290
-
* If missed IBIWON check, the wrong data will be return. When IBIWON happen, return failure
1291
-
* and yield the above events handler.
1292
-
*/
1293
-
if (SVC_I3C_MSTATUS_IBIWON(reg)) {
1294
-
ret = -EAGAIN;
1295
-
*actual_len = 0;
1296
-
goto emit_stop;
1297
1197
}
1298
1198
1299
1199
if (rnw)
···
1688
1624
return ret;
1689
1625
}
1690
1626
1691
-
master->enabled_events |= SVC_I3C_EVENT_IBI;
1627
+
master->enabled_events++;
1692
1628
svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
1693
1629
1694
1630
return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
···
1700
1636
struct svc_i3c_master *master = to_svc_i3c_master(m);
1701
1637
int ret;
1702
1638
1703
-
master->enabled_events &= ~SVC_I3C_EVENT_IBI;
1639
+
master->enabled_events--;
1704
1640
if (!master->enabled_events)
1705
1641
svc_i3c_master_disable_interrupts(master);
1706
1642
···
1891
1827
rpm_disable:
1892
1828
pm_runtime_dont_use_autosuspend(&pdev->dev);
1893
1829
pm_runtime_put_noidle(&pdev->dev);
1894
-
pm_runtime_set_suspended(&pdev->dev);
1895
1830
pm_runtime_disable(&pdev->dev);
1831
+
pm_runtime_set_suspended(&pdev->dev);
1896
1832
1897
1833
err_disable_clks:
1898
1834
svc_i3c_master_unprepare_clks(master);
+8
-2
include/linux/i3c/master.h
+8
-2
include/linux/i3c/master.h
···
298
298
* @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
299
299
* @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
300
300
* @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
301
-
*
301
+
* @I3C_ADDR_SLOT_EXT_STATUS_MASK: address slot mask with extended information
302
+
* @I3C_ADDR_SLOT_EXT_DESIRED: the bitmask represents addresses that are preferred by some devices,
303
+
* such as the "assigned-address" property in a device tree source.
302
304
* On an I3C bus, addresses are assigned dynamically, and we need to know which
303
305
* addresses are free to use and which ones are already assigned.
304
306
*
···
313
311
I3C_ADDR_SLOT_I2C_DEV,
314
312
I3C_ADDR_SLOT_I3C_DEV,
315
313
I3C_ADDR_SLOT_STATUS_MASK = 3,
314
+
I3C_ADDR_SLOT_EXT_STATUS_MASK = 7,
315
+
I3C_ADDR_SLOT_EXT_DESIRED = BIT(2),
316
316
};
317
+
318
+
#define I3C_ADDR_SLOT_STATUS_BITS 4
317
319
318
320
/**
319
321
* struct i3c_bus - I3C bus object
···
360
354
struct i3c_bus {
361
355
struct i3c_dev_desc *cur_master;
362
356
int id;
363
-
unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
357
+
unsigned long addrslots[((I2C_MAX_ADDR + 1) * I3C_ADDR_SLOT_STATUS_BITS) / BITS_PER_LONG];
364
358
enum i3c_bus_mode mode;
365
359
struct {
366
360
unsigned long i3c;