tjh.dev / kernel
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Merge tag 'drm-fixes-2023-10-27' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"This is the final set of fixes for 6.6, just misc bits mainly in
amdgpu and i915, nothing too noteworthy.

amdgpu:
- ignore duplicated BOs in CS parser
- remove redundant call to amdgpu_ctx_priority_is_valid()
- Extend VI APSM quirks to more platforms

amdkfd:
- reserve fence slot while locking BO

dp_mst:
- Fix NULL deref in get_mst_branch_device_by_guid_helper()

logicvc:
- Kconfig: Select REGMAP and REGMAP_MMIO

ivpu:
- Fix missing VPUIP interrupts

i915:
- Determine context valid in OA reports
- Hold GT forcewake during steering operations
- Check if PMU is closed before stopping event"

* tag 'drm-fixes-2023-10-27' of git://anongit.freedesktop.org/drm/drm:
accel/ivpu/37xx: Fix missing VPUIP interrupts
drm/amd: Disable ASPM for VI w/ all Intel systems
drm/i915/pmu: Check if pmu is closed before stopping event
drm/i915/mcr: Hold GT forcewake during steering operations
drm/logicvc: Kconfig: select REGMAP and REGMAP_MMIO
drm/i915/perf: Determine context valid in OA reports
drm/amdkfd: reserve a fence slot while locking the BO
drm/amdgpu: Remove redundant call to priority_is_valid()
drm/dp_mst: Fix NULL deref in get_mst_branch_device_by_guid_helper()
drm/amdgpu: ignore duplicate BOs again

Linus Torvalds 750b9588 3a568e3a

+55 -23
+5 -6
drivers/accel/ivpu/ivpu_hw_37xx.c
··· 940 940 if (status == 0) 941 941 return 0; 942 942 943 - /* Disable global interrupt before handling local buttress interrupts */ 944 - REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); 945 - 946 943 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status)) 947 944 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", 948 945 REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL)); ··· 971 974 else 972 975 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status); 973 976 974 - /* Re-enable global interrupt */ 975 - REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); 976 - 977 977 if (schedule_recovery) 978 978 ivpu_pm_schedule_recovery(vdev); 979 979 ··· 982 988 struct ivpu_device *vdev = ptr; 983 989 u32 ret_irqv, ret_irqb; 984 990 991 + REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); 992 + 985 993 ret_irqv = ivpu_hw_37xx_irqv_handler(vdev, irq); 986 994 ret_irqb = ivpu_hw_37xx_irqb_handler(vdev, irq); 995 + 996 + /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ 997 + REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); 987 998 988 999 return IRQ_RETVAL(ret_irqb | ret_irqv); 989 1000 }
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 1103 1103 if (unlikely(ret)) 1104 1104 goto error; 1105 1105 1106 - ret = drm_exec_lock_obj(&ctx->exec, &bo->tbo.base); 1106 + ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1); 1107 1107 drm_exec_retry_on_contention(&ctx->exec); 1108 1108 if (unlikely(ret)) 1109 1109 goto error;
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
··· 65 65 } 66 66 67 67 amdgpu_sync_create(&p->sync); 68 - drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT); 68 + drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT | 69 + DRM_EXEC_IGNORE_DUPLICATES); 69 70 return 0; 70 71 } 71 72
+8 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
··· 55 55 return true; 56 56 default: 57 57 case AMDGPU_CTX_PRIORITY_UNSET: 58 + /* UNSET priority is not valid and we don't carry that 59 + * around, but set it to NORMAL in the only place this 60 + * function is called, amdgpu_ctx_ioctl(). 61 + */ 58 62 return false; 59 63 } 60 64 } ··· 99 95 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 100 96 int32_t priority) 101 97 { 102 - if (!amdgpu_ctx_priority_is_valid(priority)) 103 - return -EINVAL; 104 - 105 98 /* NORMAL and below are accessible by everyone */ 106 99 if (priority <= AMDGPU_CTX_PRIORITY_NORMAL) 107 100 return 0; ··· 633 632 return 0; 634 633 } 635 634 636 - 637 - 638 635 static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, 639 636 struct amdgpu_fpriv *fpriv, uint32_t id, 640 637 bool set, u32 *stable_pstate) ··· 675 676 id = args->in.ctx_id; 676 677 priority = args->in.priority; 677 678 678 - /* For backwards compatibility reasons, we need to accept 679 - * ioctls with garbage in the priority field */ 679 + /* For backwards compatibility, we need to accept ioctls with garbage 680 + * in the priority field. Garbage values in the priority field, result 681 + * in the priority being set to NORMAL. 682 + */ 680 683 if (!amdgpu_ctx_priority_is_valid(priority)) 681 684 priority = AMDGPU_CTX_PRIORITY_NORMAL; 682 685
+1 -1
drivers/gpu/drm/amd/amdgpu/vi.c
··· 1124 1124 bool bL1SS = false; 1125 1125 bool bClkReqSupport = true; 1126 1126 1127 - if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) 1127 + if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_pcie_dynamic_switching_supported()) 1128 1128 return; 1129 1129 1130 1130 if (adev->flags & AMD_IS_APU ||
+3 -3
drivers/gpu/drm/display/drm_dp_mst_topology.c
··· 2574 2574 struct drm_dp_mst_branch *found_mstb; 2575 2575 struct drm_dp_mst_port *port; 2576 2576 2577 + if (!mstb) 2578 + return NULL; 2579 + 2577 2580 if (memcmp(mstb->guid, guid, 16) == 0) 2578 2581 return mstb; 2579 2582 2580 2583 2581 2584 list_for_each_entry(port, &mstb->ports, next) { 2582 - if (!port->mstb) 2583 - continue; 2584 - 2585 2585 found_mstb = get_mst_branch_device_by_guid_helper(port->mstb, guid); 2586 2586 2587 2587 if (found_mstb)
+22 -2
drivers/gpu/drm/i915/gt/intel_gt_mcr.c
··· 376 376 * driver threads, but also with hardware/firmware agents. A dedicated 377 377 * locking register is used. 378 378 */ 379 - if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) 379 + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { 380 + /* 381 + * The steering control and semaphore registers are inside an 382 + * "always on" power domain with respect to RC6. However there 383 + * are some issues if higher-level platform sleep states are 384 + * entering/exiting at the same time these registers are 385 + * accessed. Grabbing GT forcewake and holding it over the 386 + * entire lock/steer/unlock cycle ensures that those sleep 387 + * states have been fully exited before we access these 388 + * registers. This wakeref will be released in the unlock 389 + * routine. 390 + * 391 + * This is expected to become a formally documented/numbered 392 + * workaround soon. 393 + */ 394 + intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_GT); 395 + 380 396 err = wait_for(intel_uncore_read_fw(gt->uncore, 381 397 MTL_STEER_SEMAPHORE) == 0x1, 100); 398 + } 382 399 383 400 /* 384 401 * Even on platforms with a hardware lock, we'll continue to grab ··· 432 415 { 433 416 spin_unlock_irqrestore(&gt->mcr_lock, flags); 434 417 435 - if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) 418 + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { 436 419 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); 420 + 421 + intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_GT); 422 + } 437 423 } 438 424 439 425 /**
+2 -2
drivers/gpu/drm/i915/i915_perf.c
··· 482 482 static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report) 483 483 { 484 484 return !(oa_report_id(stream, report) & 485 - stream->perf->gen8_valid_ctx_bit) && 486 - GRAPHICS_VER(stream->perf->i915) <= 11; 485 + stream->perf->gen8_valid_ctx_bit); 487 486 } 488 487 489 488 static u64 oa_timestamp(struct i915_perf_stream *stream, void *report) ··· 5105 5106 perf->gen8_valid_ctx_bit = BIT(16); 5106 5107 break; 5107 5108 case 12: 5109 + perf->gen8_valid_ctx_bit = BIT(16); 5108 5110 /* 5109 5111 * Calculate offset at runtime in oa_pin_context for gen12 and 5110 5112 * cache the value in perf->ctx_oactxctrl_offset.
+9
drivers/gpu/drm/i915/i915_pmu.c
··· 832 832 833 833 static void i915_pmu_event_stop(struct perf_event *event, int flags) 834 834 { 835 + struct drm_i915_private *i915 = 836 + container_of(event->pmu, typeof(*i915), pmu.base); 837 + struct i915_pmu *pmu = &i915->pmu; 838 + 839 + if (pmu->closed) 840 + goto out; 841 + 835 842 if (flags & PERF_EF_UPDATE) 836 843 i915_pmu_event_read(event); 837 844 i915_pmu_disable(event); 845 + 846 + out: 838 847 event->hw.state = PERF_HES_STOPPED; 839 848 } 840 849
+2
drivers/gpu/drm/logicvc/Kconfig
··· 5 5 select DRM_KMS_HELPER 6 6 select DRM_KMS_DMA_HELPER 7 7 select DRM_GEM_DMA_HELPER 8 + select REGMAP 9 + select REGMAP_MMIO 8 10 help 9 11 DRM display driver for the logiCVC programmable logic block from Xylon