Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: pcs: xpcs: Add support for 25G, 50G, and 100G interfaces
With this change we are adding support for 25G, 50G, and 100G interface
types to the XPCS driver. This had supposedly been enabled with the
addition of XLGMII but I don't see any capability for configuration there
so I suspect it may need to be refactored in the future.
With this change we can enable the XPCS driver with the selected interface
and it should be able to detect link, speed, and report the link status to
the phylink interface.
Signed-off-by: Alexander Duyck <alexanderduyck@fb.com>
Link: https://patch.msgid.link/176374320248.959489.11649590675011158859.stgit@ahduyck-xeon-server.home.arpa
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
authored by
Alexander Duyck
and committed by
Paolo Abeni
7622d552
e6c43c95
+107
-4
+101
-4
drivers/net/pcs/pcs-xpcs.c
+101
-4
drivers/net/pcs/pcs-xpcs.c
···
37
37
__ETHTOOL_LINK_MODE_MASK_NBITS,
38
38
};
39
39
40
+
static const int xpcs_25gbaser_features[] = {
41
+
ETHTOOL_LINK_MODE_MII_BIT,
42
+
ETHTOOL_LINK_MODE_Pause_BIT,
43
+
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
44
+
ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
45
+
ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
46
+
ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
47
+
__ETHTOOL_LINK_MODE_MASK_NBITS,
48
+
};
49
+
40
50
static const int xpcs_xlgmii_features[] = {
41
51
ETHTOOL_LINK_MODE_Pause_BIT,
42
52
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
···
69
59
ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
70
60
ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
71
61
ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
62
+
ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
63
+
ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
64
+
ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
65
+
ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
66
+
ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
67
+
__ETHTOOL_LINK_MODE_MASK_NBITS,
68
+
};
69
+
70
+
static const int xpcs_50gbaser_features[] = {
71
+
ETHTOOL_LINK_MODE_MII_BIT,
72
+
ETHTOOL_LINK_MODE_Pause_BIT,
73
+
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
74
+
ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
75
+
ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
76
+
ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
77
+
ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
78
+
ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
79
+
__ETHTOOL_LINK_MODE_MASK_NBITS,
80
+
};
81
+
82
+
static const int xpcs_50gbaser2_features[] = {
83
+
ETHTOOL_LINK_MODE_MII_BIT,
84
+
ETHTOOL_LINK_MODE_Pause_BIT,
85
+
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
86
+
ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
87
+
ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
88
+
ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
89
+
__ETHTOOL_LINK_MODE_MASK_NBITS,
90
+
};
91
+
92
+
static const int xpcs_100gbasep_features[] = {
93
+
ETHTOOL_LINK_MODE_MII_BIT,
94
+
ETHTOOL_LINK_MODE_Pause_BIT,
95
+
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
72
96
ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
73
97
ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
74
98
ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
···
567
523
return speed;
568
524
}
569
525
570
-
static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
571
-
struct phylink_link_state *state)
526
+
static int xpcs_c45_read_pcs_speed(struct dw_xpcs *xpcs,
527
+
struct phylink_link_state *state)
572
528
{
529
+
int pcs_ctrl1;
530
+
531
+
pcs_ctrl1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL1);
532
+
if (pcs_ctrl1 < 0)
533
+
return pcs_ctrl1;
534
+
535
+
switch (pcs_ctrl1 & MDIO_CTRL1_SPEEDSEL) {
536
+
case MDIO_PCS_CTRL1_SPEED25G:
537
+
state->speed = SPEED_25000;
538
+
break;
539
+
case MDIO_PCS_CTRL1_SPEED50G:
540
+
state->speed = SPEED_50000;
541
+
break;
542
+
case MDIO_PCS_CTRL1_SPEED100G:
543
+
state->speed = SPEED_100000;
544
+
break;
545
+
default:
546
+
state->speed = SPEED_UNKNOWN;
547
+
break;
548
+
}
549
+
550
+
return 0;
551
+
}
552
+
553
+
static int xpcs_resolve_pma(struct dw_xpcs *xpcs,
554
+
struct phylink_link_state *state)
555
+
{
556
+
int err = 0;
557
+
573
558
state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
574
559
state->duplex = DUPLEX_FULL;
575
560
···
609
536
case PHY_INTERFACE_MODE_XLGMII:
610
537
state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
611
538
break;
539
+
case PHY_INTERFACE_MODE_100GBASEP:
540
+
case PHY_INTERFACE_MODE_LAUI:
541
+
case PHY_INTERFACE_MODE_50GBASER:
542
+
case PHY_INTERFACE_MODE_25GBASER:
543
+
err = xpcs_c45_read_pcs_speed(xpcs, state);
544
+
break;
612
545
default:
613
546
state->speed = SPEED_UNKNOWN;
614
547
break;
615
548
}
549
+
550
+
return err;
616
551
}
617
552
618
553
static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
···
1026
945
1027
946
phylink_resolve_c73(state);
1028
947
} else {
1029
-
xpcs_resolve_pma(xpcs, state);
948
+
ret = xpcs_resolve_pma(xpcs, state);
1030
949
}
1031
950
1032
-
return 0;
951
+
return ret;
1033
952
}
1034
953
1035
954
static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
···
1394
1313
.supported = xpcs_10gkr_features,
1395
1314
.an_mode = DW_AN_C73,
1396
1315
}, {
1316
+
.interface = PHY_INTERFACE_MODE_25GBASER,
1317
+
.supported = xpcs_25gbaser_features,
1318
+
.an_mode = DW_AN_C73,
1319
+
}, {
1397
1320
.interface = PHY_INTERFACE_MODE_XLGMII,
1398
1321
.supported = xpcs_xlgmii_features,
1322
+
.an_mode = DW_AN_C73,
1323
+
}, {
1324
+
.interface = PHY_INTERFACE_MODE_50GBASER,
1325
+
.supported = xpcs_50gbaser_features,
1326
+
.an_mode = DW_AN_C73,
1327
+
}, {
1328
+
.interface = PHY_INTERFACE_MODE_LAUI,
1329
+
.supported = xpcs_50gbaser2_features,
1330
+
.an_mode = DW_AN_C73,
1331
+
}, {
1332
+
.interface = PHY_INTERFACE_MODE_100GBASEP,
1333
+
.supported = xpcs_100gbasep_features,
1399
1334
.an_mode = DW_AN_C73,
1400
1335
}, {
1401
1336
.interface = PHY_INTERFACE_MODE_10GBASER,
+6
include/uapi/linux/mdio.h
+6
include/uapi/linux/mdio.h
···
123
123
*/
124
124
#define MDIO_CTRL1_SPEED2_5G MDIO_PMA_CTRL1_SPEED2_5G
125
125
#define MDIO_CTRL1_SPEED5G MDIO_PMA_CTRL1_SPEED5G
126
+
/* 100 Gb/s */
127
+
#define MDIO_PCS_CTRL1_SPEED100G (MDIO_CTRL1_SPEEDSELEXT | 0x10)
128
+
/* 25 Gb/s */
129
+
#define MDIO_PCS_CTRL1_SPEED25G (MDIO_CTRL1_SPEEDSELEXT | 0x14)
130
+
/* 50 Gb/s */
131
+
#define MDIO_PCS_CTRL1_SPEED50G (MDIO_CTRL1_SPEEDSELEXT | 0x18)
126
132
/* 2.5 Gb/s */
127
133
#define MDIO_PMA_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18)
128
134
/* 5 Gb/s */