Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties
These DRAM configuration properties are all handled in ARM Trusted
Firmware (and have been since the early days of this SoC), and there are
no in-tree users of the DMC binding yet. It's better to just defer to
firmware instead of maintaining this large list of properties.
There's also some confusion about units: many of these are specified in
MHz, but the downstream users and driver code are treating them as Hz, I
believe. Rather than straighten all that out, I just drop them.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
authored by
Brian Norris
and committed by
Chanwoo Choi
76d136b5
2142c27e
+21
-21
+21
-21
Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
+21
-21
Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
···
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finishes, a DCF interrupt is triggered.
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rockchip,ddr3_speed_bin:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
···
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if bus is idle for standby_idle * DFI clock cycles.
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rockchip,dram_dll_dis_freq:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
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Note: if DLL was bypassed, the odt will also stop working.
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rockchip,phy_dll_dis_freq:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
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Note: PHY DLL and PHY ODT are independent.
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rockchip,auto_pd_dis_freq:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines the auto PD disable frequency in MHz.
···
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disabled.
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rockchip,ddr3_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the DRAM side drive
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default: 40
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rockchip,ddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the DRAM side ODT
···
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default: 120
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rockchip,phy_ddr3_ca_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the phy side CA line
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default: 40
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rockchip,phy_ddr3_dq_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the PHY side DQ line
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default: 40
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rockchip,phy_ddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the PHY side ODT
···
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disabled.
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rockchip,lpddr3_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
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default: 34
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rockchip,lpddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
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default: 240
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rockchip,phy_lpddr3_ca_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
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default: 40
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rockchip,phy_lpddr3_dq_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
···
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default: 40
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rockchip,phy_lpddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When dram type is LPDDR3, this parameter define the phy side odt
···
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disabled.
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rockchip,lpddr4_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
···
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default: 60
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rockchip,lpddr4_dq_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
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default: 40
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rockchip,lpddr4_ca_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
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default: 40
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rockchip,phy_lpddr4_ca_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
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default: 40
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rockchip,phy_lpddr4_ck_cs_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side clock
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default: 80
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rockchip,phy_lpddr4_dq_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
···
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default: 80
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rockchip,phy_lpddr4_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
···
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clock-names = "dmc_clk";
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operating-points-v2 = <&dmc_opp_table>;
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center-supply = <&ppvar_centerlogic>;
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rockchip,ddr3_speed_bin = <21>;
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rockchip,pd_idle = <0x40>;
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rockchip,sr_idle = <0x2>;
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rockchip,sr_mc_gate_idle = <0x3>;
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rockchip,srpd_lite_idle = <0x4>;
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rockchip,standby_idle = <0x2000>;
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rockchip,dram_dll_dis_freq = <300>;
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rockchip,phy_dll_dis_freq = <125>;
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rockchip,auto_pd_dis_freq = <666>;
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rockchip,ddr3_odt_dis_freq = <333>;
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rockchip,ddr3_drv = <40>;
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rockchip,ddr3_odt = <120>;
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rockchip,phy_ddr3_ca_drv = <40>;
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rockchip,phy_ddr3_dq_drv = <40>;
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rockchip,phy_ddr3_odt = <240>;
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rockchip,lpddr3_odt_dis_freq = <333>;
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rockchip,lpddr3_drv = <34>;
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rockchip,lpddr3_odt = <240>;
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rockchip,phy_lpddr3_ca_drv = <40>;
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rockchip,phy_lpddr3_dq_drv = <40>;
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rockchip,phy_lpddr3_odt = <240>;
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rockchip,lpddr4_odt_dis_freq = <333>;
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rockchip,lpddr4_drv = <60>;
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rockchip,lpddr4_dq_odt = <40>;
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rockchip,lpddr4_ca_odt = <40>;
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rockchip,phy_lpddr4_ca_drv = <40>;
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rockchip,phy_lpddr4_ck_cs_drv = <80>;
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rockchip,phy_lpddr4_dq_drv = <80>;
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rockchip,phy_lpddr4_odt = <60>;
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};