Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-clk-for-v6.9

+1

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

··· 50 50 - renesas,r8a779a0-cpg-mssr # R-Car V3U 51 51 - renesas,r8a779f0-cpg-mssr # R-Car S4-8 52 52 - renesas,r8a779g0-cpg-mssr # R-Car V4H 53 + - renesas,r8a779h0-cpg-mssr # R-Car V4M 53 54 54 55 reg: 55 56 maxItems: 1

+1

Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml

··· 45 45 - renesas,r8a779a0-sysc # R-Car V3U 46 46 - renesas,r8a779f0-sysc # R-Car S4-8 47 47 - renesas,r8a779g0-sysc # R-Car V4H 48 + - renesas,r8a779h0-sysc # R-Car V4M 48 49 49 50 reg: 50 51 maxItems: 1

+96

include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2023 Renesas Electronics Corp. 4 + */ 5 + #ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ 6 + #define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ 7 + 8 + #include <dt-bindings/clock/renesas-cpg-mssr.h> 9 + 10 + /* r8a779h0 CPG Core Clocks */ 11 + 12 + #define R8A779H0_CLK_ZX 0 13 + #define R8A779H0_CLK_ZD 1 14 + #define R8A779H0_CLK_ZS 2 15 + #define R8A779H0_CLK_ZT 3 16 + #define R8A779H0_CLK_ZTR 4 17 + #define R8A779H0_CLK_S0D2 5 18 + #define R8A779H0_CLK_S0D3 6 19 + #define R8A779H0_CLK_S0D4 7 20 + #define R8A779H0_CLK_S0D1_VIO 8 21 + #define R8A779H0_CLK_S0D2_VIO 9 22 + #define R8A779H0_CLK_S0D4_VIO 10 23 + #define R8A779H0_CLK_S0D8_VIO 11 24 + #define R8A779H0_CLK_VIOBUSD1 12 25 + #define R8A779H0_CLK_VIOBUSD2 13 26 + #define R8A779H0_CLK_S0D1_VC 14 27 + #define R8A779H0_CLK_S0D2_VC 15 28 + #define R8A779H0_CLK_S0D4_VC 16 29 + #define R8A779H0_CLK_VCBUSD1 17 30 + #define R8A779H0_CLK_VCBUSD2 18 31 + #define R8A779H0_CLK_S0D2_MM 19 32 + #define R8A779H0_CLK_S0D4_MM 20 33 + #define R8A779H0_CLK_S0D2_U3DG 21 34 + #define R8A779H0_CLK_S0D4_U3DG 22 35 + #define R8A779H0_CLK_S0D2_RT 23 36 + #define R8A779H0_CLK_S0D3_RT 24 37 + #define R8A779H0_CLK_S0D4_RT 25 38 + #define R8A779H0_CLK_S0D6_RT 26 39 + #define R8A779H0_CLK_S0D2_PER 27 40 + #define R8A779H0_CLK_S0D3_PER 28 41 + #define R8A779H0_CLK_S0D4_PER 29 42 + #define R8A779H0_CLK_S0D6_PER 30 43 + #define R8A779H0_CLK_S0D12_PER 31 44 + #define R8A779H0_CLK_S0D24_PER 32 45 + #define R8A779H0_CLK_S0D1_HSC 33 46 + #define R8A779H0_CLK_S0D2_HSC 34 47 + #define R8A779H0_CLK_S0D4_HSC 35 48 + #define R8A779H0_CLK_S0D8_HSC 36 49 + #define R8A779H0_CLK_SVD1_IR 37 50 + #define R8A779H0_CLK_SVD2_IR 38 51 + #define R8A779H0_CLK_IMPAD1 39 52 + #define R8A779H0_CLK_IMPAD4 40 53 + #define R8A779H0_CLK_IMPB 41 54 + #define R8A779H0_CLK_SVD1_VIP 42 55 + #define R8A779H0_CLK_SVD2_VIP 43 56 + #define R8A779H0_CLK_CL 44 57 + #define R8A779H0_CLK_CL16M 45 58 + #define R8A779H0_CLK_CL16M_MM 46 59 + #define R8A779H0_CLK_CL16M_RT 47 60 + #define R8A779H0_CLK_CL16M_PER 48 61 + #define R8A779H0_CLK_CL16M_HSC 49 62 + #define R8A779H0_CLK_ZC0 50 63 + #define R8A779H0_CLK_ZC1 51 64 + #define R8A779H0_CLK_ZC2 52 65 + #define R8A779H0_CLK_ZC3 53 66 + #define R8A779H0_CLK_ZB3 54 67 + #define R8A779H0_CLK_ZB3D2 55 68 + #define R8A779H0_CLK_ZB3D4 56 69 + #define R8A779H0_CLK_ZG 57 70 + #define R8A779H0_CLK_SD0H 58 71 + #define R8A779H0_CLK_SD0 59 72 + #define R8A779H0_CLK_RPC 60 73 + #define R8A779H0_CLK_RPCD2 61 74 + #define R8A779H0_CLK_MSO 62 75 + #define R8A779H0_CLK_CANFD 63 76 + #define R8A779H0_CLK_CSI 64 77 + #define R8A779H0_CLK_FRAY 65 78 + #define R8A779H0_CLK_IPC 66 79 + #define R8A779H0_CLK_SASYNCRT 67 80 + #define R8A779H0_CLK_SASYNCPERD1 68 81 + #define R8A779H0_CLK_SASYNCPERD2 69 82 + #define R8A779H0_CLK_SASYNCPERD4 70 83 + #define R8A779H0_CLK_DSIEXT 71 84 + #define R8A779H0_CLK_DSIREF 72 85 + #define R8A779H0_CLK_ADGH 73 86 + #define R8A779H0_CLK_OSC 74 87 + #define R8A779H0_CLK_ZR0 75 88 + #define R8A779H0_CLK_ZR1 76 89 + #define R8A779H0_CLK_ZR2 77 90 + #define R8A779H0_CLK_RGMII 78 91 + #define R8A779H0_CLK_CPEX 79 92 + #define R8A779H0_CLK_CP 80 93 + #define R8A779H0_CLK_CBFUSA 81 94 + #define R8A779H0_CLK_R 82 95 + 96 + #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */

+49

include/dt-bindings/power/renesas,r8a779h0-sysc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2023 Renesas Electronics Corp. 4 + */ 5 + #ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ 6 + #define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ 7 + 8 + /* 9 + * These power domain indices match the Power Domain Register Numbers (PDR) 10 + */ 11 + 12 + #define R8A779H0_PD_A1E0D0C0 0 13 + #define R8A779H0_PD_A1E0D0C1 1 14 + #define R8A779H0_PD_A1E0D0C2 2 15 + #define R8A779H0_PD_A1E0D0C3 3 16 + #define R8A779H0_PD_A2E0D0 16 17 + #define R8A779H0_PD_A3CR0 21 18 + #define R8A779H0_PD_A3CR1 22 19 + #define R8A779H0_PD_A3CR2 23 20 + #define R8A779H0_PD_A33DGA 24 21 + #define R8A779H0_PD_A23DGB 25 22 + #define R8A779H0_PD_C4 31 23 + #define R8A779H0_PD_A1DSP0 33 24 + #define R8A779H0_PD_A2IMP01 34 25 + #define R8A779H0_PD_A2PSC 35 26 + #define R8A779H0_PD_A2CV0 36 27 + #define R8A779H0_PD_A2CV1 37 28 + #define R8A779H0_PD_A3IMR0 38 29 + #define R8A779H0_PD_A3IMR1 39 30 + #define R8A779H0_PD_A3VC 40 31 + #define R8A779H0_PD_A2CN0 42 32 + #define R8A779H0_PD_A1CN0 44 33 + #define R8A779H0_PD_A1DSP1 45 34 + #define R8A779H0_PD_A2DMA 47 35 + #define R8A779H0_PD_A2CV2 48 36 + #define R8A779H0_PD_A2CV3 49 37 + #define R8A779H0_PD_A3IMR2 50 38 + #define R8A779H0_PD_A3IMR3 51 39 + #define R8A779H0_PD_A3PCI 52 40 + #define R8A779H0_PD_A2PCIPHY 53 41 + #define R8A779H0_PD_A3VIP0 56 42 + #define R8A779H0_PD_A3VIP2 58 43 + #define R8A779H0_PD_A3ISP0 60 44 + #define R8A779H0_PD_A3DUL 62 45 + 46 + /* Always-on power area */ 47 + #define R8A779H0_PD_ALWAYS_ON 64 48 + 49 + #endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */

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