clk: renesas: r9a07g043: Add clock and reset entries for CRU

Add CRU clock and reset entries to CPG driver.

CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g043_no_pm_mod_clks[] array and pass it as part of CPG data for
RZ/G2UL SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240123114415.290918-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by

Geert Uytterhoeven 2 years ago 78ed2529 292d3079

+31

1 changed file

expand all

drivers

clk

renesas

r9a07g043-cpg.c

+31

drivers/clk/renesas/r9a07g043-cpg.c

··· 48 48 CLK_SEL_PLL3_3, 49 49 CLK_DIV_PLL3_C, 50 50 #ifdef CONFIG_ARM64 51 + CLK_M2_DIV2, 51 52 CLK_PLL5, 52 53 CLK_PLL5_500, 53 54 CLK_PLL5_250, ··· 143 142 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 144 143 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), 145 144 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), 145 + #ifdef CONFIG_ARM64 146 + DEF_FIXED("M2", R9A07G043_CLK_M2, CLK_PLL3_533, 1, 2), 147 + DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G043_CLK_M2, 1, 2), 148 + #endif 146 149 }; 147 150 148 151 static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { ··· 200 195 0x554, 6), 201 196 DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 202 197 0x554, 7), 198 + #ifdef CONFIG_ARM64 199 + DEF_MOD("cru_sysclk", R9A07G043_CRU_SYSCLK, CLK_M2_DIV2, 200 + 0x564, 0), 201 + DEF_MOD("cru_vclk", R9A07G043_CRU_VCLK, R9A07G043_CLK_M2, 202 + 0x564, 1), 203 + DEF_MOD("cru_pclk", R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT, 204 + 0x564, 2), 205 + DEF_MOD("cru_aclk", R9A07G043_CRU_ACLK, R9A07G043_CLK_M0, 206 + 0x564, 3), 207 + #endif 203 208 DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, 204 209 0x570, 0), 205 210 DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, ··· 301 286 DEF_RST(R9A07G043_SPI_RST, 0x850, 0), 302 287 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 303 288 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 289 + #ifdef CONFIG_ARM64 290 + DEF_RST(R9A07G043_CRU_CMN_RSTB, 0x864, 0), 291 + DEF_RST(R9A07G043_CRU_PRESETN, 0x864, 1), 292 + DEF_RST(R9A07G043_CRU_ARESETN, 0x864, 2), 293 + #endif 304 294 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), 305 295 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), 306 296 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), ··· 351 331 MOD_CLK_BASE + R9A07G043_DMAC_ACLK, 352 332 }; 353 333 334 + #ifdef CONFIG_ARM64 335 + static const unsigned int r9a07g043_no_pm_mod_clks[] = { 336 + MOD_CLK_BASE + R9A07G043_CRU_SYSCLK, 337 + MOD_CLK_BASE + R9A07G043_CRU_VCLK, 338 + }; 339 + #endif 340 + 354 341 const struct rzg2l_cpg_info r9a07g043_cpg_info = { 355 342 /* Core Clocks */ 356 343 .core_clks = r9a07g043_core_clks, ··· 374 347 .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), 375 348 #ifdef CONFIG_ARM64 376 349 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, 350 + 351 + /* No PM Module Clocks */ 352 + .no_pm_mod_clks = r9a07g043_no_pm_mod_clks, 353 + .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g043_no_pm_mod_clks), 377 354 #endif 378 355 #ifdef CONFIG_RISCV 379 356 .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,

Configure Feed

Configure Feed