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dt-bindings: devfreq: rk3399_dmc: Specify idle params in nanoseconds

It's inefficient to use the same number of cycles for all OPPs, since
lower frequencies make for longer idle times. Let's specify the idle
time instead, so software can pick the optimal number of cycles on its
own.

NB: these bindings aren't used anywhere yet.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

authored by

Brian Norris and committed by
Chanwoo Choi
77c18808 4de8fd02

+46 -5
+46 -5
Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
··· 54 54 being used. 55 55 56 56 rockchip,pd_idle: 57 + deprecated: true 57 58 $ref: /schemas/types.yaml#/definitions/uint32 58 59 description: 59 60 Configure the PD_IDLE value. Defines the power-down idle period in which 60 61 memories are placed into power-down mode if bus is idle for PD_IDLE DFI 61 62 clock cycles. 63 + See also rockchip,pd-idle-ns. 62 64 63 65 rockchip,sr_idle: 66 + deprecated: true 64 67 $ref: /schemas/types.yaml#/definitions/uint32 65 68 description: 66 69 Configure the SR_IDLE value. Defines the self-refresh idle period in 67 70 which memories are placed into self-refresh mode if bus is idle for 68 71 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock). 72 + See also rockchip,sr-idle-ns. 69 73 default: 0 70 74 71 75 rockchip,sr_mc_gate_idle: 76 + deprecated: true 72 77 $ref: /schemas/types.yaml#/definitions/uint32 73 78 description: 74 79 Defines the memory self-refresh and controller clock gating idle period. 75 80 Memories are placed into self-refresh mode and memory controller clock 76 81 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock 77 82 cycles. 83 + See also rockchip,sr-mc-gate-idle-ns. 78 84 79 85 rockchip,srpd_lite_idle: 86 + deprecated: true 80 87 $ref: /schemas/types.yaml#/definitions/uint32 81 88 description: 82 89 Defines the self-refresh power down idle period in which memories are 83 90 placed into self-refresh power down mode if bus is idle for 84 91 srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4 85 92 only. 93 + See also rockchip,srpd-lite-idle-ns. 86 94 87 95 rockchip,standby_idle: 96 + deprecated: true 88 97 $ref: /schemas/types.yaml#/definitions/uint32 89 98 description: 90 99 Defines the standby idle period in which memories are placed into 91 100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated 92 101 if bus is idle for standby_idle * DFI clock cycles. 102 + See also rockchip,standby-idle-ns. 93 103 94 104 rockchip,dram_dll_dis_freq: 95 105 deprecated: true ··· 282 272 strength. 283 273 default: 60 284 274 275 + rockchip,pd-idle-ns: 276 + description: 277 + Configure the PD_IDLE value in nanoseconds. Defines the power-down idle 278 + period in which memories are placed into power-down mode if bus is idle 279 + for PD_IDLE nanoseconds. 280 + 281 + rockchip,sr-idle-ns: 282 + description: 283 + Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle 284 + period in which memories are placed into self-refresh mode if bus is idle 285 + for SR_IDLE nanoseconds. 286 + default: 0 287 + 288 + rockchip,sr-mc-gate-idle-ns: 289 + description: 290 + Defines the memory self-refresh and controller clock gating idle period in nanoseconds. 291 + Memories are placed into self-refresh mode and memory controller clock 292 + arg gating started if bus is idle for sr_mc_gate_idle nanoseconds. 293 + 294 + rockchip,srpd-lite-idle-ns: 295 + description: 296 + Defines the self-refresh power down idle period in which memories are 297 + placed into self-refresh power down mode if bus is idle for 298 + srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only. 299 + 300 + rockchip,standby-idle-ns: 301 + description: 302 + Defines the standby idle period in which memories are placed into 303 + self-refresh mode. The controller, pi, PHY and DRAM clock will be gated 304 + if bus is idle for standby_idle nanoseconds. 305 + 285 306 required: 286 307 - compatible 287 308 - devfreq-events ··· 336 295 clock-names = "dmc_clk"; 337 296 operating-points-v2 = <&dmc_opp_table>; 338 297 center-supply = <&ppvar_centerlogic>; 339 - rockchip,pd_idle = <0x40>; 340 - rockchip,sr_idle = <0x2>; 341 - rockchip,sr_mc_gate_idle = <0x3>; 342 - rockchip,srpd_lite_idle = <0x4>; 343 - rockchip,standby_idle = <0x2000>; 298 + rockchip,pd-idle-ns = <160>; 299 + rockchip,sr-idle-ns = <10240>; 300 + rockchip,sr-mc-gate-idle-ns = <40960>; 301 + rockchip,srpd-lite-idle-ns = <61440>; 302 + rockchip,standby-idle-ns = <81920>; 344 303 rockchip,ddr3_odt_dis_freq = <333000000>; 345 304 rockchip,lpddr3_odt_dis_freq = <333000000>; 346 305 rockchip,lpddr4_odt_dis_freq = <333000000>;