drm/msm/dp: stop parsing clock names from DT

+58 -17

drivers/gpu/drm/msm/dp/dp_ctrl.c

··· 69 69 u8 tu_size_minus1; 70 70 }; 71 71 72 + struct dss_module_power { 73 + unsigned int num_clk; 74 + struct clk_bulk_data *clocks; 75 + }; 76 + 72 77 struct dp_ctrl_private { 73 78 struct dp_ctrl dp_ctrl; 74 79 struct drm_device *drm_dev; ··· 84 79 struct dp_parser *parser; 85 80 struct dp_catalog *catalog; 86 81 82 + struct dss_module_power mp[DP_MAX_PM]; 87 83 struct clk *pixel_clk; 88 84 89 85 struct completion idle_comp; ··· 95 89 bool link_clks_on; 96 90 bool stream_clks_on; 97 91 }; 92 + 93 + static inline const char *dp_pm_name(enum dp_pm_type module) 94 + { 95 + switch (module) { 96 + case DP_CORE_PM: return "DP_CORE_PM"; 97 + case DP_CTRL_PM: return "DP_CTRL_PM"; 98 + default: return "???"; 99 + } 100 + } 98 101 99 102 static int dp_aux_link_configure(struct drm_dp_aux *aux, 100 103 struct dp_link_info *link) ··· 1344 1329 if (pm_type != DP_CORE_PM && 1345 1330 pm_type != DP_CTRL_PM) { 1346 1331 DRM_ERROR("unsupported ctrl module: %s\n", 1347 - dp_parser_pm_name(pm_type)); 1332 + dp_pm_name(pm_type)); 1348 1333 return -EINVAL; 1349 1334 } 1350 1335 ··· 1364 1349 if ((pm_type == DP_CTRL_PM) && (!ctrl->core_clks_on)) { 1365 1350 drm_dbg_dp(ctrl->drm_dev, 1366 1351 "Enable core clks before link clks\n"); 1367 - mp = &ctrl->parser->mp[DP_CORE_PM]; 1352 + mp = &ctrl->mp[DP_CORE_PM]; 1368 1353 1369 1354 ret = clk_bulk_prepare_enable(mp->num_clk, mp->clocks); 1370 1355 if (ret) ··· 1374 1359 } 1375 1360 } 1376 1361 1377 - mp = &ctrl->parser->mp[pm_type]; 1362 + mp = &ctrl->mp[pm_type]; 1378 1363 if (enable) { 1379 1364 ret = clk_bulk_prepare_enable(mp->num_clk, mp->clocks); 1380 1365 if (ret) ··· 1390 1375 1391 1376 drm_dbg_dp(ctrl->drm_dev, "%s clocks for %s\n", 1392 1377 enable ? "enable" : "disable", 1393 - dp_parser_pm_name(pm_type)); 1378 + dp_pm_name(pm_type)); 1394 1379 drm_dbg_dp(ctrl->drm_dev, 1395 1380 "stream_clks:%s link_clks:%s core_clks:%s\n", 1396 1381 ctrl->stream_clks_on ? "on" : "off", ··· 2168 2153 return ret; 2169 2154 } 2170 2155 2156 + static const char *core_clks[] = { 2157 + "core_iface", 2158 + "core_aux", 2159 + }; 2160 + 2161 + static const char *ctrl_clks[] = { 2162 + "ctrl_link", 2163 + "ctrl_link_iface", 2164 + }; 2165 + 2171 2166 static int dp_ctrl_clk_init(struct dp_ctrl *dp_ctrl) 2172 2167 { 2173 - struct dp_ctrl_private *ctrl_private; 2174 - int rc = 0; 2175 - struct dss_module_power *core, *ctrl; 2168 + struct dp_ctrl_private *ctrl; 2169 + struct dss_module_power *core, *link; 2176 2170 struct device *dev; 2171 + int i, rc; 2177 2172 2178 - ctrl_private = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2179 - dev = ctrl_private->dev; 2173 + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2174 + dev = ctrl->dev; 2180 2175 2181 - core = &ctrl_private->parser->mp[DP_CORE_PM]; 2182 - ctrl = &ctrl_private->parser->mp[DP_CTRL_PM]; 2176 + core = &ctrl->mp[DP_CORE_PM]; 2177 + link = &ctrl->mp[DP_CTRL_PM]; 2178 + 2179 + core->num_clk = ARRAY_SIZE(core_clks); 2180 + core->clocks = devm_kcalloc(dev, core->num_clk, sizeof(*core->clocks), GFP_KERNEL); 2181 + if (!core->clocks) 2182 + return -ENOMEM; 2183 + 2184 + for (i = 0; i < core->num_clk; i++) 2185 + core->clocks[i].id = core_clks[i]; 2183 2186 2184 2187 rc = devm_clk_bulk_get(dev, core->num_clk, core->clocks); 2185 2188 if (rc) 2186 2189 return rc; 2187 2190 2188 - rc = devm_clk_bulk_get(dev, ctrl->num_clk, ctrl->clocks); 2189 - if (rc) 2190 - return -ENODEV; 2191 + link->num_clk = ARRAY_SIZE(ctrl_clks); 2192 + link->clocks = devm_kcalloc(dev, link->num_clk, sizeof(*link->clocks), GFP_KERNEL); 2193 + if (!link->clocks) 2194 + return -ENOMEM; 2191 2195 2192 - ctrl_private->pixel_clk = devm_clk_get(dev, "stream_pixel"); 2193 - if (IS_ERR(ctrl_private->pixel_clk)) 2194 - return PTR_ERR(ctrl_private->pixel_clk); 2196 + for (i = 0; i < link->num_clk; i++) 2197 + link->clocks[i].id = ctrl_clks[i]; 2198 + 2199 + rc = devm_clk_bulk_get(dev, link->num_clk, link->clocks); 2200 + if (rc) 2201 + return rc; 2202 + 2203 + ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); 2204 + if (IS_ERR(ctrl->pixel_clk)) 2205 + return PTR_ERR(ctrl->pixel_clk); 2195 2206 2196 2207 return 0; 2197 2208 }

+6

drivers/gpu/drm/msm/dp/dp_ctrl.h

··· 17 17 bool wide_bus_en; 18 18 }; 19 19 20 + enum dp_pm_type { 21 + DP_CORE_PM, 22 + DP_CTRL_PM, 23 + DP_MAX_PM 24 + }; 25 + 20 26 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl); 21 27 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train); 22 28 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);

-112

drivers/gpu/drm/msm/dp/dp_parser.c

··· 141 141 return 0; 142 142 } 143 143 144 - static inline bool dp_parser_check_prefix(const char *clk_prefix, 145 - const char *clk_name) 146 - { 147 - return !strncmp(clk_prefix, clk_name, strlen(clk_prefix)); 148 - } 149 - 150 - static int dp_parser_init_clk_data(struct dp_parser *parser) 151 - { 152 - int num_clk, i, rc; 153 - int core_clk_count = 0, ctrl_clk_count = 0; 154 - const char *clk_name; 155 - struct device *dev = &parser->pdev->dev; 156 - struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; 157 - struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; 158 - 159 - num_clk = of_property_count_strings(dev->of_node, "clock-names"); 160 - if (num_clk <= 0) { 161 - DRM_ERROR("no clocks are defined\n"); 162 - return -EINVAL; 163 - } 164 - 165 - for (i = 0; i < num_clk; i++) { 166 - rc = of_property_read_string_index(dev->of_node, 167 - "clock-names", i, &clk_name); 168 - if (rc < 0) 169 - return rc; 170 - 171 - if (dp_parser_check_prefix("core", clk_name)) 172 - core_clk_count++; 173 - 174 - if (dp_parser_check_prefix("ctrl", clk_name)) 175 - ctrl_clk_count++; 176 - } 177 - 178 - /* Initialize the CORE power module */ 179 - if (core_clk_count == 0) { 180 - DRM_ERROR("no core clocks are defined\n"); 181 - return -EINVAL; 182 - } 183 - 184 - core_power->num_clk = core_clk_count; 185 - core_power->clocks = devm_kcalloc(dev, 186 - core_power->num_clk, sizeof(struct clk_bulk_data), 187 - GFP_KERNEL); 188 - if (!core_power->clocks) 189 - return -ENOMEM; 190 - 191 - /* Initialize the CTRL power module */ 192 - if (ctrl_clk_count == 0) { 193 - DRM_ERROR("no ctrl clocks are defined\n"); 194 - return -EINVAL; 195 - } 196 - 197 - ctrl_power->num_clk = ctrl_clk_count; 198 - ctrl_power->clocks = devm_kcalloc(dev, 199 - ctrl_power->num_clk, sizeof(struct clk_bulk_data), 200 - GFP_KERNEL); 201 - if (!ctrl_power->clocks) { 202 - ctrl_power->num_clk = 0; 203 - return -ENOMEM; 204 - } 205 - 206 - return num_clk; 207 - } 208 - 209 - static int dp_parser_clock(struct dp_parser *parser) 210 - { 211 - int rc = 0, i = 0; 212 - int num_clk = 0; 213 - int core_clk_index = 0, ctrl_clk_index = 0; 214 - int core_clk_count = 0, ctrl_clk_count = 0; 215 - const char *clk_name; 216 - struct device *dev = &parser->pdev->dev; 217 - struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; 218 - struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; 219 - 220 - rc = dp_parser_init_clk_data(parser); 221 - if (rc < 0) { 222 - DRM_ERROR("failed to initialize power data %d\n", rc); 223 - return rc; 224 - } 225 - 226 - num_clk = rc; 227 - 228 - core_clk_count = core_power->num_clk; 229 - ctrl_clk_count = ctrl_power->num_clk; 230 - 231 - for (i = 0; i < num_clk; i++) { 232 - rc = of_property_read_string_index(dev->of_node, "clock-names", 233 - i, &clk_name); 234 - if (rc) { 235 - DRM_ERROR("error reading clock-names %d\n", rc); 236 - return rc; 237 - } 238 - if (dp_parser_check_prefix("core", clk_name) && 239 - core_clk_index < core_clk_count) { 240 - core_power->clocks[core_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); 241 - core_clk_index++; 242 - } else if (dp_parser_check_prefix("ctrl", clk_name) && 243 - ctrl_clk_index < ctrl_clk_count) { 244 - ctrl_power->clocks[ctrl_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); 245 - ctrl_clk_index++; 246 - } 247 - } 248 - 249 - return 0; 250 - } 251 - 252 144 int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser) 253 145 { 254 146 struct platform_device *pdev = parser->pdev; ··· 169 277 return rc; 170 278 171 279 rc = dp_parser_misc(parser); 172 - if (rc) 173 - return rc; 174 - 175 - rc = dp_parser_clock(parser); 176 280 if (rc) 177 281 return rc; 178 282

-22

drivers/gpu/drm/msm/dp/dp_parser.h

··· 16 16 #define DP_MAX_NUM_DP_LANES 4 17 17 #define DP_LINK_RATE_HBR2 540000 /* kbytes */ 18 18 19 - enum dp_pm_type { 20 - DP_CORE_PM, 21 - DP_CTRL_PM, 22 - DP_MAX_PM 23 - }; 24 - 25 19 struct dss_io_region { 26 20 size_t len; 27 21 void __iomem *base; ··· 27 33 struct dss_io_region link; 28 34 struct dss_io_region p0; 29 35 }; 30 - 31 - static inline const char *dp_parser_pm_name(enum dp_pm_type module) 32 - { 33 - switch (module) { 34 - case DP_CORE_PM: return "DP_CORE_PM"; 35 - case DP_CTRL_PM: return "DP_CTRL_PM"; 36 - default: return "???"; 37 - } 38 - } 39 36 40 37 /** 41 38 * struct dp_ctrl_resource - controller's IO related data ··· 40 55 union phy_configure_opts phy_opts; 41 56 }; 42 57 43 - struct dss_module_power { 44 - unsigned int num_clk; 45 - struct clk_bulk_data *clocks; 46 - }; 47 - 48 58 /** 49 59 * struct dp_parser - DP parser's data exposed to clients 50 60 * 51 61 * @pdev: platform data of the client 52 - * @mp: gpio, regulator and clock related data 53 62 */ 54 63 struct dp_parser { 55 64 struct platform_device *pdev; 56 - struct dss_module_power mp[DP_MAX_PM]; 57 65 struct dp_io io; 58 66 u32 max_dp_lanes; 59 67 u32 max_dp_link_rate;

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