tjh.dev / kernel
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drm/msm/dp: simplify stream clocks handling

There is only a single DP_STREAM_PM clock, stream_pixel. Instead of
using a separate dss_module_power instance for this single clock, handle
this clock directly. This allows us to drop several wrapping functions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576102/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-6-098d5f581dd3@linaro.org

Dmitry Baryshkov 9bd0946d 17cb153f

+47 -87
+39 -52
drivers/gpu/drm/msm/dp/dp_ctrl.c
··· 79 79 struct dp_parser *parser; 80 80 struct dp_catalog *catalog; 81 81 82 + struct clk *pixel_clk; 83 + 82 84 struct completion idle_comp; 83 85 struct completion psr_op_comp; 84 86 struct completion video_comp; ··· 1317 1315 return ret; 1318 1316 } 1319 1317 1320 - static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, 1321 - enum dp_pm_type module, char *name, unsigned long rate) 1322 - { 1323 - u32 num = ctrl->parser->mp[module].num_clk; 1324 - struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks; 1325 - 1326 - while (num && strcmp(cfg->id, name)) { 1327 - num--; 1328 - cfg++; 1329 - } 1330 - 1331 - drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n", 1332 - rate, name); 1333 - 1334 - if (num) 1335 - clk_set_rate(cfg->clk, rate); 1336 - else 1337 - DRM_ERROR("%s clock doesn't exit to set rate %lu\n", 1338 - name, rate); 1339 - } 1340 - 1341 1318 int dp_ctrl_clk_enable(struct dp_ctrl *dp_ctrl, 1342 1319 enum dp_pm_type pm_type, bool enable) 1343 1320 { ··· 1327 1346 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1328 1347 1329 1348 if (pm_type != DP_CORE_PM && 1330 - pm_type != DP_CTRL_PM && 1331 - pm_type != DP_STREAM_PM) { 1349 + pm_type != DP_CTRL_PM) { 1332 1350 DRM_ERROR("unsupported ctrl module: %s\n", 1333 1351 dp_parser_pm_name(pm_type)); 1334 1352 return -EINVAL; ··· 1343 1363 if (pm_type == DP_CTRL_PM && ctrl->link_clks_on) { 1344 1364 drm_dbg_dp(ctrl->drm_dev, 1345 1365 "links clks already enabled\n"); 1346 - return 0; 1347 - } 1348 - 1349 - if (pm_type == DP_STREAM_PM && ctrl->stream_clks_on) { 1350 - drm_dbg_dp(ctrl->drm_dev, 1351 - "pixel clks already enabled\n"); 1352 1366 return 0; 1353 1367 } 1354 1368 ··· 1370 1396 1371 1397 if (pm_type == DP_CORE_PM) 1372 1398 ctrl->core_clks_on = enable; 1373 - else if (pm_type == DP_STREAM_PM) 1374 - ctrl->stream_clks_on = enable; 1375 1399 else 1376 1400 ctrl->link_clks_on = enable; 1377 1401 ··· 1701 1729 } 1702 1730 1703 1731 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1704 - dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000); 1705 - 1706 - ret = dp_ctrl_clk_enable(&ctrl->dp_ctrl, DP_STREAM_PM, true); 1732 + ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); 1707 1733 if (ret) { 1708 - DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1734 + DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 1709 1735 return ret; 1736 + } 1737 + 1738 + if (ctrl->stream_clks_on) { 1739 + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); 1740 + } else { 1741 + ret = clk_prepare_enable(ctrl->pixel_clk); 1742 + if (ret) { 1743 + DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1744 + return ret; 1745 + } 1746 + ctrl->stream_clks_on = true; 1710 1747 } 1711 1748 1712 1749 dp_ctrl_send_phy_test_pattern(ctrl); ··· 1953 1972 } 1954 1973 } 1955 1974 1956 - dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000); 1957 - 1958 - ret = dp_ctrl_clk_enable(&ctrl->dp_ctrl, DP_STREAM_PM, true); 1975 + ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); 1959 1976 if (ret) { 1960 - DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret); 1977 + DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 1961 1978 goto end; 1979 + } 1980 + 1981 + if (ctrl->stream_clks_on) { 1982 + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); 1983 + } else { 1984 + ret = clk_prepare_enable(ctrl->pixel_clk); 1985 + if (ret) { 1986 + DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1987 + goto end; 1988 + } 1989 + ctrl->stream_clks_on = true; 1962 1990 } 1963 1991 1964 1992 if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl)) ··· 2021 2031 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2022 2032 2023 2033 if (ctrl->stream_clks_on) { 2024 - ret = dp_ctrl_clk_enable(&ctrl->dp_ctrl, DP_STREAM_PM, false); 2025 - if (ret) { 2026 - DRM_ERROR("Failed to disable pclk. ret=%d\n", ret); 2027 - return ret; 2028 - } 2034 + clk_disable_unprepare(ctrl->pixel_clk); 2035 + ctrl->stream_clks_on = false; 2029 2036 } 2030 2037 2031 2038 dev_pm_opp_set_rate(ctrl->dev, 0); ··· 2090 2103 2091 2104 dp_catalog_ctrl_reset(ctrl->catalog); 2092 2105 2093 - ret = dp_ctrl_clk_enable(&ctrl->dp_ctrl, DP_STREAM_PM, false); 2094 - if (ret) 2095 - DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); 2106 + if (ctrl->stream_clks_on) { 2107 + clk_disable_unprepare(ctrl->pixel_clk); 2108 + ctrl->stream_clks_on = false; 2109 + } 2096 2110 2097 2111 dev_pm_opp_set_rate(ctrl->dev, 0); 2098 2112 ret = dp_ctrl_clk_enable(&ctrl->dp_ctrl, DP_CTRL_PM, false); ··· 2157 2169 { 2158 2170 struct dp_ctrl_private *ctrl_private; 2159 2171 int rc = 0; 2160 - struct dss_module_power *core, *ctrl, *stream; 2172 + struct dss_module_power *core, *ctrl; 2161 2173 struct device *dev; 2162 2174 2163 2175 ctrl_private = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); ··· 2165 2177 2166 2178 core = &ctrl_private->parser->mp[DP_CORE_PM]; 2167 2179 ctrl = &ctrl_private->parser->mp[DP_CTRL_PM]; 2168 - stream = &ctrl_private->parser->mp[DP_STREAM_PM]; 2169 2180 2170 2181 rc = devm_clk_bulk_get(dev, core->num_clk, core->clocks); 2171 2182 if (rc) ··· 2174 2187 if (rc) 2175 2188 return -ENODEV; 2176 2189 2177 - rc = devm_clk_bulk_get(dev, stream->num_clk, stream->clocks); 2178 - if (rc) 2179 - return -ENODEV; 2190 + ctrl_private->pixel_clk = devm_clk_get(dev, "stream_pixel"); 2191 + if (IS_ERR(ctrl_private->pixel_clk)) 2192 + return PTR_ERR(ctrl_private->pixel_clk); 2180 2193 2181 2194 return 0; 2182 2195 }
+8 -33
drivers/gpu/drm/msm/dp/dp_parser.c
··· 150 150 static int dp_parser_init_clk_data(struct dp_parser *parser) 151 151 { 152 152 int num_clk, i, rc; 153 - int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0; 153 + int core_clk_count = 0, ctrl_clk_count = 0; 154 154 const char *clk_name; 155 155 struct device *dev = &parser->pdev->dev; 156 156 struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; 157 157 struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; 158 - struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM]; 159 158 160 159 num_clk = of_property_count_strings(dev->of_node, "clock-names"); 161 160 if (num_clk <= 0) { ··· 173 174 174 175 if (dp_parser_check_prefix("ctrl", clk_name)) 175 176 ctrl_clk_count++; 176 - 177 - if (dp_parser_check_prefix("stream", clk_name)) 178 - stream_clk_count++; 179 177 } 180 178 181 179 /* Initialize the CORE power module */ ··· 203 207 return -ENOMEM; 204 208 } 205 209 206 - /* Initialize the STREAM power module */ 207 - if (stream_clk_count == 0) { 208 - DRM_ERROR("no stream (pixel) clocks are defined\n"); 209 - return -EINVAL; 210 - } 211 - 212 - stream_power->num_clk = stream_clk_count; 213 - stream_power->clocks = devm_kcalloc(dev, 214 - stream_power->num_clk, sizeof(struct clk_bulk_data), 215 - GFP_KERNEL); 216 - if (!stream_power->clocks) { 217 - stream_power->num_clk = 0; 218 - return -ENOMEM; 219 - } 220 - 221 - return 0; 210 + return num_clk; 222 211 } 223 212 224 213 static int dp_parser_clock(struct dp_parser *parser) 225 214 { 226 215 int rc = 0, i = 0; 227 216 int num_clk = 0; 228 - int core_clk_index = 0, ctrl_clk_index = 0, stream_clk_index = 0; 229 - int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0; 217 + int core_clk_index = 0, ctrl_clk_index = 0; 218 + int core_clk_count = 0, ctrl_clk_count = 0; 230 219 const char *clk_name; 231 220 struct device *dev = &parser->pdev->dev; 232 221 struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; 233 222 struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; 234 - struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM]; 235 223 236 224 rc = dp_parser_init_clk_data(parser); 237 - if (rc) { 225 + if (rc < 0) { 238 226 DRM_ERROR("failed to initialize power data %d\n", rc); 239 - return -EINVAL; 227 + return rc; 240 228 } 229 + 230 + num_clk = rc; 241 231 242 232 core_clk_count = core_power->num_clk; 243 233 ctrl_clk_count = ctrl_power->num_clk; 244 - stream_clk_count = stream_power->num_clk; 245 - 246 - num_clk = core_clk_count + ctrl_clk_count + stream_clk_count; 247 234 248 235 for (i = 0; i < num_clk; i++) { 249 236 rc = of_property_read_string_index(dev->of_node, "clock-names", ··· 239 260 core_clk_index < core_clk_count) { 240 261 core_power->clocks[core_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); 241 262 core_clk_index++; 242 - } else if (dp_parser_check_prefix("stream", clk_name) && 243 - stream_clk_index < stream_clk_count) { 244 - stream_power->clocks[stream_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); 245 - stream_clk_index++; 246 263 } else if (dp_parser_check_prefix("ctrl", clk_name) && 247 264 ctrl_clk_index < ctrl_clk_count) { 248 265 ctrl_power->clocks[ctrl_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL);
-2
drivers/gpu/drm/msm/dp/dp_parser.h
··· 19 19 enum dp_pm_type { 20 20 DP_CORE_PM, 21 21 DP_CTRL_PM, 22 - DP_STREAM_PM, 23 22 DP_MAX_PM 24 23 }; 25 24 ··· 39 40 switch (module) { 40 41 case DP_CORE_PM: return "DP_CORE_PM"; 41 42 case DP_CTRL_PM: return "DP_CTRL_PM"; 42 - case DP_STREAM_PM: return "DP_STREAM_PM"; 43 43 default: return "???"; 44 44 } 45 45 }