Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events: Add westmereex counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-38-irogers@google.com
authored by
Ian Rogers
Weilin Wang
Caleb Biggers
and committed by
Namhyung Kim
788c5160
dc5f18a1
+586
+320
tools/perf/pmu-events/arch/x86/westmereex/cache.json
+320
tools/perf/pmu-events/arch/x86/westmereex/cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles L1D locked",
4
+
"Counter": "0,1",
4
5
"EventCode": "0x63",
5
6
"EventName": "CACHE_LOCK_CYCLES.L1D",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Cycles L1D and L2 locked",
11
+
"Counter": "0,1",
12
12
"EventCode": "0x63",
13
13
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1D cache lines replaced in M state",
18
+
"Counter": "0,1",
20
19
"EventCode": "0x51",
21
20
"EventName": "L1D.M_EVICT",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1D cache lines allocated in the M state",
25
+
"Counter": "0,1",
28
26
"EventCode": "0x51",
29
27
"EventName": "L1D.M_REPL",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1D snoop eviction of cache lines in M state",
32
+
"Counter": "0,1",
36
33
"EventCode": "0x51",
37
34
"EventName": "L1D.M_SNOOP_EVICT",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1 data cache lines allocated",
39
+
"Counter": "0,1",
44
40
"EventCode": "0x51",
45
41
"EventName": "L1D.REPL",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
46
+
"Counter": "0,1",
52
47
"EventCode": "0x52",
53
48
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
54
49
"SampleAfterValue": "2000000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "L1D hardware prefetch misses",
53
+
"Counter": "0,1",
60
54
"EventCode": "0x4E",
61
55
"EventName": "L1D_PREFETCH.MISS",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "L1D hardware prefetch requests",
60
+
"Counter": "0,1",
68
61
"EventCode": "0x4E",
69
62
"EventName": "L1D_PREFETCH.REQUESTS",
70
63
"SampleAfterValue": "200000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "L1D hardware prefetch requests triggered",
67
+
"Counter": "0,1",
76
68
"EventCode": "0x4E",
77
69
"EventName": "L1D_PREFETCH.TRIGGERS",
78
70
"SampleAfterValue": "200000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "L1 writebacks to L2 in E state",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x28",
85
76
"EventName": "L1D_WB_L2.E_STATE",
86
77
"SampleAfterValue": "100000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x28",
93
83
"EventName": "L1D_WB_L2.I_STATE",
94
84
"SampleAfterValue": "100000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "All L1 writebacks to L2",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x28",
101
90
"EventName": "L1D_WB_L2.MESI",
102
91
"SampleAfterValue": "100000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "L1 writebacks to L2 in M state",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0x28",
109
97
"EventName": "L1D_WB_L2.M_STATE",
110
98
"SampleAfterValue": "100000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "L1 writebacks to L2 in S state",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0x28",
117
104
"EventName": "L1D_WB_L2.S_STATE",
118
105
"SampleAfterValue": "100000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "All L2 data requests",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0x26",
125
111
"EventName": "L2_DATA_RQSTS.ANY",
126
112
"SampleAfterValue": "200000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "L2 data demand loads in E state",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0x26",
133
118
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
134
119
"SampleAfterValue": "200000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "L2 data demand loads in I state (misses)",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0x26",
141
125
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
142
126
"SampleAfterValue": "200000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "L2 data demand requests",
130
+
"Counter": "0,1,2,3",
148
131
"EventCode": "0x26",
149
132
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
150
133
"SampleAfterValue": "200000",
···
153
134
},
154
135
{
155
136
"BriefDescription": "L2 data demand loads in M state",
137
+
"Counter": "0,1,2,3",
156
138
"EventCode": "0x26",
157
139
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
158
140
"SampleAfterValue": "200000",
···
161
141
},
162
142
{
163
143
"BriefDescription": "L2 data demand loads in S state",
144
+
"Counter": "0,1,2,3",
164
145
"EventCode": "0x26",
165
146
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
166
147
"SampleAfterValue": "200000",
···
169
148
},
170
149
{
171
150
"BriefDescription": "L2 data prefetches in E state",
151
+
"Counter": "0,1,2,3",
172
152
"EventCode": "0x26",
173
153
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
174
154
"SampleAfterValue": "200000",
···
177
155
},
178
156
{
179
157
"BriefDescription": "L2 data prefetches in the I state (misses)",
158
+
"Counter": "0,1,2,3",
180
159
"EventCode": "0x26",
181
160
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
182
161
"SampleAfterValue": "200000",
···
185
162
},
186
163
{
187
164
"BriefDescription": "All L2 data prefetches",
165
+
"Counter": "0,1,2,3",
188
166
"EventCode": "0x26",
189
167
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
190
168
"SampleAfterValue": "200000",
···
193
169
},
194
170
{
195
171
"BriefDescription": "L2 data prefetches in M state",
172
+
"Counter": "0,1,2,3",
196
173
"EventCode": "0x26",
197
174
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
198
175
"SampleAfterValue": "200000",
···
201
176
},
202
177
{
203
178
"BriefDescription": "L2 data prefetches in the S state",
179
+
"Counter": "0,1,2,3",
204
180
"EventCode": "0x26",
205
181
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
206
182
"SampleAfterValue": "200000",
···
209
183
},
210
184
{
211
185
"BriefDescription": "L2 lines allocated",
186
+
"Counter": "0,1,2,3",
212
187
"EventCode": "0xF1",
213
188
"EventName": "L2_LINES_IN.ANY",
214
189
"SampleAfterValue": "100000",
···
217
190
},
218
191
{
219
192
"BriefDescription": "L2 lines allocated in the E state",
193
+
"Counter": "0,1,2,3",
220
194
"EventCode": "0xF1",
221
195
"EventName": "L2_LINES_IN.E_STATE",
222
196
"SampleAfterValue": "100000",
···
225
197
},
226
198
{
227
199
"BriefDescription": "L2 lines allocated in the S state",
200
+
"Counter": "0,1,2,3",
228
201
"EventCode": "0xF1",
229
202
"EventName": "L2_LINES_IN.S_STATE",
230
203
"SampleAfterValue": "100000",
···
233
204
},
234
205
{
235
206
"BriefDescription": "L2 lines evicted",
207
+
"Counter": "0,1,2,3",
236
208
"EventCode": "0xF2",
237
209
"EventName": "L2_LINES_OUT.ANY",
238
210
"SampleAfterValue": "100000",
···
241
211
},
242
212
{
243
213
"BriefDescription": "L2 lines evicted by a demand request",
214
+
"Counter": "0,1,2,3",
244
215
"EventCode": "0xF2",
245
216
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
246
217
"SampleAfterValue": "100000",
···
249
218
},
250
219
{
251
220
"BriefDescription": "L2 modified lines evicted by a demand request",
221
+
"Counter": "0,1,2,3",
252
222
"EventCode": "0xF2",
253
223
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
254
224
"SampleAfterValue": "100000",
···
257
225
},
258
226
{
259
227
"BriefDescription": "L2 lines evicted by a prefetch request",
228
+
"Counter": "0,1,2,3",
260
229
"EventCode": "0xF2",
261
230
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
262
231
"SampleAfterValue": "100000",
···
265
232
},
266
233
{
267
234
"BriefDescription": "L2 modified lines evicted by a prefetch request",
235
+
"Counter": "0,1,2,3",
268
236
"EventCode": "0xF2",
269
237
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
270
238
"SampleAfterValue": "100000",
···
273
239
},
274
240
{
275
241
"BriefDescription": "L2 instruction fetches",
242
+
"Counter": "0,1,2,3",
276
243
"EventCode": "0x24",
277
244
"EventName": "L2_RQSTS.IFETCHES",
278
245
"SampleAfterValue": "200000",
···
281
246
},
282
247
{
283
248
"BriefDescription": "L2 instruction fetch hits",
249
+
"Counter": "0,1,2,3",
284
250
"EventCode": "0x24",
285
251
"EventName": "L2_RQSTS.IFETCH_HIT",
286
252
"SampleAfterValue": "200000",
···
289
253
},
290
254
{
291
255
"BriefDescription": "L2 instruction fetch misses",
256
+
"Counter": "0,1,2,3",
292
257
"EventCode": "0x24",
293
258
"EventName": "L2_RQSTS.IFETCH_MISS",
294
259
"SampleAfterValue": "200000",
···
297
260
},
298
261
{
299
262
"BriefDescription": "L2 load hits",
263
+
"Counter": "0,1,2,3",
300
264
"EventCode": "0x24",
301
265
"EventName": "L2_RQSTS.LD_HIT",
302
266
"SampleAfterValue": "200000",
···
305
267
},
306
268
{
307
269
"BriefDescription": "L2 load misses",
270
+
"Counter": "0,1,2,3",
308
271
"EventCode": "0x24",
309
272
"EventName": "L2_RQSTS.LD_MISS",
310
273
"SampleAfterValue": "200000",
···
313
274
},
314
275
{
315
276
"BriefDescription": "L2 requests",
277
+
"Counter": "0,1,2,3",
316
278
"EventCode": "0x24",
317
279
"EventName": "L2_RQSTS.LOADS",
318
280
"SampleAfterValue": "200000",
···
321
281
},
322
282
{
323
283
"BriefDescription": "All L2 misses",
284
+
"Counter": "0,1,2,3",
324
285
"EventCode": "0x24",
325
286
"EventName": "L2_RQSTS.MISS",
326
287
"SampleAfterValue": "200000",
···
329
288
},
330
289
{
331
290
"BriefDescription": "All L2 prefetches",
291
+
"Counter": "0,1,2,3",
332
292
"EventCode": "0x24",
333
293
"EventName": "L2_RQSTS.PREFETCHES",
334
294
"SampleAfterValue": "200000",
···
337
295
},
338
296
{
339
297
"BriefDescription": "L2 prefetch hits",
298
+
"Counter": "0,1,2,3",
340
299
"EventCode": "0x24",
341
300
"EventName": "L2_RQSTS.PREFETCH_HIT",
342
301
"SampleAfterValue": "200000",
···
345
302
},
346
303
{
347
304
"BriefDescription": "L2 prefetch misses",
305
+
"Counter": "0,1,2,3",
348
306
"EventCode": "0x24",
349
307
"EventName": "L2_RQSTS.PREFETCH_MISS",
350
308
"SampleAfterValue": "200000",
···
353
309
},
354
310
{
355
311
"BriefDescription": "All L2 requests",
312
+
"Counter": "0,1,2,3",
356
313
"EventCode": "0x24",
357
314
"EventName": "L2_RQSTS.REFERENCES",
358
315
"SampleAfterValue": "200000",
···
361
316
},
362
317
{
363
318
"BriefDescription": "L2 RFO requests",
319
+
"Counter": "0,1,2,3",
364
320
"EventCode": "0x24",
365
321
"EventName": "L2_RQSTS.RFOS",
366
322
"SampleAfterValue": "200000",
···
369
323
},
370
324
{
371
325
"BriefDescription": "L2 RFO hits",
326
+
"Counter": "0,1,2,3",
372
327
"EventCode": "0x24",
373
328
"EventName": "L2_RQSTS.RFO_HIT",
374
329
"SampleAfterValue": "200000",
···
377
330
},
378
331
{
379
332
"BriefDescription": "L2 RFO misses",
333
+
"Counter": "0,1,2,3",
380
334
"EventCode": "0x24",
381
335
"EventName": "L2_RQSTS.RFO_MISS",
382
336
"SampleAfterValue": "200000",
···
385
337
},
386
338
{
387
339
"BriefDescription": "All L2 transactions",
340
+
"Counter": "0,1,2,3",
388
341
"EventCode": "0xF0",
389
342
"EventName": "L2_TRANSACTIONS.ANY",
390
343
"SampleAfterValue": "200000",
···
393
344
},
394
345
{
395
346
"BriefDescription": "L2 fill transactions",
347
+
"Counter": "0,1,2,3",
396
348
"EventCode": "0xF0",
397
349
"EventName": "L2_TRANSACTIONS.FILL",
398
350
"SampleAfterValue": "200000",
···
401
351
},
402
352
{
403
353
"BriefDescription": "L2 instruction fetch transactions",
354
+
"Counter": "0,1,2,3",
404
355
"EventCode": "0xF0",
405
356
"EventName": "L2_TRANSACTIONS.IFETCH",
406
357
"SampleAfterValue": "200000",
···
409
358
},
410
359
{
411
360
"BriefDescription": "L1D writeback to L2 transactions",
361
+
"Counter": "0,1,2,3",
412
362
"EventCode": "0xF0",
413
363
"EventName": "L2_TRANSACTIONS.L1D_WB",
414
364
"SampleAfterValue": "200000",
···
417
365
},
418
366
{
419
367
"BriefDescription": "L2 Load transactions",
368
+
"Counter": "0,1,2,3",
420
369
"EventCode": "0xF0",
421
370
"EventName": "L2_TRANSACTIONS.LOAD",
422
371
"SampleAfterValue": "200000",
···
425
372
},
426
373
{
427
374
"BriefDescription": "L2 prefetch transactions",
375
+
"Counter": "0,1,2,3",
428
376
"EventCode": "0xF0",
429
377
"EventName": "L2_TRANSACTIONS.PREFETCH",
430
378
"SampleAfterValue": "200000",
···
433
379
},
434
380
{
435
381
"BriefDescription": "L2 RFO transactions",
382
+
"Counter": "0,1,2,3",
436
383
"EventCode": "0xF0",
437
384
"EventName": "L2_TRANSACTIONS.RFO",
438
385
"SampleAfterValue": "200000",
···
441
386
},
442
387
{
443
388
"BriefDescription": "L2 writeback to LLC transactions",
389
+
"Counter": "0,1,2,3",
444
390
"EventCode": "0xF0",
445
391
"EventName": "L2_TRANSACTIONS.WB",
446
392
"SampleAfterValue": "200000",
···
449
393
},
450
394
{
451
395
"BriefDescription": "L2 demand lock RFOs in E state",
396
+
"Counter": "0,1,2,3",
452
397
"EventCode": "0x27",
453
398
"EventName": "L2_WRITE.LOCK.E_STATE",
454
399
"SampleAfterValue": "100000",
···
457
400
},
458
401
{
459
402
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
403
+
"Counter": "0,1,2,3",
460
404
"EventCode": "0x27",
461
405
"EventName": "L2_WRITE.LOCK.HIT",
462
406
"SampleAfterValue": "100000",
···
465
407
},
466
408
{
467
409
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
410
+
"Counter": "0,1,2,3",
468
411
"EventCode": "0x27",
469
412
"EventName": "L2_WRITE.LOCK.I_STATE",
470
413
"SampleAfterValue": "100000",
···
473
414
},
474
415
{
475
416
"BriefDescription": "All demand L2 lock RFOs",
417
+
"Counter": "0,1,2,3",
476
418
"EventCode": "0x27",
477
419
"EventName": "L2_WRITE.LOCK.MESI",
478
420
"SampleAfterValue": "100000",
···
481
421
},
482
422
{
483
423
"BriefDescription": "L2 demand lock RFOs in M state",
424
+
"Counter": "0,1,2,3",
484
425
"EventCode": "0x27",
485
426
"EventName": "L2_WRITE.LOCK.M_STATE",
486
427
"SampleAfterValue": "100000",
···
489
428
},
490
429
{
491
430
"BriefDescription": "L2 demand lock RFOs in S state",
431
+
"Counter": "0,1,2,3",
492
432
"EventCode": "0x27",
493
433
"EventName": "L2_WRITE.LOCK.S_STATE",
494
434
"SampleAfterValue": "100000",
···
497
435
},
498
436
{
499
437
"BriefDescription": "All L2 demand store RFOs that hit the cache",
438
+
"Counter": "0,1,2,3",
500
439
"EventCode": "0x27",
501
440
"EventName": "L2_WRITE.RFO.HIT",
502
441
"SampleAfterValue": "100000",
···
505
442
},
506
443
{
507
444
"BriefDescription": "L2 demand store RFOs in I state (misses)",
445
+
"Counter": "0,1,2,3",
508
446
"EventCode": "0x27",
509
447
"EventName": "L2_WRITE.RFO.I_STATE",
510
448
"SampleAfterValue": "100000",
···
513
449
},
514
450
{
515
451
"BriefDescription": "All L2 demand store RFOs",
452
+
"Counter": "0,1,2,3",
516
453
"EventCode": "0x27",
517
454
"EventName": "L2_WRITE.RFO.MESI",
518
455
"SampleAfterValue": "100000",
···
521
456
},
522
457
{
523
458
"BriefDescription": "L2 demand store RFOs in M state",
459
+
"Counter": "0,1,2,3",
524
460
"EventCode": "0x27",
525
461
"EventName": "L2_WRITE.RFO.M_STATE",
526
462
"SampleAfterValue": "100000",
···
529
463
},
530
464
{
531
465
"BriefDescription": "L2 demand store RFOs in S state",
466
+
"Counter": "0,1,2,3",
532
467
"EventCode": "0x27",
533
468
"EventName": "L2_WRITE.RFO.S_STATE",
534
469
"SampleAfterValue": "100000",
···
537
470
},
538
471
{
539
472
"BriefDescription": "Longest latency cache miss",
473
+
"Counter": "0,1,2,3",
540
474
"EventCode": "0x2E",
541
475
"EventName": "LONGEST_LAT_CACHE.MISS",
542
476
"SampleAfterValue": "100000",
···
545
477
},
546
478
{
547
479
"BriefDescription": "Longest latency cache reference",
480
+
"Counter": "0,1,2,3",
548
481
"EventCode": "0x2E",
549
482
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
550
483
"SampleAfterValue": "200000",
···
553
484
},
554
485
{
555
486
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
487
+
"Counter": "3",
556
488
"EventCode": "0xB",
557
489
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
558
490
"MSRIndex": "0x3F6",
···
563
493
},
564
494
{
565
495
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
496
+
"Counter": "3",
566
497
"EventCode": "0xB",
567
498
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
568
499
"MSRIndex": "0x3F6",
···
574
503
},
575
504
{
576
505
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
506
+
"Counter": "3",
577
507
"EventCode": "0xB",
578
508
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
579
509
"MSRIndex": "0x3F6",
···
585
513
},
586
514
{
587
515
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
516
+
"Counter": "3",
588
517
"EventCode": "0xB",
589
518
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
590
519
"MSRIndex": "0x3F6",
···
596
523
},
597
524
{
598
525
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
526
+
"Counter": "3",
599
527
"EventCode": "0xB",
600
528
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
601
529
"MSRIndex": "0x3F6",
···
607
533
},
608
534
{
609
535
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
536
+
"Counter": "3",
610
537
"EventCode": "0xB",
611
538
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
612
539
"MSRIndex": "0x3F6",
···
618
543
},
619
544
{
620
545
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
546
+
"Counter": "3",
621
547
"EventCode": "0xB",
622
548
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
623
549
"MSRIndex": "0x3F6",
···
629
553
},
630
554
{
631
555
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
556
+
"Counter": "3",
632
557
"EventCode": "0xB",
633
558
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
634
559
"MSRIndex": "0x3F6",
···
640
563
},
641
564
{
642
565
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
566
+
"Counter": "3",
643
567
"EventCode": "0xB",
644
568
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
645
569
"MSRIndex": "0x3F6",
···
651
573
},
652
574
{
653
575
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
576
+
"Counter": "3",
654
577
"EventCode": "0xB",
655
578
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
656
579
"MSRIndex": "0x3F6",
···
662
583
},
663
584
{
664
585
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
586
+
"Counter": "3",
665
587
"EventCode": "0xB",
666
588
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
667
589
"MSRIndex": "0x3F6",
···
673
593
},
674
594
{
675
595
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
596
+
"Counter": "3",
676
597
"EventCode": "0xB",
677
598
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
678
599
"MSRIndex": "0x3F6",
···
684
603
},
685
604
{
686
605
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
606
+
"Counter": "3",
687
607
"EventCode": "0xB",
688
608
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
689
609
"MSRIndex": "0x3F6",
···
695
613
},
696
614
{
697
615
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
616
+
"Counter": "3",
698
617
"EventCode": "0xB",
699
618
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
700
619
"MSRIndex": "0x3F6",
···
706
623
},
707
624
{
708
625
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
626
+
"Counter": "3",
709
627
"EventCode": "0xB",
710
628
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
711
629
"MSRIndex": "0x3F6",
···
717
633
},
718
634
{
719
635
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
636
+
"Counter": "0,1,2,3",
720
637
"EventCode": "0xB",
721
638
"EventName": "MEM_INST_RETIRED.LOADS",
722
639
"PEBS": "1",
···
726
641
},
727
642
{
728
643
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
644
+
"Counter": "0,1,2,3",
729
645
"EventCode": "0xB",
730
646
"EventName": "MEM_INST_RETIRED.STORES",
731
647
"PEBS": "1",
···
735
649
},
736
650
{
737
651
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
652
+
"Counter": "0,1,2,3",
738
653
"EventCode": "0xCB",
739
654
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
740
655
"PEBS": "1",
···
744
657
},
745
658
{
746
659
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
660
+
"Counter": "0,1,2,3",
747
661
"EventCode": "0xCB",
748
662
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
749
663
"PEBS": "1",
···
753
665
},
754
666
{
755
667
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
668
+
"Counter": "0,1,2,3",
756
669
"EventCode": "0xCB",
757
670
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
758
671
"PEBS": "1",
···
762
673
},
763
674
{
764
675
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
676
+
"Counter": "0,1,2,3",
765
677
"EventCode": "0xCB",
766
678
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
767
679
"PEBS": "1",
···
771
681
},
772
682
{
773
683
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
684
+
"Counter": "0,1,2,3",
774
685
"EventCode": "0xCB",
775
686
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
776
687
"PEBS": "1",
···
780
689
},
781
690
{
782
691
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
692
+
"Counter": "0,1,2,3",
783
693
"EventCode": "0xCB",
784
694
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
785
695
"PEBS": "1",
···
789
697
},
790
698
{
791
699
"BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)",
700
+
"Counter": "0,1,2,3",
792
701
"EventCode": "0xF",
793
702
"EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
794
703
"PEBS": "1",
···
798
705
},
799
706
{
800
707
"BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
708
+
"Counter": "0,1,2,3",
801
709
"EventCode": "0xF",
802
710
"EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",
803
711
"PEBS": "1",
···
807
713
},
808
714
{
809
715
"BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
716
+
"Counter": "0,1,2,3",
810
717
"EventCode": "0xF",
811
718
"EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
812
719
"PEBS": "1",
···
816
721
},
817
722
{
818
723
"BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)",
724
+
"Counter": "0,1,2,3",
819
725
"EventCode": "0xF",
820
726
"EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",
821
727
"PEBS": "1",
···
825
729
},
826
730
{
827
731
"BriefDescription": "Load instructions retired IO (Precise Event)",
732
+
"Counter": "0,1,2,3",
828
733
"EventCode": "0xF",
829
734
"EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
830
735
"PEBS": "1",
···
834
737
},
835
738
{
836
739
"BriefDescription": "All offcore requests",
740
+
"Counter": "0,1,2,3",
837
741
"EventCode": "0xB0",
838
742
"EventName": "OFFCORE_REQUESTS.ANY",
839
743
"SampleAfterValue": "100000",
···
842
744
},
843
745
{
844
746
"BriefDescription": "Offcore read requests",
747
+
"Counter": "0,1,2,3",
845
748
"EventCode": "0xB0",
846
749
"EventName": "OFFCORE_REQUESTS.ANY.READ",
847
750
"SampleAfterValue": "100000",
···
850
751
},
851
752
{
852
753
"BriefDescription": "Offcore RFO requests",
754
+
"Counter": "0,1,2,3",
853
755
"EventCode": "0xB0",
854
756
"EventName": "OFFCORE_REQUESTS.ANY.RFO",
855
757
"SampleAfterValue": "100000",
···
858
758
},
859
759
{
860
760
"BriefDescription": "Offcore demand code read requests",
761
+
"Counter": "0,1,2,3",
861
762
"EventCode": "0xB0",
862
763
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
863
764
"SampleAfterValue": "100000",
···
866
765
},
867
766
{
868
767
"BriefDescription": "Offcore demand data read requests",
768
+
"Counter": "0,1,2,3",
869
769
"EventCode": "0xB0",
870
770
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
871
771
"SampleAfterValue": "100000",
···
874
772
},
875
773
{
876
774
"BriefDescription": "Offcore demand RFO requests",
775
+
"Counter": "0,1,2,3",
877
776
"EventCode": "0xB0",
878
777
"EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
879
778
"SampleAfterValue": "100000",
···
882
779
},
883
780
{
884
781
"BriefDescription": "Offcore L1 data cache writebacks",
782
+
"Counter": "0,1,2,3",
885
783
"EventCode": "0xB0",
886
784
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
887
785
"SampleAfterValue": "100000",
···
890
786
},
891
787
{
892
788
"BriefDescription": "Outstanding offcore reads",
789
+
"Counter": "0",
893
790
"EventCode": "0x60",
894
791
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
895
792
"SampleAfterValue": "2000000",
···
898
793
},
899
794
{
900
795
"BriefDescription": "Cycles offcore reads busy",
796
+
"Counter": "0",
901
797
"CounterMask": "1",
902
798
"EventCode": "0x60",
903
799
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
···
907
801
},
908
802
{
909
803
"BriefDescription": "Outstanding offcore demand code reads",
804
+
"Counter": "0",
910
805
"EventCode": "0x60",
911
806
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
912
807
"SampleAfterValue": "2000000",
···
915
808
},
916
809
{
917
810
"BriefDescription": "Cycles offcore demand code read busy",
811
+
"Counter": "0",
918
812
"CounterMask": "1",
919
813
"EventCode": "0x60",
920
814
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
···
924
816
},
925
817
{
926
818
"BriefDescription": "Outstanding offcore demand data reads",
819
+
"Counter": "0",
927
820
"EventCode": "0x60",
928
821
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
929
822
"SampleAfterValue": "2000000",
···
932
823
},
933
824
{
934
825
"BriefDescription": "Cycles offcore demand data read busy",
826
+
"Counter": "0",
935
827
"CounterMask": "1",
936
828
"EventCode": "0x60",
937
829
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
···
941
831
},
942
832
{
943
833
"BriefDescription": "Outstanding offcore demand RFOs",
834
+
"Counter": "0",
944
835
"EventCode": "0x60",
945
836
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
946
837
"SampleAfterValue": "2000000",
···
949
838
},
950
839
{
951
840
"BriefDescription": "Cycles offcore demand RFOs busy",
841
+
"Counter": "0",
952
842
"CounterMask": "1",
953
843
"EventCode": "0x60",
954
844
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
···
958
846
},
959
847
{
960
848
"BriefDescription": "Offcore requests blocked due to Super Queue full",
849
+
"Counter": "0,1,2,3",
961
850
"EventCode": "0xB2",
962
851
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
963
852
"SampleAfterValue": "100000",
···
966
853
},
967
854
{
968
855
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
856
+
"Counter": "2",
969
857
"EventCode": "0xB7",
970
858
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
971
859
"MSRIndex": "0x1A6",
···
976
862
},
977
863
{
978
864
"BriefDescription": "All offcore data reads",
865
+
"Counter": "2",
979
866
"EventCode": "0xB7",
980
867
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
981
868
"MSRIndex": "0x1A6",
···
986
871
},
987
872
{
988
873
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
874
+
"Counter": "2",
989
875
"EventCode": "0xB7",
990
876
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
991
877
"MSRIndex": "0x1A6",
···
996
880
},
997
881
{
998
882
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
883
+
"Counter": "2",
999
884
"EventCode": "0xB7",
1000
885
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
1001
886
"MSRIndex": "0x1A6",
···
1006
889
},
1007
890
{
1008
891
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
892
+
"Counter": "2",
1009
893
"EventCode": "0xB7",
1010
894
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
1011
895
"MSRIndex": "0x1A6",
···
1016
898
},
1017
899
{
1018
900
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
901
+
"Counter": "2",
1019
902
"EventCode": "0xB7",
1020
903
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
1021
904
"MSRIndex": "0x1A6",
···
1026
907
},
1027
908
{
1028
909
"BriefDescription": "Offcore data reads satisfied by the LLC",
910
+
"Counter": "2",
1029
911
"EventCode": "0xB7",
1030
912
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
1031
913
"MSRIndex": "0x1A6",
···
1036
916
},
1037
917
{
1038
918
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
919
+
"Counter": "2",
1039
920
"EventCode": "0xB7",
1040
921
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
1041
922
"MSRIndex": "0x1A6",
···
1046
925
},
1047
926
{
1048
927
"BriefDescription": "Offcore data reads satisfied by a remote cache",
928
+
"Counter": "2",
1049
929
"EventCode": "0xB7",
1050
930
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
1051
931
"MSRIndex": "0x1A6",
···
1056
934
},
1057
935
{
1058
936
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
937
+
"Counter": "2",
1059
938
"EventCode": "0xB7",
1060
939
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
1061
940
"MSRIndex": "0x1A6",
···
1066
943
},
1067
944
{
1068
945
"BriefDescription": "Offcore data reads that HIT in a remote cache",
946
+
"Counter": "2",
1069
947
"EventCode": "0xB7",
1070
948
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
1071
949
"MSRIndex": "0x1A6",
···
1076
952
},
1077
953
{
1078
954
"BriefDescription": "Offcore data reads that HITM in a remote cache",
955
+
"Counter": "2",
1079
956
"EventCode": "0xB7",
1080
957
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1081
958
"MSRIndex": "0x1A6",
···
1086
961
},
1087
962
{
1088
963
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
964
+
"Counter": "2",
1089
965
"EventCode": "0xB7",
1090
966
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1091
967
"MSRIndex": "0x1A6",
···
1096
970
},
1097
971
{
1098
972
"BriefDescription": "All offcore code reads",
973
+
"Counter": "2",
1099
974
"EventCode": "0xB7",
1100
975
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1101
976
"MSRIndex": "0x1A6",
···
1106
979
},
1107
980
{
1108
981
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
982
+
"Counter": "2",
1109
983
"EventCode": "0xB7",
1110
984
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1111
985
"MSRIndex": "0x1A6",
···
1116
988
},
1117
989
{
1118
990
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
991
+
"Counter": "2",
1119
992
"EventCode": "0xB7",
1120
993
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1121
994
"MSRIndex": "0x1A6",
···
1126
997
},
1127
998
{
1128
999
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
1000
+
"Counter": "2",
1129
1001
"EventCode": "0xB7",
1130
1002
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1131
1003
"MSRIndex": "0x1A6",
···
1136
1006
},
1137
1007
{
1138
1008
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
1009
+
"Counter": "2",
1139
1010
"EventCode": "0xB7",
1140
1011
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1141
1012
"MSRIndex": "0x1A6",
···
1146
1015
},
1147
1016
{
1148
1017
"BriefDescription": "Offcore code reads satisfied by the LLC",
1018
+
"Counter": "2",
1149
1019
"EventCode": "0xB7",
1150
1020
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1151
1021
"MSRIndex": "0x1A6",
···
1156
1024
},
1157
1025
{
1158
1026
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
1027
+
"Counter": "2",
1159
1028
"EventCode": "0xB7",
1160
1029
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1161
1030
"MSRIndex": "0x1A6",
···
1166
1033
},
1167
1034
{
1168
1035
"BriefDescription": "Offcore code reads satisfied by a remote cache",
1036
+
"Counter": "2",
1169
1037
"EventCode": "0xB7",
1170
1038
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1171
1039
"MSRIndex": "0x1A6",
···
1176
1042
},
1177
1043
{
1178
1044
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1045
+
"Counter": "2",
1179
1046
"EventCode": "0xB7",
1180
1047
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1181
1048
"MSRIndex": "0x1A6",
···
1186
1051
},
1187
1052
{
1188
1053
"BriefDescription": "Offcore code reads that HIT in a remote cache",
1054
+
"Counter": "2",
1189
1055
"EventCode": "0xB7",
1190
1056
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1191
1057
"MSRIndex": "0x1A6",
···
1196
1060
},
1197
1061
{
1198
1062
"BriefDescription": "Offcore code reads that HITM in a remote cache",
1063
+
"Counter": "2",
1199
1064
"EventCode": "0xB7",
1200
1065
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1201
1066
"MSRIndex": "0x1A6",
···
1206
1069
},
1207
1070
{
1208
1071
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1072
+
"Counter": "2",
1209
1073
"EventCode": "0xB7",
1210
1074
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1211
1075
"MSRIndex": "0x1A6",
···
1216
1078
},
1217
1079
{
1218
1080
"BriefDescription": "All offcore requests",
1081
+
"Counter": "2",
1219
1082
"EventCode": "0xB7",
1220
1083
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1221
1084
"MSRIndex": "0x1A6",
···
1226
1087
},
1227
1088
{
1228
1089
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1090
+
"Counter": "2",
1229
1091
"EventCode": "0xB7",
1230
1092
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1231
1093
"MSRIndex": "0x1A6",
···
1236
1096
},
1237
1097
{
1238
1098
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1099
+
"Counter": "2",
1239
1100
"EventCode": "0xB7",
1240
1101
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1241
1102
"MSRIndex": "0x1A6",
···
1246
1105
},
1247
1106
{
1248
1107
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1108
+
"Counter": "2",
1249
1109
"EventCode": "0xB7",
1250
1110
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1251
1111
"MSRIndex": "0x1A6",
···
1256
1114
},
1257
1115
{
1258
1116
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
1117
+
"Counter": "2",
1259
1118
"EventCode": "0xB7",
1260
1119
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1261
1120
"MSRIndex": "0x1A6",
···
1266
1123
},
1267
1124
{
1268
1125
"BriefDescription": "Offcore requests satisfied by the LLC",
1126
+
"Counter": "2",
1269
1127
"EventCode": "0xB7",
1270
1128
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1271
1129
"MSRIndex": "0x1A6",
···
1276
1132
},
1277
1133
{
1278
1134
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1135
+
"Counter": "2",
1279
1136
"EventCode": "0xB7",
1280
1137
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1281
1138
"MSRIndex": "0x1A6",
···
1286
1141
},
1287
1142
{
1288
1143
"BriefDescription": "Offcore requests satisfied by a remote cache",
1144
+
"Counter": "2",
1289
1145
"EventCode": "0xB7",
1290
1146
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1291
1147
"MSRIndex": "0x1A6",
···
1296
1150
},
1297
1151
{
1298
1152
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1153
+
"Counter": "2",
1299
1154
"EventCode": "0xB7",
1300
1155
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1301
1156
"MSRIndex": "0x1A6",
···
1306
1159
},
1307
1160
{
1308
1161
"BriefDescription": "Offcore requests that HIT in a remote cache",
1162
+
"Counter": "2",
1309
1163
"EventCode": "0xB7",
1310
1164
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1311
1165
"MSRIndex": "0x1A6",
···
1316
1168
},
1317
1169
{
1318
1170
"BriefDescription": "Offcore requests that HITM in a remote cache",
1171
+
"Counter": "2",
1319
1172
"EventCode": "0xB7",
1320
1173
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1321
1174
"MSRIndex": "0x1A6",
···
1326
1177
},
1327
1178
{
1328
1179
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1180
+
"Counter": "2",
1329
1181
"EventCode": "0xB7",
1330
1182
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1331
1183
"MSRIndex": "0x1A6",
···
1336
1186
},
1337
1187
{
1338
1188
"BriefDescription": "All offcore RFO requests",
1189
+
"Counter": "2",
1339
1190
"EventCode": "0xB7",
1340
1191
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1341
1192
"MSRIndex": "0x1A6",
···
1346
1195
},
1347
1196
{
1348
1197
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1198
+
"Counter": "2",
1349
1199
"EventCode": "0xB7",
1350
1200
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1351
1201
"MSRIndex": "0x1A6",
···
1356
1204
},
1357
1205
{
1358
1206
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1207
+
"Counter": "2",
1359
1208
"EventCode": "0xB7",
1360
1209
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1361
1210
"MSRIndex": "0x1A6",
···
1366
1213
},
1367
1214
{
1368
1215
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1216
+
"Counter": "2",
1369
1217
"EventCode": "0xB7",
1370
1218
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1371
1219
"MSRIndex": "0x1A6",
···
1376
1222
},
1377
1223
{
1378
1224
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
1225
+
"Counter": "2",
1379
1226
"EventCode": "0xB7",
1380
1227
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1381
1228
"MSRIndex": "0x1A6",
···
1386
1231
},
1387
1232
{
1388
1233
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
1234
+
"Counter": "2",
1389
1235
"EventCode": "0xB7",
1390
1236
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1391
1237
"MSRIndex": "0x1A6",
···
1396
1240
},
1397
1241
{
1398
1242
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1243
+
"Counter": "2",
1399
1244
"EventCode": "0xB7",
1400
1245
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1401
1246
"MSRIndex": "0x1A6",
···
1406
1249
},
1407
1250
{
1408
1251
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1252
+
"Counter": "2",
1409
1253
"EventCode": "0xB7",
1410
1254
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1411
1255
"MSRIndex": "0x1A6",
···
1416
1258
},
1417
1259
{
1418
1260
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1261
+
"Counter": "2",
1419
1262
"EventCode": "0xB7",
1420
1263
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1421
1264
"MSRIndex": "0x1A6",
···
1426
1267
},
1427
1268
{
1428
1269
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1270
+
"Counter": "2",
1429
1271
"EventCode": "0xB7",
1430
1272
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1431
1273
"MSRIndex": "0x1A6",
···
1436
1276
},
1437
1277
{
1438
1278
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1279
+
"Counter": "2",
1439
1280
"EventCode": "0xB7",
1440
1281
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1441
1282
"MSRIndex": "0x1A6",
···
1446
1285
},
1447
1286
{
1448
1287
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
1288
+
"Counter": "2",
1449
1289
"EventCode": "0xB7",
1450
1290
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1451
1291
"MSRIndex": "0x1A6",
···
1456
1294
},
1457
1295
{
1458
1296
"BriefDescription": "All offcore writebacks",
1297
+
"Counter": "2",
1459
1298
"EventCode": "0xB7",
1460
1299
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1461
1300
"MSRIndex": "0x1A6",
···
1466
1303
},
1467
1304
{
1468
1305
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1306
+
"Counter": "2",
1469
1307
"EventCode": "0xB7",
1470
1308
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1471
1309
"MSRIndex": "0x1A6",
···
1476
1312
},
1477
1313
{
1478
1314
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1315
+
"Counter": "2",
1479
1316
"EventCode": "0xB7",
1480
1317
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1481
1318
"MSRIndex": "0x1A6",
···
1486
1321
},
1487
1322
{
1488
1323
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
1324
+
"Counter": "2",
1489
1325
"EventCode": "0xB7",
1490
1326
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1491
1327
"MSRIndex": "0x1A6",
···
1496
1330
},
1497
1331
{
1498
1332
"BriefDescription": "Offcore writebacks to the LLC",
1333
+
"Counter": "2",
1499
1334
"EventCode": "0xB7",
1500
1335
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1501
1336
"MSRIndex": "0x1A6",
···
1506
1339
},
1507
1340
{
1508
1341
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1342
+
"Counter": "2",
1509
1343
"EventCode": "0xB7",
1510
1344
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1511
1345
"MSRIndex": "0x1A6",
···
1516
1348
},
1517
1349
{
1518
1350
"BriefDescription": "Offcore writebacks to a remote cache",
1351
+
"Counter": "2",
1519
1352
"EventCode": "0xB7",
1520
1353
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1521
1354
"MSRIndex": "0x1A6",
···
1526
1357
},
1527
1358
{
1528
1359
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1360
+
"Counter": "2",
1529
1361
"EventCode": "0xB7",
1530
1362
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1531
1363
"MSRIndex": "0x1A6",
···
1536
1366
},
1537
1367
{
1538
1368
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
1369
+
"Counter": "2",
1539
1370
"EventCode": "0xB7",
1540
1371
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1541
1372
"MSRIndex": "0x1A6",
···
1546
1375
},
1547
1376
{
1548
1377
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
1378
+
"Counter": "2",
1549
1379
"EventCode": "0xB7",
1550
1380
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1551
1381
"MSRIndex": "0x1A6",
···
1556
1384
},
1557
1385
{
1558
1386
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1387
+
"Counter": "2",
1559
1388
"EventCode": "0xB7",
1560
1389
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1561
1390
"MSRIndex": "0x1A6",
···
1566
1393
},
1567
1394
{
1568
1395
"BriefDescription": "All offcore code or data read requests",
1396
+
"Counter": "2",
1569
1397
"EventCode": "0xB7",
1570
1398
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1571
1399
"MSRIndex": "0x1A6",
···
1576
1402
},
1577
1403
{
1578
1404
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1405
+
"Counter": "2",
1579
1406
"EventCode": "0xB7",
1580
1407
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1581
1408
"MSRIndex": "0x1A6",
···
1586
1411
},
1587
1412
{
1588
1413
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1414
+
"Counter": "2",
1589
1415
"EventCode": "0xB7",
1590
1416
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1591
1417
"MSRIndex": "0x1A6",
···
1596
1420
},
1597
1421
{
1598
1422
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1423
+
"Counter": "2",
1599
1424
"EventCode": "0xB7",
1600
1425
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1601
1426
"MSRIndex": "0x1A6",
···
1606
1429
},
1607
1430
{
1608
1431
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
1432
+
"Counter": "2",
1609
1433
"EventCode": "0xB7",
1610
1434
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1611
1435
"MSRIndex": "0x1A6",
···
1616
1438
},
1617
1439
{
1618
1440
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1441
+
"Counter": "2",
1619
1442
"EventCode": "0xB7",
1620
1443
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1621
1444
"MSRIndex": "0x1A6",
···
1626
1447
},
1627
1448
{
1628
1449
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1450
+
"Counter": "2",
1629
1451
"EventCode": "0xB7",
1630
1452
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1631
1453
"MSRIndex": "0x1A6",
···
1636
1456
},
1637
1457
{
1638
1458
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1459
+
"Counter": "2",
1639
1460
"EventCode": "0xB7",
1640
1461
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1641
1462
"MSRIndex": "0x1A6",
···
1646
1465
},
1647
1466
{
1648
1467
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1468
+
"Counter": "2",
1649
1469
"EventCode": "0xB7",
1650
1470
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1651
1471
"MSRIndex": "0x1A6",
···
1656
1474
},
1657
1475
{
1658
1476
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1477
+
"Counter": "2",
1659
1478
"EventCode": "0xB7",
1660
1479
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1661
1480
"MSRIndex": "0x1A6",
···
1666
1483
},
1667
1484
{
1668
1485
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1486
+
"Counter": "2",
1669
1487
"EventCode": "0xB7",
1670
1488
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1671
1489
"MSRIndex": "0x1A6",
···
1676
1492
},
1677
1493
{
1678
1494
"BriefDescription": "Offcore request = all data, response = any cache_dram",
1495
+
"Counter": "2",
1679
1496
"EventCode": "0xB7",
1680
1497
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1681
1498
"MSRIndex": "0x1A6",
···
1686
1501
},
1687
1502
{
1688
1503
"BriefDescription": "Offcore request = all data, response = any location",
1504
+
"Counter": "2",
1689
1505
"EventCode": "0xB7",
1690
1506
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1691
1507
"MSRIndex": "0x1A6",
···
1696
1510
},
1697
1511
{
1698
1512
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
1513
+
"Counter": "2",
1699
1514
"EventCode": "0xB7",
1700
1515
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1701
1516
"MSRIndex": "0x1A6",
···
1706
1519
},
1707
1520
{
1708
1521
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
1522
+
"Counter": "2",
1709
1523
"EventCode": "0xB7",
1710
1524
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1711
1525
"MSRIndex": "0x1A6",
···
1716
1528
},
1717
1529
{
1718
1530
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
1531
+
"Counter": "2",
1719
1532
"EventCode": "0xB7",
1720
1533
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1721
1534
"MSRIndex": "0x1A6",
···
1726
1537
},
1727
1538
{
1728
1539
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
1540
+
"Counter": "2",
1729
1541
"EventCode": "0xB7",
1730
1542
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1731
1543
"MSRIndex": "0x1A6",
···
1736
1546
},
1737
1547
{
1738
1548
"BriefDescription": "Offcore request = all data, response = local cache",
1549
+
"Counter": "2",
1739
1550
"EventCode": "0xB7",
1740
1551
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1741
1552
"MSRIndex": "0x1A6",
···
1746
1555
},
1747
1556
{
1748
1557
"BriefDescription": "Offcore request = all data, response = local cache or dram",
1558
+
"Counter": "2",
1749
1559
"EventCode": "0xB7",
1750
1560
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1751
1561
"MSRIndex": "0x1A6",
···
1756
1564
},
1757
1565
{
1758
1566
"BriefDescription": "Offcore request = all data, response = remote cache",
1567
+
"Counter": "2",
1759
1568
"EventCode": "0xB7",
1760
1569
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1761
1570
"MSRIndex": "0x1A6",
···
1766
1573
},
1767
1574
{
1768
1575
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
1576
+
"Counter": "2",
1769
1577
"EventCode": "0xB7",
1770
1578
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1771
1579
"MSRIndex": "0x1A6",
···
1776
1582
},
1777
1583
{
1778
1584
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
1585
+
"Counter": "2",
1779
1586
"EventCode": "0xB7",
1780
1587
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1781
1588
"MSRIndex": "0x1A6",
···
1786
1591
},
1787
1592
{
1788
1593
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
1594
+
"Counter": "2",
1789
1595
"EventCode": "0xB7",
1790
1596
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1791
1597
"MSRIndex": "0x1A6",
···
1796
1600
},
1797
1601
{
1798
1602
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1603
+
"Counter": "2",
1799
1604
"EventCode": "0xB7",
1800
1605
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1801
1606
"MSRIndex": "0x1A6",
···
1806
1609
},
1807
1610
{
1808
1611
"BriefDescription": "All offcore demand data requests",
1612
+
"Counter": "2",
1809
1613
"EventCode": "0xB7",
1810
1614
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1811
1615
"MSRIndex": "0x1A6",
···
1816
1618
},
1817
1619
{
1818
1620
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1621
+
"Counter": "2",
1819
1622
"EventCode": "0xB7",
1820
1623
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1821
1624
"MSRIndex": "0x1A6",
···
1826
1627
},
1827
1628
{
1828
1629
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1630
+
"Counter": "2",
1829
1631
"EventCode": "0xB7",
1830
1632
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1831
1633
"MSRIndex": "0x1A6",
···
1836
1636
},
1837
1637
{
1838
1638
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1639
+
"Counter": "2",
1839
1640
"EventCode": "0xB7",
1840
1641
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1841
1642
"MSRIndex": "0x1A6",
···
1846
1645
},
1847
1646
{
1848
1647
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
1648
+
"Counter": "2",
1849
1649
"EventCode": "0xB7",
1850
1650
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1851
1651
"MSRIndex": "0x1A6",
···
1856
1654
},
1857
1655
{
1858
1656
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
1657
+
"Counter": "2",
1859
1658
"EventCode": "0xB7",
1860
1659
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1861
1660
"MSRIndex": "0x1A6",
···
1866
1663
},
1867
1664
{
1868
1665
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1666
+
"Counter": "2",
1869
1667
"EventCode": "0xB7",
1870
1668
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1871
1669
"MSRIndex": "0x1A6",
···
1876
1672
},
1877
1673
{
1878
1674
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
1675
+
"Counter": "2",
1879
1676
"EventCode": "0xB7",
1880
1677
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
1881
1678
"MSRIndex": "0x1A6",
···
1886
1681
},
1887
1682
{
1888
1683
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
1684
+
"Counter": "2",
1889
1685
"EventCode": "0xB7",
1890
1686
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
1891
1687
"MSRIndex": "0x1A6",
···
1896
1690
},
1897
1691
{
1898
1692
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
1693
+
"Counter": "2",
1899
1694
"EventCode": "0xB7",
1900
1695
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
1901
1696
"MSRIndex": "0x1A6",
···
1906
1699
},
1907
1700
{
1908
1701
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
1702
+
"Counter": "2",
1909
1703
"EventCode": "0xB7",
1910
1704
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1911
1705
"MSRIndex": "0x1A6",
···
1916
1708
},
1917
1709
{
1918
1710
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
1711
+
"Counter": "2",
1919
1712
"EventCode": "0xB7",
1920
1713
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1921
1714
"MSRIndex": "0x1A6",
···
1926
1717
},
1927
1718
{
1928
1719
"BriefDescription": "All offcore demand data reads",
1720
+
"Counter": "2",
1929
1721
"EventCode": "0xB7",
1930
1722
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1931
1723
"MSRIndex": "0x1A6",
···
1936
1726
},
1937
1727
{
1938
1728
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
1729
+
"Counter": "2",
1939
1730
"EventCode": "0xB7",
1940
1731
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1941
1732
"MSRIndex": "0x1A6",
···
1946
1735
},
1947
1736
{
1948
1737
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
1738
+
"Counter": "2",
1949
1739
"EventCode": "0xB7",
1950
1740
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1951
1741
"MSRIndex": "0x1A6",
···
1956
1744
},
1957
1745
{
1958
1746
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
1747
+
"Counter": "2",
1959
1748
"EventCode": "0xB7",
1960
1749
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1961
1750
"MSRIndex": "0x1A6",
···
1966
1753
},
1967
1754
{
1968
1755
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
1756
+
"Counter": "2",
1969
1757
"EventCode": "0xB7",
1970
1758
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1971
1759
"MSRIndex": "0x1A6",
···
1976
1762
},
1977
1763
{
1978
1764
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
1765
+
"Counter": "2",
1979
1766
"EventCode": "0xB7",
1980
1767
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1981
1768
"MSRIndex": "0x1A6",
···
1986
1771
},
1987
1772
{
1988
1773
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
1774
+
"Counter": "2",
1989
1775
"EventCode": "0xB7",
1990
1776
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
1991
1777
"MSRIndex": "0x1A6",
···
1996
1780
},
1997
1781
{
1998
1782
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
1783
+
"Counter": "2",
1999
1784
"EventCode": "0xB7",
2000
1785
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
2001
1786
"MSRIndex": "0x1A6",
···
2006
1789
},
2007
1790
{
2008
1791
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
1792
+
"Counter": "2",
2009
1793
"EventCode": "0xB7",
2010
1794
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
2011
1795
"MSRIndex": "0x1A6",
···
2016
1798
},
2017
1799
{
2018
1800
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
1801
+
"Counter": "2",
2019
1802
"EventCode": "0xB7",
2020
1803
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
2021
1804
"MSRIndex": "0x1A6",
···
2026
1807
},
2027
1808
{
2028
1809
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
1810
+
"Counter": "2",
2029
1811
"EventCode": "0xB7",
2030
1812
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
2031
1813
"MSRIndex": "0x1A6",
···
2036
1816
},
2037
1817
{
2038
1818
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
1819
+
"Counter": "2",
2039
1820
"EventCode": "0xB7",
2040
1821
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
2041
1822
"MSRIndex": "0x1A6",
···
2046
1825
},
2047
1826
{
2048
1827
"BriefDescription": "All offcore demand code reads",
1828
+
"Counter": "2",
2049
1829
"EventCode": "0xB7",
2050
1830
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
2051
1831
"MSRIndex": "0x1A6",
···
2056
1834
},
2057
1835
{
2058
1836
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
1837
+
"Counter": "2",
2059
1838
"EventCode": "0xB7",
2060
1839
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
2061
1840
"MSRIndex": "0x1A6",
···
2066
1843
},
2067
1844
{
2068
1845
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
1846
+
"Counter": "2",
2069
1847
"EventCode": "0xB7",
2070
1848
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
2071
1849
"MSRIndex": "0x1A6",
···
2076
1852
},
2077
1853
{
2078
1854
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
1855
+
"Counter": "2",
2079
1856
"EventCode": "0xB7",
2080
1857
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2081
1858
"MSRIndex": "0x1A6",
···
2086
1861
},
2087
1862
{
2088
1863
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
1864
+
"Counter": "2",
2089
1865
"EventCode": "0xB7",
2090
1866
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2091
1867
"MSRIndex": "0x1A6",
···
2096
1870
},
2097
1871
{
2098
1872
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
1873
+
"Counter": "2",
2099
1874
"EventCode": "0xB7",
2100
1875
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2101
1876
"MSRIndex": "0x1A6",
···
2106
1879
},
2107
1880
{
2108
1881
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
1882
+
"Counter": "2",
2109
1883
"EventCode": "0xB7",
2110
1884
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
2111
1885
"MSRIndex": "0x1A6",
···
2116
1888
},
2117
1889
{
2118
1890
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
1891
+
"Counter": "2",
2119
1892
"EventCode": "0xB7",
2120
1893
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
2121
1894
"MSRIndex": "0x1A6",
···
2126
1897
},
2127
1898
{
2128
1899
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
1900
+
"Counter": "2",
2129
1901
"EventCode": "0xB7",
2130
1902
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
2131
1903
"MSRIndex": "0x1A6",
···
2136
1906
},
2137
1907
{
2138
1908
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
1909
+
"Counter": "2",
2139
1910
"EventCode": "0xB7",
2140
1911
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
2141
1912
"MSRIndex": "0x1A6",
···
2146
1915
},
2147
1916
{
2148
1917
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
1918
+
"Counter": "2",
2149
1919
"EventCode": "0xB7",
2150
1920
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2151
1921
"MSRIndex": "0x1A6",
···
2156
1924
},
2157
1925
{
2158
1926
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
1927
+
"Counter": "2",
2159
1928
"EventCode": "0xB7",
2160
1929
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2161
1930
"MSRIndex": "0x1A6",
···
2166
1933
},
2167
1934
{
2168
1935
"BriefDescription": "All offcore demand RFO requests",
1936
+
"Counter": "2",
2169
1937
"EventCode": "0xB7",
2170
1938
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2171
1939
"MSRIndex": "0x1A6",
···
2176
1942
},
2177
1943
{
2178
1944
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
1945
+
"Counter": "2",
2179
1946
"EventCode": "0xB7",
2180
1947
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2181
1948
"MSRIndex": "0x1A6",
···
2186
1951
},
2187
1952
{
2188
1953
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
1954
+
"Counter": "2",
2189
1955
"EventCode": "0xB7",
2190
1956
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2191
1957
"MSRIndex": "0x1A6",
···
2196
1960
},
2197
1961
{
2198
1962
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
1963
+
"Counter": "2",
2199
1964
"EventCode": "0xB7",
2200
1965
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2201
1966
"MSRIndex": "0x1A6",
···
2206
1969
},
2207
1970
{
2208
1971
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
1972
+
"Counter": "2",
2209
1973
"EventCode": "0xB7",
2210
1974
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2211
1975
"MSRIndex": "0x1A6",
···
2216
1978
},
2217
1979
{
2218
1980
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
1981
+
"Counter": "2",
2219
1982
"EventCode": "0xB7",
2220
1983
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2221
1984
"MSRIndex": "0x1A6",
···
2226
1987
},
2227
1988
{
2228
1989
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
1990
+
"Counter": "2",
2229
1991
"EventCode": "0xB7",
2230
1992
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
2231
1993
"MSRIndex": "0x1A6",
···
2236
1996
},
2237
1997
{
2238
1998
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
1999
+
"Counter": "2",
2239
2000
"EventCode": "0xB7",
2240
2001
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2241
2002
"MSRIndex": "0x1A6",
···
2246
2005
},
2247
2006
{
2248
2007
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
2008
+
"Counter": "2",
2249
2009
"EventCode": "0xB7",
2250
2010
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2251
2011
"MSRIndex": "0x1A6",
···
2256
2014
},
2257
2015
{
2258
2016
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
2017
+
"Counter": "2",
2259
2018
"EventCode": "0xB7",
2260
2019
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2261
2020
"MSRIndex": "0x1A6",
···
2266
2023
},
2267
2024
{
2268
2025
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
2026
+
"Counter": "2",
2269
2027
"EventCode": "0xB7",
2270
2028
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2271
2029
"MSRIndex": "0x1A6",
···
2276
2032
},
2277
2033
{
2278
2034
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
2035
+
"Counter": "2",
2279
2036
"EventCode": "0xB7",
2280
2037
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2281
2038
"MSRIndex": "0x1A6",
···
2286
2041
},
2287
2042
{
2288
2043
"BriefDescription": "All offcore other requests",
2044
+
"Counter": "2",
2289
2045
"EventCode": "0xB7",
2290
2046
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2291
2047
"MSRIndex": "0x1A6",
···
2296
2050
},
2297
2051
{
2298
2052
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2053
+
"Counter": "2",
2299
2054
"EventCode": "0xB7",
2300
2055
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2301
2056
"MSRIndex": "0x1A6",
···
2306
2059
},
2307
2060
{
2308
2061
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2062
+
"Counter": "2",
2309
2063
"EventCode": "0xB7",
2310
2064
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2311
2065
"MSRIndex": "0x1A6",
···
2316
2068
},
2317
2069
{
2318
2070
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2071
+
"Counter": "2",
2319
2072
"EventCode": "0xB7",
2320
2073
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2321
2074
"MSRIndex": "0x1A6",
···
2326
2077
},
2327
2078
{
2328
2079
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
2080
+
"Counter": "2",
2329
2081
"EventCode": "0xB7",
2330
2082
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2331
2083
"MSRIndex": "0x1A6",
···
2336
2086
},
2337
2087
{
2338
2088
"BriefDescription": "Offcore other requests satisfied by the LLC",
2089
+
"Counter": "2",
2339
2090
"EventCode": "0xB7",
2340
2091
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2341
2092
"MSRIndex": "0x1A6",
···
2346
2095
},
2347
2096
{
2348
2097
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2098
+
"Counter": "2",
2349
2099
"EventCode": "0xB7",
2350
2100
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2351
2101
"MSRIndex": "0x1A6",
···
2356
2104
},
2357
2105
{
2358
2106
"BriefDescription": "Offcore other requests satisfied by a remote cache",
2107
+
"Counter": "2",
2359
2108
"EventCode": "0xB7",
2360
2109
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2361
2110
"MSRIndex": "0x1A6",
···
2366
2113
},
2367
2114
{
2368
2115
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2116
+
"Counter": "2",
2369
2117
"EventCode": "0xB7",
2370
2118
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2371
2119
"MSRIndex": "0x1A6",
···
2376
2122
},
2377
2123
{
2378
2124
"BriefDescription": "Offcore other requests that HIT in a remote cache",
2125
+
"Counter": "2",
2379
2126
"EventCode": "0xB7",
2380
2127
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2381
2128
"MSRIndex": "0x1A6",
···
2386
2131
},
2387
2132
{
2388
2133
"BriefDescription": "Offcore other requests that HITM in a remote cache",
2134
+
"Counter": "2",
2389
2135
"EventCode": "0xB7",
2390
2136
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2391
2137
"MSRIndex": "0x1A6",
···
2396
2140
},
2397
2141
{
2398
2142
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2143
+
"Counter": "2",
2399
2144
"EventCode": "0xB7",
2400
2145
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2401
2146
"MSRIndex": "0x1A6",
···
2406
2149
},
2407
2150
{
2408
2151
"BriefDescription": "All offcore prefetch data requests",
2152
+
"Counter": "2",
2409
2153
"EventCode": "0xB7",
2410
2154
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2411
2155
"MSRIndex": "0x1A6",
···
2416
2158
},
2417
2159
{
2418
2160
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2161
+
"Counter": "2",
2419
2162
"EventCode": "0xB7",
2420
2163
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2421
2164
"MSRIndex": "0x1A6",
···
2426
2167
},
2427
2168
{
2428
2169
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2170
+
"Counter": "2",
2429
2171
"EventCode": "0xB7",
2430
2172
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2431
2173
"MSRIndex": "0x1A6",
···
2436
2176
},
2437
2177
{
2438
2178
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2179
+
"Counter": "2",
2439
2180
"EventCode": "0xB7",
2440
2181
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2441
2182
"MSRIndex": "0x1A6",
···
2446
2185
},
2447
2186
{
2448
2187
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
2188
+
"Counter": "2",
2449
2189
"EventCode": "0xB7",
2450
2190
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2451
2191
"MSRIndex": "0x1A6",
···
2456
2194
},
2457
2195
{
2458
2196
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2197
+
"Counter": "2",
2459
2198
"EventCode": "0xB7",
2460
2199
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2461
2200
"MSRIndex": "0x1A6",
···
2466
2203
},
2467
2204
{
2468
2205
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2206
+
"Counter": "2",
2469
2207
"EventCode": "0xB7",
2470
2208
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2471
2209
"MSRIndex": "0x1A6",
···
2476
2212
},
2477
2213
{
2478
2214
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2215
+
"Counter": "2",
2479
2216
"EventCode": "0xB7",
2480
2217
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2481
2218
"MSRIndex": "0x1A6",
···
2486
2221
},
2487
2222
{
2488
2223
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2224
+
"Counter": "2",
2489
2225
"EventCode": "0xB7",
2490
2226
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2491
2227
"MSRIndex": "0x1A6",
···
2496
2230
},
2497
2231
{
2498
2232
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2233
+
"Counter": "2",
2499
2234
"EventCode": "0xB7",
2500
2235
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2501
2236
"MSRIndex": "0x1A6",
···
2506
2239
},
2507
2240
{
2508
2241
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2242
+
"Counter": "2",
2509
2243
"EventCode": "0xB7",
2510
2244
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2511
2245
"MSRIndex": "0x1A6",
···
2516
2248
},
2517
2249
{
2518
2250
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2251
+
"Counter": "2",
2519
2252
"EventCode": "0xB7",
2520
2253
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2521
2254
"MSRIndex": "0x1A6",
···
2526
2257
},
2527
2258
{
2528
2259
"BriefDescription": "All offcore prefetch data reads",
2260
+
"Counter": "2",
2529
2261
"EventCode": "0xB7",
2530
2262
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2531
2263
"MSRIndex": "0x1A6",
···
2536
2266
},
2537
2267
{
2538
2268
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2269
+
"Counter": "2",
2539
2270
"EventCode": "0xB7",
2540
2271
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2541
2272
"MSRIndex": "0x1A6",
···
2546
2275
},
2547
2276
{
2548
2277
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2278
+
"Counter": "2",
2549
2279
"EventCode": "0xB7",
2550
2280
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2551
2281
"MSRIndex": "0x1A6",
···
2556
2284
},
2557
2285
{
2558
2286
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2287
+
"Counter": "2",
2559
2288
"EventCode": "0xB7",
2560
2289
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2561
2290
"MSRIndex": "0x1A6",
···
2566
2293
},
2567
2294
{
2568
2295
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
2296
+
"Counter": "2",
2569
2297
"EventCode": "0xB7",
2570
2298
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2571
2299
"MSRIndex": "0x1A6",
···
2576
2302
},
2577
2303
{
2578
2304
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2305
+
"Counter": "2",
2579
2306
"EventCode": "0xB7",
2580
2307
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2581
2308
"MSRIndex": "0x1A6",
···
2586
2311
},
2587
2312
{
2588
2313
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2314
+
"Counter": "2",
2589
2315
"EventCode": "0xB7",
2590
2316
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2591
2317
"MSRIndex": "0x1A6",
···
2596
2320
},
2597
2321
{
2598
2322
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2323
+
"Counter": "2",
2599
2324
"EventCode": "0xB7",
2600
2325
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2601
2326
"MSRIndex": "0x1A6",
···
2606
2329
},
2607
2330
{
2608
2331
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2332
+
"Counter": "2",
2609
2333
"EventCode": "0xB7",
2610
2334
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2611
2335
"MSRIndex": "0x1A6",
···
2616
2338
},
2617
2339
{
2618
2340
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2341
+
"Counter": "2",
2619
2342
"EventCode": "0xB7",
2620
2343
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2621
2344
"MSRIndex": "0x1A6",
···
2626
2347
},
2627
2348
{
2628
2349
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2350
+
"Counter": "2",
2629
2351
"EventCode": "0xB7",
2630
2352
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2631
2353
"MSRIndex": "0x1A6",
···
2636
2356
},
2637
2357
{
2638
2358
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2359
+
"Counter": "2",
2639
2360
"EventCode": "0xB7",
2640
2361
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2641
2362
"MSRIndex": "0x1A6",
···
2646
2365
},
2647
2366
{
2648
2367
"BriefDescription": "All offcore prefetch code reads",
2368
+
"Counter": "2",
2649
2369
"EventCode": "0xB7",
2650
2370
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2651
2371
"MSRIndex": "0x1A6",
···
2656
2374
},
2657
2375
{
2658
2376
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2377
+
"Counter": "2",
2659
2378
"EventCode": "0xB7",
2660
2379
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2661
2380
"MSRIndex": "0x1A6",
···
2666
2383
},
2667
2384
{
2668
2385
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2386
+
"Counter": "2",
2669
2387
"EventCode": "0xB7",
2670
2388
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2671
2389
"MSRIndex": "0x1A6",
···
2676
2392
},
2677
2393
{
2678
2394
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2395
+
"Counter": "2",
2679
2396
"EventCode": "0xB7",
2680
2397
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2681
2398
"MSRIndex": "0x1A6",
···
2686
2401
},
2687
2402
{
2688
2403
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
2404
+
"Counter": "2",
2689
2405
"EventCode": "0xB7",
2690
2406
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2691
2407
"MSRIndex": "0x1A6",
···
2696
2410
},
2697
2411
{
2698
2412
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2413
+
"Counter": "2",
2699
2414
"EventCode": "0xB7",
2700
2415
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2701
2416
"MSRIndex": "0x1A6",
···
2706
2419
},
2707
2420
{
2708
2421
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2422
+
"Counter": "2",
2709
2423
"EventCode": "0xB7",
2710
2424
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2711
2425
"MSRIndex": "0x1A6",
···
2716
2428
},
2717
2429
{
2718
2430
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2431
+
"Counter": "2",
2719
2432
"EventCode": "0xB7",
2720
2433
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2721
2434
"MSRIndex": "0x1A6",
···
2726
2437
},
2727
2438
{
2728
2439
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2440
+
"Counter": "2",
2729
2441
"EventCode": "0xB7",
2730
2442
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2731
2443
"MSRIndex": "0x1A6",
···
2736
2446
},
2737
2447
{
2738
2448
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2449
+
"Counter": "2",
2739
2450
"EventCode": "0xB7",
2740
2451
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2741
2452
"MSRIndex": "0x1A6",
···
2746
2455
},
2747
2456
{
2748
2457
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2458
+
"Counter": "2",
2749
2459
"EventCode": "0xB7",
2750
2460
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2751
2461
"MSRIndex": "0x1A6",
···
2756
2464
},
2757
2465
{
2758
2466
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2467
+
"Counter": "2",
2759
2468
"EventCode": "0xB7",
2760
2469
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2761
2470
"MSRIndex": "0x1A6",
···
2766
2473
},
2767
2474
{
2768
2475
"BriefDescription": "All offcore prefetch RFO requests",
2476
+
"Counter": "2",
2769
2477
"EventCode": "0xB7",
2770
2478
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2771
2479
"MSRIndex": "0x1A6",
···
2776
2482
},
2777
2483
{
2778
2484
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
2485
+
"Counter": "2",
2779
2486
"EventCode": "0xB7",
2780
2487
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2781
2488
"MSRIndex": "0x1A6",
···
2786
2491
},
2787
2492
{
2788
2493
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
2494
+
"Counter": "2",
2789
2495
"EventCode": "0xB7",
2790
2496
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2791
2497
"MSRIndex": "0x1A6",
···
2796
2500
},
2797
2501
{
2798
2502
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
2503
+
"Counter": "2",
2799
2504
"EventCode": "0xB7",
2800
2505
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2801
2506
"MSRIndex": "0x1A6",
···
2806
2509
},
2807
2510
{
2808
2511
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
2512
+
"Counter": "2",
2809
2513
"EventCode": "0xB7",
2810
2514
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2811
2515
"MSRIndex": "0x1A6",
···
2816
2518
},
2817
2519
{
2818
2520
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
2521
+
"Counter": "2",
2819
2522
"EventCode": "0xB7",
2820
2523
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2821
2524
"MSRIndex": "0x1A6",
···
2826
2527
},
2827
2528
{
2828
2529
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
2530
+
"Counter": "2",
2829
2531
"EventCode": "0xB7",
2830
2532
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
2831
2533
"MSRIndex": "0x1A6",
···
2836
2536
},
2837
2537
{
2838
2538
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
2539
+
"Counter": "2",
2839
2540
"EventCode": "0xB7",
2840
2541
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
2841
2542
"MSRIndex": "0x1A6",
···
2846
2545
},
2847
2546
{
2848
2547
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
2548
+
"Counter": "2",
2849
2549
"EventCode": "0xB7",
2850
2550
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
2851
2551
"MSRIndex": "0x1A6",
···
2856
2554
},
2857
2555
{
2858
2556
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
2557
+
"Counter": "2",
2859
2558
"EventCode": "0xB7",
2860
2559
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
2861
2560
"MSRIndex": "0x1A6",
···
2866
2563
},
2867
2564
{
2868
2565
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
2566
+
"Counter": "2",
2869
2567
"EventCode": "0xB7",
2870
2568
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2871
2569
"MSRIndex": "0x1A6",
···
2876
2572
},
2877
2573
{
2878
2574
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
2575
+
"Counter": "2",
2879
2576
"EventCode": "0xB7",
2880
2577
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2881
2578
"MSRIndex": "0x1A6",
···
2886
2581
},
2887
2582
{
2888
2583
"BriefDescription": "All offcore prefetch requests",
2584
+
"Counter": "2",
2889
2585
"EventCode": "0xB7",
2890
2586
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2891
2587
"MSRIndex": "0x1A6",
···
2896
2590
},
2897
2591
{
2898
2592
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
2593
+
"Counter": "2",
2899
2594
"EventCode": "0xB7",
2900
2595
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2901
2596
"MSRIndex": "0x1A6",
···
2906
2599
},
2907
2600
{
2908
2601
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
2602
+
"Counter": "2",
2909
2603
"EventCode": "0xB7",
2910
2604
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2911
2605
"MSRIndex": "0x1A6",
···
2916
2608
},
2917
2609
{
2918
2610
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
2611
+
"Counter": "2",
2919
2612
"EventCode": "0xB7",
2920
2613
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2921
2614
"MSRIndex": "0x1A6",
···
2926
2617
},
2927
2618
{
2928
2619
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
2620
+
"Counter": "2",
2929
2621
"EventCode": "0xB7",
2930
2622
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2931
2623
"MSRIndex": "0x1A6",
···
2936
2626
},
2937
2627
{
2938
2628
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
2629
+
"Counter": "2",
2939
2630
"EventCode": "0xB7",
2940
2631
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2941
2632
"MSRIndex": "0x1A6",
···
2946
2635
},
2947
2636
{
2948
2637
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
2638
+
"Counter": "2",
2949
2639
"EventCode": "0xB7",
2950
2640
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
2951
2641
"MSRIndex": "0x1A6",
···
2956
2644
},
2957
2645
{
2958
2646
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
2647
+
"Counter": "2",
2959
2648
"EventCode": "0xB7",
2960
2649
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
2961
2650
"MSRIndex": "0x1A6",
···
2966
2653
},
2967
2654
{
2968
2655
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
2656
+
"Counter": "2",
2969
2657
"EventCode": "0xB7",
2970
2658
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
2971
2659
"MSRIndex": "0x1A6",
···
2976
2662
},
2977
2663
{
2978
2664
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
2665
+
"Counter": "2",
2979
2666
"EventCode": "0xB7",
2980
2667
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
2981
2668
"MSRIndex": "0x1A6",
···
2986
2671
},
2987
2672
{
2988
2673
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
2674
+
"Counter": "2",
2989
2675
"EventCode": "0xB7",
2990
2676
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2991
2677
"MSRIndex": "0x1A6",
···
2996
2680
},
2997
2681
{
2998
2682
"BriefDescription": "Super Queue LRU hints sent to LLC",
2683
+
"Counter": "0,1,2,3",
2999
2684
"EventCode": "0xF4",
3000
2685
"EventName": "SQ_MISC.LRU_HINTS",
3001
2686
"SampleAfterValue": "2000000",
···
3004
2687
},
3005
2688
{
3006
2689
"BriefDescription": "Super Queue lock splits across a cache line",
2690
+
"Counter": "0,1,2,3",
3007
2691
"EventCode": "0xF4",
3008
2692
"EventName": "SQ_MISC.SPLIT_LOCK",
3009
2693
"SampleAfterValue": "2000000",
···
3012
2694
},
3013
2695
{
3014
2696
"BriefDescription": "Loads delayed with at-Retirement block code",
2697
+
"Counter": "0,1,2,3",
3015
2698
"EventCode": "0x6",
3016
2699
"EventName": "STORE_BLOCKS.AT_RET",
3017
2700
"SampleAfterValue": "200000",
···
3020
2701
},
3021
2702
{
3022
2703
"BriefDescription": "Cacheable loads delayed with L1D block code",
2704
+
"Counter": "0,1,2,3",
3023
2705
"EventCode": "0x6",
3024
2706
"EventName": "STORE_BLOCKS.L1D_BLOCK",
3025
2707
"SampleAfterValue": "200000",
+7
tools/perf/pmu-events/arch/x86/westmereex/counter.json
+7
tools/perf/pmu-events/arch/x86/westmereex/counter.json
+28
tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
+28
tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "X87 Floating point assists (Precise Event)",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xF7",
5
6
"EventName": "FP_ASSIST.ALL",
6
7
"PEBS": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0xF7",
14
14
"EventName": "FP_ASSIST.INPUT",
15
15
"PEBS": "1",
···
19
17
},
20
18
{
21
19
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xF7",
23
22
"EventName": "FP_ASSIST.OUTPUT",
24
23
"PEBS": "1",
···
28
25
},
29
26
{
30
27
"BriefDescription": "MMX Uops",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0x10",
32
30
"EventName": "FP_COMP_OPS_EXE.MMX",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "SSE2 integer Uops",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0x10",
40
37
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "SSE* FP double precision Uops",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0x10",
48
44
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "SSE and SSE2 FP Uops",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0x10",
56
51
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "SSE FP packed Uops",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0x10",
64
58
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "SSE FP scalar Uops",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0x10",
72
65
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "SSE* FP single precision Uops",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0x10",
80
72
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Computational floating-point operations executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x10",
88
79
"EventName": "FP_COMP_OPS_EXE.X87",
89
80
"SampleAfterValue": "2000000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "All Floating Point to and from MMX transitions",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0xCC",
96
86
"EventName": "FP_MMX_TRANS.ANY",
97
87
"SampleAfterValue": "2000000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Transitions from MMX to Floating Point instructions",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0xCC",
104
93
"EventName": "FP_MMX_TRANS.TO_FP",
105
94
"SampleAfterValue": "2000000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Transitions from Floating Point to MMX instructions",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0xCC",
112
100
"EventName": "FP_MMX_TRANS.TO_MMX",
113
101
"SampleAfterValue": "2000000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "128 bit SIMD integer pack operations",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x12",
120
107
"EventName": "SIMD_INT_128.PACK",
121
108
"SampleAfterValue": "200000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "128 bit SIMD integer arithmetic operations",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x12",
128
114
"EventName": "SIMD_INT_128.PACKED_ARITH",
129
115
"SampleAfterValue": "200000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "128 bit SIMD integer logical operations",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x12",
136
121
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
137
122
"SampleAfterValue": "200000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "128 bit SIMD integer multiply operations",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x12",
144
128
"EventName": "SIMD_INT_128.PACKED_MPY",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "128 bit SIMD integer shift operations",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x12",
152
135
"EventName": "SIMD_INT_128.PACKED_SHIFT",
153
136
"SampleAfterValue": "200000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x12",
160
142
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "128 bit SIMD integer unpack operations",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0x12",
168
149
"EventName": "SIMD_INT_128.UNPACK",
169
150
"SampleAfterValue": "200000",
···
172
151
},
173
152
{
174
153
"BriefDescription": "SIMD integer 64 bit pack operations",
154
+
"Counter": "0,1,2,3",
175
155
"EventCode": "0xFD",
176
156
"EventName": "SIMD_INT_64.PACK",
177
157
"SampleAfterValue": "200000",
···
180
158
},
181
159
{
182
160
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
161
+
"Counter": "0,1,2,3",
183
162
"EventCode": "0xFD",
184
163
"EventName": "SIMD_INT_64.PACKED_ARITH",
185
164
"SampleAfterValue": "200000",
···
188
165
},
189
166
{
190
167
"BriefDescription": "SIMD integer 64 bit logical operations",
168
+
"Counter": "0,1,2,3",
191
169
"EventCode": "0xFD",
192
170
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
193
171
"SampleAfterValue": "200000",
···
196
172
},
197
173
{
198
174
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
175
+
"Counter": "0,1,2,3",
199
176
"EventCode": "0xFD",
200
177
"EventName": "SIMD_INT_64.PACKED_MPY",
201
178
"SampleAfterValue": "200000",
···
204
179
},
205
180
{
206
181
"BriefDescription": "SIMD integer 64 bit shift operations",
182
+
"Counter": "0,1,2,3",
207
183
"EventCode": "0xFD",
208
184
"EventName": "SIMD_INT_64.PACKED_SHIFT",
209
185
"SampleAfterValue": "200000",
···
212
186
},
213
187
{
214
188
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
189
+
"Counter": "0,1,2,3",
215
190
"EventCode": "0xFD",
216
191
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
217
192
"SampleAfterValue": "200000",
···
220
193
},
221
194
{
222
195
"BriefDescription": "SIMD integer 64 bit unpack operations",
196
+
"Counter": "0,1,2,3",
223
197
"EventCode": "0xFD",
224
198
"EventName": "SIMD_INT_64.UNPACK",
225
199
"SampleAfterValue": "200000",
+3
tools/perf/pmu-events/arch/x86/westmereex/frontend.json
+3
tools/perf/pmu-events/arch/x86/westmereex/frontend.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Instructions decoded",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD0",
5
6
"EventName": "MACRO_INSTS.DECODED",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Macro-fused instructions decoded",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0xA6",
13
13
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "Two Uop instructions decoded",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x19",
21
20
"EventName": "TWO_UOP_INSTS_DECODED",
22
21
"SampleAfterValue": "2000000",
+68
tools/perf/pmu-events/arch/x86/westmereex/memory.json
+68
tools/perf/pmu-events/arch/x86/westmereex/memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Misaligned store references",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x5",
5
6
"EventName": "MISALIGN_MEM_REF.STORE",
6
7
"SampleAfterValue": "200000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Offcore data reads satisfied by any DRAM",
11
+
"Counter": "2",
12
12
"EventCode": "0xB7",
13
13
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
14
14
"MSRIndex": "0x1A6",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Offcore data reads that missed the LLC",
20
+
"Counter": "2",
22
21
"EventCode": "0xB7",
23
22
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
24
23
"MSRIndex": "0x1A6",
···
29
26
},
30
27
{
31
28
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
29
+
"Counter": "2",
32
30
"EventCode": "0xB7",
33
31
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
34
32
"MSRIndex": "0x1A6",
···
39
35
},
40
36
{
41
37
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
38
+
"Counter": "2",
42
39
"EventCode": "0xB7",
43
40
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
44
41
"MSRIndex": "0x1A6",
···
49
44
},
50
45
{
51
46
"BriefDescription": "Offcore code reads satisfied by any DRAM",
47
+
"Counter": "2",
52
48
"EventCode": "0xB7",
53
49
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
54
50
"MSRIndex": "0x1A6",
···
59
53
},
60
54
{
61
55
"BriefDescription": "Offcore code reads that missed the LLC",
56
+
"Counter": "2",
62
57
"EventCode": "0xB7",
63
58
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
64
59
"MSRIndex": "0x1A6",
···
69
62
},
70
63
{
71
64
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
65
+
"Counter": "2",
72
66
"EventCode": "0xB7",
73
67
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
74
68
"MSRIndex": "0x1A6",
···
79
71
},
80
72
{
81
73
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
74
+
"Counter": "2",
82
75
"EventCode": "0xB7",
83
76
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
84
77
"MSRIndex": "0x1A6",
···
89
80
},
90
81
{
91
82
"BriefDescription": "Offcore requests satisfied by any DRAM",
83
+
"Counter": "2",
92
84
"EventCode": "0xB7",
93
85
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
94
86
"MSRIndex": "0x1A6",
···
99
89
},
100
90
{
101
91
"BriefDescription": "Offcore requests that missed the LLC",
92
+
"Counter": "2",
102
93
"EventCode": "0xB7",
103
94
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
104
95
"MSRIndex": "0x1A6",
···
109
98
},
110
99
{
111
100
"BriefDescription": "Offcore requests satisfied by the local DRAM",
101
+
"Counter": "2",
112
102
"EventCode": "0xB7",
113
103
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
114
104
"MSRIndex": "0x1A6",
···
119
107
},
120
108
{
121
109
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
110
+
"Counter": "2",
122
111
"EventCode": "0xB7",
123
112
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
124
113
"MSRIndex": "0x1A6",
···
129
116
},
130
117
{
131
118
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
119
+
"Counter": "2",
132
120
"EventCode": "0xB7",
133
121
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
134
122
"MSRIndex": "0x1A6",
···
139
125
},
140
126
{
141
127
"BriefDescription": "Offcore RFO requests that missed the LLC",
128
+
"Counter": "2",
142
129
"EventCode": "0xB7",
143
130
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
144
131
"MSRIndex": "0x1A6",
···
149
134
},
150
135
{
151
136
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
137
+
"Counter": "2",
152
138
"EventCode": "0xB7",
153
139
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
154
140
"MSRIndex": "0x1A6",
···
159
143
},
160
144
{
161
145
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
146
+
"Counter": "2",
162
147
"EventCode": "0xB7",
163
148
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
164
149
"MSRIndex": "0x1A6",
···
169
152
},
170
153
{
171
154
"BriefDescription": "Offcore writebacks to any DRAM",
155
+
"Counter": "2",
172
156
"EventCode": "0xB7",
173
157
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
174
158
"MSRIndex": "0x1A6",
···
179
161
},
180
162
{
181
163
"BriefDescription": "Offcore writebacks that missed the LLC",
164
+
"Counter": "2",
182
165
"EventCode": "0xB7",
183
166
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
184
167
"MSRIndex": "0x1A6",
···
189
170
},
190
171
{
191
172
"BriefDescription": "Offcore writebacks to the local DRAM",
173
+
"Counter": "2",
192
174
"EventCode": "0xB7",
193
175
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
194
176
"MSRIndex": "0x1A6",
···
199
179
},
200
180
{
201
181
"BriefDescription": "Offcore writebacks to a remote DRAM",
182
+
"Counter": "2",
202
183
"EventCode": "0xB7",
203
184
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
204
185
"MSRIndex": "0x1A6",
···
209
188
},
210
189
{
211
190
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
191
+
"Counter": "2",
212
192
"EventCode": "0xB7",
213
193
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
214
194
"MSRIndex": "0x1A6",
···
219
197
},
220
198
{
221
199
"BriefDescription": "Offcore code or data read requests that missed the LLC",
200
+
"Counter": "2",
222
201
"EventCode": "0xB7",
223
202
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
224
203
"MSRIndex": "0x1A6",
···
229
206
},
230
207
{
231
208
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
209
+
"Counter": "2",
232
210
"EventCode": "0xB7",
233
211
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
234
212
"MSRIndex": "0x1A6",
···
239
215
},
240
216
{
241
217
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
218
+
"Counter": "2",
242
219
"EventCode": "0xB7",
243
220
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
244
221
"MSRIndex": "0x1A6",
···
249
224
},
250
225
{
251
226
"BriefDescription": "Offcore request = all data, response = any DRAM",
227
+
"Counter": "2",
252
228
"EventCode": "0xB7",
253
229
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
254
230
"MSRIndex": "0x1A6",
···
259
233
},
260
234
{
261
235
"BriefDescription": "Offcore request = all data, response = any LLC miss",
236
+
"Counter": "2",
262
237
"EventCode": "0xB7",
263
238
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
264
239
"MSRIndex": "0x1A6",
···
269
242
},
270
243
{
271
244
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
245
+
"Counter": "2",
272
246
"EventCode": "0xB7",
273
247
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
274
248
"MSRIndex": "0x1A6",
···
279
251
},
280
252
{
281
253
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
254
+
"Counter": "2",
282
255
"EventCode": "0xB7",
283
256
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
284
257
"MSRIndex": "0x1A6",
···
289
260
},
290
261
{
291
262
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
263
+
"Counter": "2",
292
264
"EventCode": "0xB7",
293
265
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
294
266
"MSRIndex": "0x1A6",
···
299
269
},
300
270
{
301
271
"BriefDescription": "Offcore demand data requests that missed the LLC",
272
+
"Counter": "2",
302
273
"EventCode": "0xB7",
303
274
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
304
275
"MSRIndex": "0x1A6",
···
309
278
},
310
279
{
311
280
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
281
+
"Counter": "2",
312
282
"EventCode": "0xB7",
313
283
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
314
284
"MSRIndex": "0x1A6",
···
319
287
},
320
288
{
321
289
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
290
+
"Counter": "2",
322
291
"EventCode": "0xB7",
323
292
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
324
293
"MSRIndex": "0x1A6",
···
329
296
},
330
297
{
331
298
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
299
+
"Counter": "2",
332
300
"EventCode": "0xB7",
333
301
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
334
302
"MSRIndex": "0x1A6",
···
339
305
},
340
306
{
341
307
"BriefDescription": "Offcore demand data reads that missed the LLC",
308
+
"Counter": "2",
342
309
"EventCode": "0xB7",
343
310
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
344
311
"MSRIndex": "0x1A6",
···
349
314
},
350
315
{
351
316
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
317
+
"Counter": "2",
352
318
"EventCode": "0xB7",
353
319
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
354
320
"MSRIndex": "0x1A6",
···
359
323
},
360
324
{
361
325
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
326
+
"Counter": "2",
362
327
"EventCode": "0xB7",
363
328
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
364
329
"MSRIndex": "0x1A6",
···
369
332
},
370
333
{
371
334
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
335
+
"Counter": "2",
372
336
"EventCode": "0xB7",
373
337
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
374
338
"MSRIndex": "0x1A6",
···
379
341
},
380
342
{
381
343
"BriefDescription": "Offcore demand code reads that missed the LLC",
344
+
"Counter": "2",
382
345
"EventCode": "0xB7",
383
346
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
384
347
"MSRIndex": "0x1A6",
···
389
350
},
390
351
{
391
352
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
353
+
"Counter": "2",
392
354
"EventCode": "0xB7",
393
355
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
394
356
"MSRIndex": "0x1A6",
···
399
359
},
400
360
{
401
361
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
362
+
"Counter": "2",
402
363
"EventCode": "0xB7",
403
364
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
404
365
"MSRIndex": "0x1A6",
···
409
368
},
410
369
{
411
370
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
371
+
"Counter": "2",
412
372
"EventCode": "0xB7",
413
373
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
414
374
"MSRIndex": "0x1A6",
···
419
377
},
420
378
{
421
379
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
380
+
"Counter": "2",
422
381
"EventCode": "0xB7",
423
382
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
424
383
"MSRIndex": "0x1A6",
···
429
386
},
430
387
{
431
388
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
389
+
"Counter": "2",
432
390
"EventCode": "0xB7",
433
391
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
434
392
"MSRIndex": "0x1A6",
···
439
395
},
440
396
{
441
397
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
398
+
"Counter": "2",
442
399
"EventCode": "0xB7",
443
400
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
444
401
"MSRIndex": "0x1A6",
···
449
404
},
450
405
{
451
406
"BriefDescription": "Offcore other requests satisfied by any DRAM",
407
+
"Counter": "2",
452
408
"EventCode": "0xB7",
453
409
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
454
410
"MSRIndex": "0x1A6",
···
459
413
},
460
414
{
461
415
"BriefDescription": "Offcore other requests that missed the LLC",
416
+
"Counter": "2",
462
417
"EventCode": "0xB7",
463
418
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
464
419
"MSRIndex": "0x1A6",
···
469
422
},
470
423
{
471
424
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
425
+
"Counter": "2",
472
426
"EventCode": "0xB7",
473
427
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
474
428
"MSRIndex": "0x1A6",
···
479
431
},
480
432
{
481
433
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
434
+
"Counter": "2",
482
435
"EventCode": "0xB7",
483
436
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
484
437
"MSRIndex": "0x1A6",
···
489
440
},
490
441
{
491
442
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
443
+
"Counter": "2",
492
444
"EventCode": "0xB7",
493
445
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
494
446
"MSRIndex": "0x1A6",
···
499
449
},
500
450
{
501
451
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
452
+
"Counter": "2",
502
453
"EventCode": "0xB7",
503
454
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
504
455
"MSRIndex": "0x1A6",
···
509
458
},
510
459
{
511
460
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
461
+
"Counter": "2",
512
462
"EventCode": "0xB7",
513
463
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
514
464
"MSRIndex": "0x1A6",
···
519
467
},
520
468
{
521
469
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
470
+
"Counter": "2",
522
471
"EventCode": "0xB7",
523
472
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
524
473
"MSRIndex": "0x1A6",
···
529
476
},
530
477
{
531
478
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
479
+
"Counter": "2",
532
480
"EventCode": "0xB7",
533
481
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
534
482
"MSRIndex": "0x1A6",
···
539
485
},
540
486
{
541
487
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
488
+
"Counter": "2",
542
489
"EventCode": "0xB7",
543
490
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
544
491
"MSRIndex": "0x1A6",
···
549
494
},
550
495
{
551
496
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
497
+
"Counter": "2",
552
498
"EventCode": "0xB7",
553
499
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
554
500
"MSRIndex": "0x1A6",
···
559
503
},
560
504
{
561
505
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
506
+
"Counter": "2",
562
507
"EventCode": "0xB7",
563
508
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
564
509
"MSRIndex": "0x1A6",
···
569
512
},
570
513
{
571
514
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
515
+
"Counter": "2",
572
516
"EventCode": "0xB7",
573
517
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
574
518
"MSRIndex": "0x1A6",
···
579
521
},
580
522
{
581
523
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
524
+
"Counter": "2",
582
525
"EventCode": "0xB7",
583
526
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
584
527
"MSRIndex": "0x1A6",
···
589
530
},
590
531
{
591
532
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
533
+
"Counter": "2",
592
534
"EventCode": "0xB7",
593
535
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
594
536
"MSRIndex": "0x1A6",
···
599
539
},
600
540
{
601
541
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
542
+
"Counter": "2",
602
543
"EventCode": "0xB7",
603
544
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
604
545
"MSRIndex": "0x1A6",
···
609
548
},
610
549
{
611
550
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
551
+
"Counter": "2",
612
552
"EventCode": "0xB7",
613
553
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
614
554
"MSRIndex": "0x1A6",
···
619
557
},
620
558
{
621
559
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
560
+
"Counter": "2",
622
561
"EventCode": "0xB7",
623
562
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
624
563
"MSRIndex": "0x1A6",
···
629
566
},
630
567
{
631
568
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
569
+
"Counter": "2",
632
570
"EventCode": "0xB7",
633
571
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
634
572
"MSRIndex": "0x1A6",
···
639
575
},
640
576
{
641
577
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
578
+
"Counter": "2",
642
579
"EventCode": "0xB7",
643
580
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
644
581
"MSRIndex": "0x1A6",
···
649
584
},
650
585
{
651
586
"BriefDescription": "Offcore prefetch requests that missed the LLC",
587
+
"Counter": "2",
652
588
"EventCode": "0xB7",
653
589
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
654
590
"MSRIndex": "0x1A6",
···
659
593
},
660
594
{
661
595
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
596
+
"Counter": "2",
662
597
"EventCode": "0xB7",
663
598
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
664
599
"MSRIndex": "0x1A6",
···
669
602
},
670
603
{
671
604
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
605
+
"Counter": "2",
672
606
"EventCode": "0xB7",
673
607
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
674
608
"MSRIndex": "0x1A6",
+28
tools/perf/pmu-events/arch/x86/westmereex/other.json
+28
tools/perf/pmu-events/arch/x86/westmereex/other.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "ES segment renames",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD5",
5
6
"EventName": "ES_REG_RENAMES",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "I/O transactions",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x6C",
13
13
"EventName": "IO_TRANSACTIONS",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1I instruction fetch stall cycles",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x80",
21
20
"EventName": "L1I.CYCLES_STALLED",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1I instruction fetch hits",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x80",
29
27
"EventName": "L1I.HITS",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1I instruction fetch misses",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x80",
37
34
"EventName": "L1I.MISSES",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1I Instruction fetches",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x80",
45
41
"EventName": "L1I.READS",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "Large ITLB hit",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x82",
53
48
"EventName": "LARGE_ITLB.HIT",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "Loads that partially overlap an earlier store",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0x3",
61
55
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "All loads dispatched",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x13",
69
62
"EventName": "LOAD_DISPATCH.ANY",
70
63
"SampleAfterValue": "2000000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "Loads dispatched from the MOB",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x13",
77
69
"EventName": "LOAD_DISPATCH.MOB",
78
70
"SampleAfterValue": "2000000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "Loads dispatched that bypass the MOB",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x13",
85
76
"EventName": "LOAD_DISPATCH.RS",
86
77
"SampleAfterValue": "2000000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "Loads dispatched from stage 305",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x13",
93
83
"EventName": "LOAD_DISPATCH.RS_DELAYED",
94
84
"SampleAfterValue": "2000000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "False dependencies due to partial address aliasing",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x7",
101
90
"EventName": "PARTIAL_ADDRESS_ALIAS",
102
91
"SampleAfterValue": "200000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "All Store buffer stall cycles",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0x4",
109
97
"EventName": "SB_DRAIN.ANY",
110
98
"SampleAfterValue": "200000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "Segment rename stall cycles",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0xD4",
117
104
"EventName": "SEG_RENAME_STALLS",
118
105
"SampleAfterValue": "2000000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "Snoop code requests",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0xB4",
125
111
"EventName": "SNOOPQ_REQUESTS.CODE",
126
112
"SampleAfterValue": "100000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "Snoop data requests",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0xB4",
133
118
"EventName": "SNOOPQ_REQUESTS.DATA",
134
119
"SampleAfterValue": "100000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "Snoop invalidate requests",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0xB4",
141
125
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
142
126
"SampleAfterValue": "100000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "Outstanding snoop code requests",
130
+
"Counter": "0",
148
131
"EventCode": "0xB3",
149
132
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
150
133
"SampleAfterValue": "2000000",
···
153
134
},
154
135
{
155
136
"BriefDescription": "Cycles snoop code requests queued",
137
+
"Counter": "0",
156
138
"CounterMask": "1",
157
139
"EventCode": "0xB3",
158
140
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
···
162
142
},
163
143
{
164
144
"BriefDescription": "Outstanding snoop data requests",
145
+
"Counter": "0",
165
146
"EventCode": "0xB3",
166
147
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
167
148
"SampleAfterValue": "2000000",
···
170
149
},
171
150
{
172
151
"BriefDescription": "Cycles snoop data requests queued",
152
+
"Counter": "0",
173
153
"CounterMask": "1",
174
154
"EventCode": "0xB3",
175
155
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
···
179
157
},
180
158
{
181
159
"BriefDescription": "Outstanding snoop invalidate requests",
160
+
"Counter": "0",
182
161
"EventCode": "0xB3",
183
162
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
184
163
"SampleAfterValue": "2000000",
···
187
164
},
188
165
{
189
166
"BriefDescription": "Cycles snoop invalidate requests queued",
167
+
"Counter": "0",
190
168
"CounterMask": "1",
191
169
"EventCode": "0xB3",
192
170
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
···
196
172
},
197
173
{
198
174
"BriefDescription": "Thread responded HIT to snoop",
175
+
"Counter": "0,1,2,3",
199
176
"EventCode": "0xB8",
200
177
"EventName": "SNOOP_RESPONSE.HIT",
201
178
"SampleAfterValue": "100000",
···
204
179
},
205
180
{
206
181
"BriefDescription": "Thread responded HITE to snoop",
182
+
"Counter": "0,1,2,3",
207
183
"EventCode": "0xB8",
208
184
"EventName": "SNOOP_RESPONSE.HITE",
209
185
"SampleAfterValue": "100000",
···
212
186
},
213
187
{
214
188
"BriefDescription": "Thread responded HITM to snoop",
189
+
"Counter": "0,1,2,3",
215
190
"EventCode": "0xB8",
216
191
"EventName": "SNOOP_RESPONSE.HITM",
217
192
"SampleAfterValue": "100000",
···
220
193
},
221
194
{
222
195
"BriefDescription": "Super Queue full stall cycles",
196
+
"Counter": "0,1,2,3",
223
197
"EventCode": "0xF6",
224
198
"EventName": "SQ_FULL_STALL_CYCLES",
225
199
"SampleAfterValue": "2000000",
+111
tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
+111
tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles the divider is busy",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x14",
5
6
"EventName": "ARITH.CYCLES_DIV_BUSY",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Divide Operations executed",
11
+
"Counter": "0,1,2,3",
12
12
"CounterMask": "1",
13
13
"EdgeDetect": "1",
14
14
"EventCode": "0x14",
···
20
18
},
21
19
{
22
20
"BriefDescription": "Multiply operations executed",
21
+
"Counter": "0,1,2,3",
23
22
"EventCode": "0x14",
24
23
"EventName": "ARITH.MUL",
25
24
"SampleAfterValue": "2000000",
···
28
25
},
29
26
{
30
27
"BriefDescription": "BACLEAR asserted with bad target address",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0xE6",
32
30
"EventName": "BACLEAR.BAD_TARGET",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "BACLEAR asserted, regardless of cause",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0xE6",
40
37
"EventName": "BACLEAR.CLEAR",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "Instruction queue forced BACLEAR",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0xA7",
48
44
"EventName": "BACLEAR_FORCE_IQ",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "Early Branch Prediction Unit clears",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0xE8",
56
51
"EventName": "BPU_CLEARS.EARLY",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Late Branch Prediction Unit clears",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0xE8",
64
58
"EventName": "BPU_CLEARS.LATE",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "Branch prediction unit missed call or return",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0xE5",
72
65
"EventName": "BPU_MISSED_CALL_RET",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "Branch instructions decoded",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0xE0",
80
72
"EventName": "BR_INST_DECODED",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Branch instructions executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x88",
88
79
"EventName": "BR_INST_EXEC.ANY",
89
80
"SampleAfterValue": "200000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "Conditional branch instructions executed",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0x88",
96
86
"EventName": "BR_INST_EXEC.COND",
97
87
"SampleAfterValue": "200000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Unconditional branches executed",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0x88",
104
93
"EventName": "BR_INST_EXEC.DIRECT",
105
94
"SampleAfterValue": "200000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Unconditional call branches executed",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0x88",
112
100
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
113
101
"SampleAfterValue": "20000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "Indirect call branches executed",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x88",
120
107
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
121
108
"SampleAfterValue": "20000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "Indirect non call branches executed",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x88",
128
114
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
129
115
"SampleAfterValue": "20000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "Call branches executed",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x88",
136
121
"EventName": "BR_INST_EXEC.NEAR_CALLS",
137
122
"SampleAfterValue": "20000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "All non call branches executed",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x88",
144
128
"EventName": "BR_INST_EXEC.NON_CALLS",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "Indirect return branches executed",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x88",
152
135
"EventName": "BR_INST_EXEC.RETURN_NEAR",
153
136
"SampleAfterValue": "20000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "Taken branches executed",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x88",
160
142
"EventName": "BR_INST_EXEC.TAKEN",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "Retired branch instructions (Precise Event)",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0xC4",
168
149
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
169
150
"PEBS": "1",
···
173
152
},
174
153
{
175
154
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
155
+
"Counter": "0,1,2,3",
176
156
"EventCode": "0xC4",
177
157
"EventName": "BR_INST_RETIRED.CONDITIONAL",
178
158
"PEBS": "1",
···
182
160
},
183
161
{
184
162
"BriefDescription": "Retired near call instructions (Precise Event)",
163
+
"Counter": "0,1,2,3",
185
164
"EventCode": "0xC4",
186
165
"EventName": "BR_INST_RETIRED.NEAR_CALL",
187
166
"PEBS": "1",
···
191
168
},
192
169
{
193
170
"BriefDescription": "Mispredicted branches executed",
171
+
"Counter": "0,1,2,3",
194
172
"EventCode": "0x89",
195
173
"EventName": "BR_MISP_EXEC.ANY",
196
174
"SampleAfterValue": "20000",
···
199
175
},
200
176
{
201
177
"BriefDescription": "Mispredicted conditional branches executed",
178
+
"Counter": "0,1,2,3",
202
179
"EventCode": "0x89",
203
180
"EventName": "BR_MISP_EXEC.COND",
204
181
"SampleAfterValue": "20000",
···
207
182
},
208
183
{
209
184
"BriefDescription": "Mispredicted unconditional branches executed",
185
+
"Counter": "0,1,2,3",
210
186
"EventCode": "0x89",
211
187
"EventName": "BR_MISP_EXEC.DIRECT",
212
188
"SampleAfterValue": "20000",
···
215
189
},
216
190
{
217
191
"BriefDescription": "Mispredicted non call branches executed",
192
+
"Counter": "0,1,2,3",
218
193
"EventCode": "0x89",
219
194
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
220
195
"SampleAfterValue": "2000",
···
223
196
},
224
197
{
225
198
"BriefDescription": "Mispredicted indirect call branches executed",
199
+
"Counter": "0,1,2,3",
226
200
"EventCode": "0x89",
227
201
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
228
202
"SampleAfterValue": "2000",
···
231
203
},
232
204
{
233
205
"BriefDescription": "Mispredicted indirect non call branches executed",
206
+
"Counter": "0,1,2,3",
234
207
"EventCode": "0x89",
235
208
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
236
209
"SampleAfterValue": "2000",
···
239
210
},
240
211
{
241
212
"BriefDescription": "Mispredicted call branches executed",
213
+
"Counter": "0,1,2,3",
242
214
"EventCode": "0x89",
243
215
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
244
216
"SampleAfterValue": "2000",
···
247
217
},
248
218
{
249
219
"BriefDescription": "Mispredicted non call branches executed",
220
+
"Counter": "0,1,2,3",
250
221
"EventCode": "0x89",
251
222
"EventName": "BR_MISP_EXEC.NON_CALLS",
252
223
"SampleAfterValue": "20000",
···
255
224
},
256
225
{
257
226
"BriefDescription": "Mispredicted return branches executed",
227
+
"Counter": "0,1,2,3",
258
228
"EventCode": "0x89",
259
229
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
260
230
"SampleAfterValue": "2000",
···
263
231
},
264
232
{
265
233
"BriefDescription": "Mispredicted taken branches executed",
234
+
"Counter": "0,1,2,3",
266
235
"EventCode": "0x89",
267
236
"EventName": "BR_MISP_EXEC.TAKEN",
268
237
"SampleAfterValue": "20000",
···
271
238
},
272
239
{
273
240
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
241
+
"Counter": "0,1,2,3",
274
242
"EventCode": "0xC5",
275
243
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
276
244
"PEBS": "1",
···
280
246
},
281
247
{
282
248
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
249
+
"Counter": "0,1,2,3",
283
250
"EventCode": "0xC5",
284
251
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
285
252
"PEBS": "1",
···
289
254
},
290
255
{
291
256
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
257
+
"Counter": "0,1,2,3",
292
258
"EventCode": "0xC5",
293
259
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
294
260
"PEBS": "1",
···
298
262
},
299
263
{
300
264
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
265
+
"Counter": "Fixed counter 3",
301
266
"EventName": "CPU_CLK_UNHALTED.REF",
302
267
"SampleAfterValue": "2000000"
303
268
},
304
269
{
305
270
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
271
+
"Counter": "0,1,2,3",
306
272
"EventCode": "0x3C",
307
273
"EventName": "CPU_CLK_UNHALTED.REF_P",
308
274
"SampleAfterValue": "100000",
···
312
274
},
313
275
{
314
276
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
277
+
"Counter": "Fixed counter 2",
315
278
"EventName": "CPU_CLK_UNHALTED.THREAD",
316
279
"SampleAfterValue": "2000000"
317
280
},
318
281
{
319
282
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
283
+
"Counter": "0,1,2,3",
320
284
"EventCode": "0x3C",
321
285
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
322
286
"SampleAfterValue": "2000000"
323
287
},
324
288
{
325
289
"BriefDescription": "Total CPU cycles",
290
+
"Counter": "0,1,2,3",
326
291
"CounterMask": "2",
327
292
"EventCode": "0x3C",
328
293
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
···
334
293
},
335
294
{
336
295
"BriefDescription": "Any Instruction Length Decoder stall cycles",
296
+
"Counter": "0,1,2,3",
337
297
"EventCode": "0x87",
338
298
"EventName": "ILD_STALL.ANY",
339
299
"SampleAfterValue": "2000000",
···
342
300
},
343
301
{
344
302
"BriefDescription": "Instruction Queue full stall cycles",
303
+
"Counter": "0,1,2,3",
345
304
"EventCode": "0x87",
346
305
"EventName": "ILD_STALL.IQ_FULL",
347
306
"SampleAfterValue": "2000000",
···
350
307
},
351
308
{
352
309
"BriefDescription": "Length Change Prefix stall cycles",
310
+
"Counter": "0,1,2,3",
353
311
"EventCode": "0x87",
354
312
"EventName": "ILD_STALL.LCP",
355
313
"SampleAfterValue": "2000000",
···
358
314
},
359
315
{
360
316
"BriefDescription": "Stall cycles due to BPU MRU bypass",
317
+
"Counter": "0,1,2,3",
361
318
"EventCode": "0x87",
362
319
"EventName": "ILD_STALL.MRU",
363
320
"SampleAfterValue": "2000000",
···
366
321
},
367
322
{
368
323
"BriefDescription": "Regen stall cycles",
324
+
"Counter": "0,1,2,3",
369
325
"EventCode": "0x87",
370
326
"EventName": "ILD_STALL.REGEN",
371
327
"SampleAfterValue": "2000000",
···
374
328
},
375
329
{
376
330
"BriefDescription": "Instructions that must be decoded by decoder 0",
331
+
"Counter": "0,1,2,3",
377
332
"EventCode": "0x18",
378
333
"EventName": "INST_DECODED.DEC0",
379
334
"SampleAfterValue": "2000000",
···
382
335
},
383
336
{
384
337
"BriefDescription": "Instructions written to instruction queue.",
338
+
"Counter": "0,1,2,3",
385
339
"EventCode": "0x17",
386
340
"EventName": "INST_QUEUE_WRITES",
387
341
"SampleAfterValue": "2000000",
···
390
342
},
391
343
{
392
344
"BriefDescription": "Cycles instructions are written to the instruction queue",
345
+
"Counter": "0,1,2,3",
393
346
"EventCode": "0x1E",
394
347
"EventName": "INST_QUEUE_WRITE_CYCLES",
395
348
"SampleAfterValue": "2000000",
···
398
349
},
399
350
{
400
351
"BriefDescription": "Instructions retired (fixed counter)",
352
+
"Counter": "Fixed counter 1",
401
353
"EventName": "INST_RETIRED.ANY",
402
354
"SampleAfterValue": "2000000"
403
355
},
404
356
{
405
357
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
358
+
"Counter": "0,1,2,3",
406
359
"EventCode": "0xC0",
407
360
"EventName": "INST_RETIRED.ANY_P",
408
361
"PEBS": "1",
···
413
362
},
414
363
{
415
364
"BriefDescription": "Retired MMX instructions (Precise Event)",
365
+
"Counter": "0,1,2,3",
416
366
"EventCode": "0xC0",
417
367
"EventName": "INST_RETIRED.MMX",
418
368
"PEBS": "1",
···
422
370
},
423
371
{
424
372
"BriefDescription": "Total cycles (Precise Event)",
373
+
"Counter": "0,1,2,3",
425
374
"CounterMask": "16",
426
375
"EventCode": "0xC0",
427
376
"EventName": "INST_RETIRED.TOTAL_CYCLES",
···
433
380
},
434
381
{
435
382
"BriefDescription": "Total cycles (Precise Event)",
383
+
"Counter": "0,1,2,3",
436
384
"CounterMask": "16",
437
385
"EventCode": "0xC0",
438
386
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
···
444
390
},
445
391
{
446
392
"BriefDescription": "Retired floating-point operations (Precise Event)",
393
+
"Counter": "0,1,2,3",
447
394
"EventCode": "0xC0",
448
395
"EventName": "INST_RETIRED.X87",
449
396
"PEBS": "1",
···
453
398
},
454
399
{
455
400
"BriefDescription": "Load operations conflicting with software prefetches",
401
+
"Counter": "0,1",
456
402
"EventCode": "0x4C",
457
403
"EventName": "LOAD_HIT_PRE",
458
404
"SampleAfterValue": "200000",
···
461
405
},
462
406
{
463
407
"BriefDescription": "Cycles when uops were delivered by the LSD",
408
+
"Counter": "0,1,2,3",
464
409
"CounterMask": "1",
465
410
"EventCode": "0xA8",
466
411
"EventName": "LSD.ACTIVE",
···
470
413
},
471
414
{
472
415
"BriefDescription": "Cycles no uops were delivered by the LSD",
416
+
"Counter": "0,1,2,3",
473
417
"CounterMask": "1",
474
418
"EventCode": "0xA8",
475
419
"EventName": "LSD.INACTIVE",
···
480
422
},
481
423
{
482
424
"BriefDescription": "Loops that can't stream from the instruction queue",
425
+
"Counter": "0,1,2,3",
483
426
"EventCode": "0x20",
484
427
"EventName": "LSD_OVERFLOW",
485
428
"SampleAfterValue": "2000000",
···
488
429
},
489
430
{
490
431
"BriefDescription": "Cycles machine clear asserted",
432
+
"Counter": "0,1,2,3",
491
433
"EventCode": "0xC3",
492
434
"EventName": "MACHINE_CLEARS.CYCLES",
493
435
"SampleAfterValue": "20000",
···
496
436
},
497
437
{
498
438
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
439
+
"Counter": "0,1,2,3",
499
440
"EventCode": "0xC3",
500
441
"EventName": "MACHINE_CLEARS.MEM_ORDER",
501
442
"SampleAfterValue": "20000",
···
504
443
},
505
444
{
506
445
"BriefDescription": "Self-Modifying Code detected",
446
+
"Counter": "0,1,2,3",
507
447
"EventCode": "0xC3",
508
448
"EventName": "MACHINE_CLEARS.SMC",
509
449
"SampleAfterValue": "20000",
···
512
450
},
513
451
{
514
452
"BriefDescription": "All RAT stall cycles",
453
+
"Counter": "0,1,2,3",
515
454
"EventCode": "0xD2",
516
455
"EventName": "RAT_STALLS.ANY",
517
456
"SampleAfterValue": "2000000",
···
520
457
},
521
458
{
522
459
"BriefDescription": "Flag stall cycles",
460
+
"Counter": "0,1,2,3",
523
461
"EventCode": "0xD2",
524
462
"EventName": "RAT_STALLS.FLAGS",
525
463
"SampleAfterValue": "2000000",
···
528
464
},
529
465
{
530
466
"BriefDescription": "Partial register stall cycles",
467
+
"Counter": "0,1,2,3",
531
468
"EventCode": "0xD2",
532
469
"EventName": "RAT_STALLS.REGISTERS",
533
470
"SampleAfterValue": "2000000",
···
536
471
},
537
472
{
538
473
"BriefDescription": "ROB read port stalls cycles",
474
+
"Counter": "0,1,2,3",
539
475
"EventCode": "0xD2",
540
476
"EventName": "RAT_STALLS.ROB_READ_PORT",
541
477
"SampleAfterValue": "2000000",
···
544
478
},
545
479
{
546
480
"BriefDescription": "Scoreboard stall cycles",
481
+
"Counter": "0,1,2,3",
547
482
"EventCode": "0xD2",
548
483
"EventName": "RAT_STALLS.SCOREBOARD",
549
484
"SampleAfterValue": "2000000",
···
552
485
},
553
486
{
554
487
"BriefDescription": "Resource related stall cycles",
488
+
"Counter": "0,1,2,3",
555
489
"EventCode": "0xA2",
556
490
"EventName": "RESOURCE_STALLS.ANY",
557
491
"SampleAfterValue": "2000000",
···
560
492
},
561
493
{
562
494
"BriefDescription": "FPU control word write stall cycles",
495
+
"Counter": "0,1,2,3",
563
496
"EventCode": "0xA2",
564
497
"EventName": "RESOURCE_STALLS.FPCW",
565
498
"SampleAfterValue": "2000000",
···
568
499
},
569
500
{
570
501
"BriefDescription": "Load buffer stall cycles",
502
+
"Counter": "0,1,2,3",
571
503
"EventCode": "0xA2",
572
504
"EventName": "RESOURCE_STALLS.LOAD",
573
505
"SampleAfterValue": "2000000",
···
576
506
},
577
507
{
578
508
"BriefDescription": "MXCSR rename stall cycles",
509
+
"Counter": "0,1,2,3",
579
510
"EventCode": "0xA2",
580
511
"EventName": "RESOURCE_STALLS.MXCSR",
581
512
"SampleAfterValue": "2000000",
···
584
513
},
585
514
{
586
515
"BriefDescription": "Other Resource related stall cycles",
516
+
"Counter": "0,1,2,3",
587
517
"EventCode": "0xA2",
588
518
"EventName": "RESOURCE_STALLS.OTHER",
589
519
"SampleAfterValue": "2000000",
···
592
520
},
593
521
{
594
522
"BriefDescription": "ROB full stall cycles",
523
+
"Counter": "0,1,2,3",
595
524
"EventCode": "0xA2",
596
525
"EventName": "RESOURCE_STALLS.ROB_FULL",
597
526
"SampleAfterValue": "2000000",
···
600
527
},
601
528
{
602
529
"BriefDescription": "Reservation Station full stall cycles",
530
+
"Counter": "0,1,2,3",
603
531
"EventCode": "0xA2",
604
532
"EventName": "RESOURCE_STALLS.RS_FULL",
605
533
"SampleAfterValue": "2000000",
···
608
534
},
609
535
{
610
536
"BriefDescription": "Store buffer stall cycles",
537
+
"Counter": "0,1,2,3",
611
538
"EventCode": "0xA2",
612
539
"EventName": "RESOURCE_STALLS.STORE",
613
540
"SampleAfterValue": "2000000",
···
616
541
},
617
542
{
618
543
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
544
+
"Counter": "0,1,2,3",
619
545
"EventCode": "0xC7",
620
546
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
621
547
"PEBS": "1",
···
625
549
},
626
550
{
627
551
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
552
+
"Counter": "0,1,2,3",
628
553
"EventCode": "0xC7",
629
554
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
630
555
"PEBS": "1",
···
634
557
},
635
558
{
636
559
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
560
+
"Counter": "0,1,2,3",
637
561
"EventCode": "0xC7",
638
562
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
639
563
"PEBS": "1",
···
643
565
},
644
566
{
645
567
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
568
+
"Counter": "0,1,2,3",
646
569
"EventCode": "0xC7",
647
570
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
648
571
"PEBS": "1",
···
652
573
},
653
574
{
654
575
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
576
+
"Counter": "0,1,2,3",
655
577
"EventCode": "0xC7",
656
578
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
657
579
"PEBS": "1",
···
661
581
},
662
582
{
663
583
"BriefDescription": "Stack pointer instructions decoded",
584
+
"Counter": "0,1,2,3",
664
585
"EventCode": "0xD1",
665
586
"EventName": "UOPS_DECODED.ESP_FOLDING",
666
587
"SampleAfterValue": "2000000",
···
669
588
},
670
589
{
671
590
"BriefDescription": "Stack pointer sync operations",
591
+
"Counter": "0,1,2,3",
672
592
"EventCode": "0xD1",
673
593
"EventName": "UOPS_DECODED.ESP_SYNC",
674
594
"SampleAfterValue": "2000000",
···
677
595
},
678
596
{
679
597
"BriefDescription": "Uops decoded by Microcode Sequencer",
598
+
"Counter": "0,1,2,3",
680
599
"CounterMask": "1",
681
600
"EventCode": "0xD1",
682
601
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
···
686
603
},
687
604
{
688
605
"BriefDescription": "Cycles no Uops are decoded",
606
+
"Counter": "0,1,2,3",
689
607
"CounterMask": "1",
690
608
"EventCode": "0xD1",
691
609
"EventName": "UOPS_DECODED.STALL_CYCLES",
···
697
613
{
698
614
"AnyThread": "1",
699
615
"BriefDescription": "Cycles Uops executed on any port (core count)",
616
+
"Counter": "0,1,2,3",
700
617
"CounterMask": "1",
701
618
"EventCode": "0xB1",
702
619
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
···
707
622
{
708
623
"AnyThread": "1",
709
624
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
625
+
"Counter": "0,1,2,3",
710
626
"CounterMask": "1",
711
627
"EventCode": "0xB1",
712
628
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
···
716
630
},
717
631
{
718
632
"BriefDescription": "Uops executed on any port (core count)",
633
+
"Counter": "0,1,2,3",
719
634
"CounterMask": "1",
720
635
"EdgeDetect": "1",
721
636
"EventCode": "0xB1",
···
727
640
},
728
641
{
729
642
"BriefDescription": "Uops executed on ports 0-4 (core count)",
643
+
"Counter": "0,1,2,3",
730
644
"CounterMask": "1",
731
645
"EdgeDetect": "1",
732
646
"EventCode": "0xB1",
···
739
651
{
740
652
"AnyThread": "1",
741
653
"BriefDescription": "Cycles no Uops issued on any port (core count)",
654
+
"Counter": "0,1,2,3",
742
655
"CounterMask": "1",
743
656
"EventCode": "0xB1",
744
657
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
···
750
661
{
751
662
"AnyThread": "1",
752
663
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
664
+
"Counter": "0,1,2,3",
753
665
"CounterMask": "1",
754
666
"EventCode": "0xB1",
755
667
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
···
760
670
},
761
671
{
762
672
"BriefDescription": "Uops executed on port 0",
673
+
"Counter": "0,1,2,3",
763
674
"EventCode": "0xB1",
764
675
"EventName": "UOPS_EXECUTED.PORT0",
765
676
"SampleAfterValue": "2000000",
···
768
677
},
769
678
{
770
679
"BriefDescription": "Uops issued on ports 0, 1 or 5",
680
+
"Counter": "0,1,2,3",
771
681
"EventCode": "0xB1",
772
682
"EventName": "UOPS_EXECUTED.PORT015",
773
683
"SampleAfterValue": "2000000",
···
776
684
},
777
685
{
778
686
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
687
+
"Counter": "0,1,2,3",
779
688
"CounterMask": "1",
780
689
"EventCode": "0xB1",
781
690
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
···
786
693
},
787
694
{
788
695
"BriefDescription": "Uops executed on port 1",
696
+
"Counter": "0,1,2,3",
789
697
"EventCode": "0xB1",
790
698
"EventName": "UOPS_EXECUTED.PORT1",
791
699
"SampleAfterValue": "2000000",
···
795
701
{
796
702
"AnyThread": "1",
797
703
"BriefDescription": "Uops issued on ports 2, 3 or 4",
704
+
"Counter": "0,1,2,3",
798
705
"EventCode": "0xB1",
799
706
"EventName": "UOPS_EXECUTED.PORT234_CORE",
800
707
"SampleAfterValue": "2000000",
···
804
709
{
805
710
"AnyThread": "1",
806
711
"BriefDescription": "Uops executed on port 2 (core count)",
712
+
"Counter": "0,1,2,3",
807
713
"EventCode": "0xB1",
808
714
"EventName": "UOPS_EXECUTED.PORT2_CORE",
809
715
"SampleAfterValue": "2000000",
···
813
717
{
814
718
"AnyThread": "1",
815
719
"BriefDescription": "Uops executed on port 3 (core count)",
720
+
"Counter": "0,1,2,3",
816
721
"EventCode": "0xB1",
817
722
"EventName": "UOPS_EXECUTED.PORT3_CORE",
818
723
"SampleAfterValue": "2000000",
···
822
725
{
823
726
"AnyThread": "1",
824
727
"BriefDescription": "Uops executed on port 4 (core count)",
728
+
"Counter": "0,1,2,3",
825
729
"EventCode": "0xB1",
826
730
"EventName": "UOPS_EXECUTED.PORT4_CORE",
827
731
"SampleAfterValue": "2000000",
···
830
732
},
831
733
{
832
734
"BriefDescription": "Uops executed on port 5",
735
+
"Counter": "0,1,2,3",
833
736
"EventCode": "0xB1",
834
737
"EventName": "UOPS_EXECUTED.PORT5",
835
738
"SampleAfterValue": "2000000",
···
838
739
},
839
740
{
840
741
"BriefDescription": "Uops issued",
742
+
"Counter": "0,1,2,3",
841
743
"EventCode": "0xE",
842
744
"EventName": "UOPS_ISSUED.ANY",
843
745
"SampleAfterValue": "2000000",
···
847
747
{
848
748
"AnyThread": "1",
849
749
"BriefDescription": "Cycles no Uops were issued on any thread",
750
+
"Counter": "0,1,2,3",
850
751
"CounterMask": "1",
851
752
"EventCode": "0xE",
852
753
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
···
858
757
{
859
758
"AnyThread": "1",
860
759
"BriefDescription": "Cycles Uops were issued on either thread",
760
+
"Counter": "0,1,2,3",
861
761
"CounterMask": "1",
862
762
"EventCode": "0xE",
863
763
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
···
867
765
},
868
766
{
869
767
"BriefDescription": "Fused Uops issued",
768
+
"Counter": "0,1,2,3",
870
769
"EventCode": "0xE",
871
770
"EventName": "UOPS_ISSUED.FUSED",
872
771
"SampleAfterValue": "2000000",
···
875
772
},
876
773
{
877
774
"BriefDescription": "Cycles no Uops were issued",
775
+
"Counter": "0,1,2,3",
878
776
"CounterMask": "1",
879
777
"EventCode": "0xE",
880
778
"EventName": "UOPS_ISSUED.STALL_CYCLES",
···
885
781
},
886
782
{
887
783
"BriefDescription": "Cycles Uops are being retired",
784
+
"Counter": "0,1,2,3",
888
785
"CounterMask": "1",
889
786
"EventCode": "0xC2",
890
787
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
···
895
790
},
896
791
{
897
792
"BriefDescription": "Uops retired (Precise Event)",
793
+
"Counter": "0,1,2,3",
898
794
"EventCode": "0xC2",
899
795
"EventName": "UOPS_RETIRED.ANY",
900
796
"PEBS": "1",
···
904
798
},
905
799
{
906
800
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
801
+
"Counter": "0,1,2,3",
907
802
"EventCode": "0xC2",
908
803
"EventName": "UOPS_RETIRED.MACRO_FUSED",
909
804
"PEBS": "1",
···
913
806
},
914
807
{
915
808
"BriefDescription": "Retirement slots used (Precise Event)",
809
+
"Counter": "0,1,2,3",
916
810
"EventCode": "0xC2",
917
811
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
918
812
"PEBS": "1",
···
922
814
},
923
815
{
924
816
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
817
+
"Counter": "0,1,2,3",
925
818
"CounterMask": "1",
926
819
"EventCode": "0xC2",
927
820
"EventName": "UOPS_RETIRED.STALL_CYCLES",
···
933
824
},
934
825
{
935
826
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
827
+
"Counter": "0,1,2,3",
936
828
"CounterMask": "16",
937
829
"EventCode": "0xC2",
938
830
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
···
944
834
},
945
835
{
946
836
"BriefDescription": "Uop unfusions due to FP exceptions",
837
+
"Counter": "0,1,2,3",
947
838
"EventCode": "0xDB",
948
839
"EventName": "UOP_UNFUSION",
949
840
"SampleAfterValue": "2000000",
+21
tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
+21
tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "DTLB load misses",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x8",
5
6
"EventName": "DTLB_LOAD_MISSES.ANY",
6
7
"SampleAfterValue": "200000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "DTLB load miss large page walks",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x8",
13
13
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
14
14
"SampleAfterValue": "200000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "DTLB load miss caused by low part of address",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x8",
21
20
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
22
21
"SampleAfterValue": "200000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "DTLB second level hit",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x8",
29
27
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "DTLB load miss page walks complete",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x8",
37
34
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
38
35
"SampleAfterValue": "200000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "DTLB load miss page walk cycles",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x8",
45
41
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
46
42
"SampleAfterValue": "200000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "DTLB misses",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x49",
53
48
"EventName": "DTLB_MISSES.ANY",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "DTLB miss large page walks",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0x49",
61
55
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x49",
69
62
"EventName": "DTLB_MISSES.PDE_MISS",
70
63
"SampleAfterValue": "200000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "DTLB first level misses but second level hit",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x49",
77
69
"EventName": "DTLB_MISSES.STLB_HIT",
78
70
"SampleAfterValue": "200000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "DTLB miss page walks",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x49",
85
76
"EventName": "DTLB_MISSES.WALK_COMPLETED",
86
77
"SampleAfterValue": "200000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "DTLB miss page walk cycles",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x49",
93
83
"EventName": "DTLB_MISSES.WALK_CYCLES",
94
84
"SampleAfterValue": "2000000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "Extended Page Table walk cycles",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x4F",
101
90
"EventName": "EPT.WALK_CYCLES",
102
91
"SampleAfterValue": "2000000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "ITLB flushes",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0xAE",
109
97
"EventName": "ITLB_FLUSH",
110
98
"SampleAfterValue": "2000000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "ITLB miss",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0x85",
117
104
"EventName": "ITLB_MISSES.ANY",
118
105
"SampleAfterValue": "200000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "ITLB miss large page walks",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0x85",
125
111
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
126
112
"SampleAfterValue": "200000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "ITLB miss page walks",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0x85",
133
118
"EventName": "ITLB_MISSES.WALK_COMPLETED",
134
119
"SampleAfterValue": "200000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "ITLB miss page walk cycles",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0x85",
141
125
"EventName": "ITLB_MISSES.WALK_CYCLES",
142
126
"SampleAfterValue": "2000000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
130
+
"Counter": "0,1,2,3",
148
131
"EventCode": "0xC8",
149
132
"EventName": "ITLB_MISS_RETIRED",
150
133
"PEBS": "1",
···
154
135
},
155
136
{
156
137
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
138
+
"Counter": "0,1,2,3",
157
139
"EventCode": "0xCB",
158
140
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
159
141
"PEBS": "1",
···
163
143
},
164
144
{
165
145
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
146
+
"Counter": "0,1,2,3",
166
147
"EventCode": "0xC",
167
148
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
168
149
"PEBS": "1",