Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events: Add westmereep-sp counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-37-irogers@google.com
authored by
Ian Rogers
Weilin Wang
Caleb Biggers
and committed by
Namhyung Kim
dc5f18a1
22123c26
+583
+321
tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
+321
tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles L1D locked",
4
+
"Counter": "0,1",
4
5
"EventCode": "0x63",
5
6
"EventName": "CACHE_LOCK_CYCLES.L1D",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Cycles L1D and L2 locked",
11
+
"Counter": "0,1",
12
12
"EventCode": "0x63",
13
13
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1D cache lines replaced in M state",
18
+
"Counter": "0,1",
20
19
"EventCode": "0x51",
21
20
"EventName": "L1D.M_EVICT",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1D cache lines allocated in the M state",
25
+
"Counter": "0,1",
28
26
"EventCode": "0x51",
29
27
"EventName": "L1D.M_REPL",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1D snoop eviction of cache lines in M state",
32
+
"Counter": "0,1",
36
33
"EventCode": "0x51",
37
34
"EventName": "L1D.M_SNOOP_EVICT",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1 data cache lines allocated",
39
+
"Counter": "0,1",
44
40
"EventCode": "0x51",
45
41
"EventName": "L1D.REPL",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
46
+
"Counter": "0,1",
52
47
"EventCode": "0x52",
53
48
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
54
49
"SampleAfterValue": "2000000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "L1D hardware prefetch misses",
53
+
"Counter": "0,1",
60
54
"EventCode": "0x4E",
61
55
"EventName": "L1D_PREFETCH.MISS",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "L1D hardware prefetch requests",
60
+
"Counter": "0,1",
68
61
"EventCode": "0x4E",
69
62
"EventName": "L1D_PREFETCH.REQUESTS",
70
63
"SampleAfterValue": "200000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "L1D hardware prefetch requests triggered",
67
+
"Counter": "0,1",
76
68
"EventCode": "0x4E",
77
69
"EventName": "L1D_PREFETCH.TRIGGERS",
78
70
"SampleAfterValue": "200000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "L1 writebacks to L2 in E state",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x28",
85
76
"EventName": "L1D_WB_L2.E_STATE",
86
77
"SampleAfterValue": "100000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x28",
93
83
"EventName": "L1D_WB_L2.I_STATE",
94
84
"SampleAfterValue": "100000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "All L1 writebacks to L2",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x28",
101
90
"EventName": "L1D_WB_L2.MESI",
102
91
"SampleAfterValue": "100000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "L1 writebacks to L2 in M state",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0x28",
109
97
"EventName": "L1D_WB_L2.M_STATE",
110
98
"SampleAfterValue": "100000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "L1 writebacks to L2 in S state",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0x28",
117
104
"EventName": "L1D_WB_L2.S_STATE",
118
105
"SampleAfterValue": "100000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "All L2 data requests",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0x26",
125
111
"EventName": "L2_DATA_RQSTS.ANY",
126
112
"SampleAfterValue": "200000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "L2 data demand loads in E state",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0x26",
133
118
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
134
119
"SampleAfterValue": "200000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "L2 data demand loads in I state (misses)",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0x26",
141
125
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
142
126
"SampleAfterValue": "200000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "L2 data demand requests",
130
+
"Counter": "0,1,2,3",
148
131
"EventCode": "0x26",
149
132
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
150
133
"SampleAfterValue": "200000",
···
153
134
},
154
135
{
155
136
"BriefDescription": "L2 data demand loads in M state",
137
+
"Counter": "0,1,2,3",
156
138
"EventCode": "0x26",
157
139
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
158
140
"SampleAfterValue": "200000",
···
161
141
},
162
142
{
163
143
"BriefDescription": "L2 data demand loads in S state",
144
+
"Counter": "0,1,2,3",
164
145
"EventCode": "0x26",
165
146
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
166
147
"SampleAfterValue": "200000",
···
169
148
},
170
149
{
171
150
"BriefDescription": "L2 data prefetches in E state",
151
+
"Counter": "0,1,2,3",
172
152
"EventCode": "0x26",
173
153
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
174
154
"SampleAfterValue": "200000",
···
177
155
},
178
156
{
179
157
"BriefDescription": "L2 data prefetches in the I state (misses)",
158
+
"Counter": "0,1,2,3",
180
159
"EventCode": "0x26",
181
160
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
182
161
"SampleAfterValue": "200000",
···
185
162
},
186
163
{
187
164
"BriefDescription": "All L2 data prefetches",
165
+
"Counter": "0,1,2,3",
188
166
"EventCode": "0x26",
189
167
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
190
168
"SampleAfterValue": "200000",
···
193
169
},
194
170
{
195
171
"BriefDescription": "L2 data prefetches in M state",
172
+
"Counter": "0,1,2,3",
196
173
"EventCode": "0x26",
197
174
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
198
175
"SampleAfterValue": "200000",
···
201
176
},
202
177
{
203
178
"BriefDescription": "L2 data prefetches in the S state",
179
+
"Counter": "0,1,2,3",
204
180
"EventCode": "0x26",
205
181
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
206
182
"SampleAfterValue": "200000",
···
209
183
},
210
184
{
211
185
"BriefDescription": "L2 lines allocated",
186
+
"Counter": "0,1,2,3",
212
187
"EventCode": "0xF1",
213
188
"EventName": "L2_LINES_IN.ANY",
214
189
"SampleAfterValue": "100000",
···
217
190
},
218
191
{
219
192
"BriefDescription": "L2 lines allocated in the E state",
193
+
"Counter": "0,1,2,3",
220
194
"EventCode": "0xF1",
221
195
"EventName": "L2_LINES_IN.E_STATE",
222
196
"SampleAfterValue": "100000",
···
225
197
},
226
198
{
227
199
"BriefDescription": "L2 lines allocated in the S state",
200
+
"Counter": "0,1,2,3",
228
201
"EventCode": "0xF1",
229
202
"EventName": "L2_LINES_IN.S_STATE",
230
203
"SampleAfterValue": "100000",
···
233
204
},
234
205
{
235
206
"BriefDescription": "L2 lines evicted",
207
+
"Counter": "0,1,2,3",
236
208
"EventCode": "0xF2",
237
209
"EventName": "L2_LINES_OUT.ANY",
238
210
"SampleAfterValue": "100000",
···
241
211
},
242
212
{
243
213
"BriefDescription": "L2 lines evicted by a demand request",
214
+
"Counter": "0,1,2,3",
244
215
"EventCode": "0xF2",
245
216
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
246
217
"SampleAfterValue": "100000",
···
249
218
},
250
219
{
251
220
"BriefDescription": "L2 modified lines evicted by a demand request",
221
+
"Counter": "0,1,2,3",
252
222
"EventCode": "0xF2",
253
223
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
254
224
"SampleAfterValue": "100000",
···
257
225
},
258
226
{
259
227
"BriefDescription": "L2 lines evicted by a prefetch request",
228
+
"Counter": "0,1,2,3",
260
229
"EventCode": "0xF2",
261
230
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
262
231
"SampleAfterValue": "100000",
···
265
232
},
266
233
{
267
234
"BriefDescription": "L2 modified lines evicted by a prefetch request",
235
+
"Counter": "0,1,2,3",
268
236
"EventCode": "0xF2",
269
237
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
270
238
"SampleAfterValue": "100000",
···
273
239
},
274
240
{
275
241
"BriefDescription": "L2 instruction fetches",
242
+
"Counter": "0,1,2,3",
276
243
"EventCode": "0x24",
277
244
"EventName": "L2_RQSTS.IFETCHES",
278
245
"SampleAfterValue": "200000",
···
281
246
},
282
247
{
283
248
"BriefDescription": "L2 instruction fetch hits",
249
+
"Counter": "0,1,2,3",
284
250
"EventCode": "0x24",
285
251
"EventName": "L2_RQSTS.IFETCH_HIT",
286
252
"SampleAfterValue": "200000",
···
289
253
},
290
254
{
291
255
"BriefDescription": "L2 instruction fetch misses",
256
+
"Counter": "0,1,2,3",
292
257
"EventCode": "0x24",
293
258
"EventName": "L2_RQSTS.IFETCH_MISS",
294
259
"SampleAfterValue": "200000",
···
297
260
},
298
261
{
299
262
"BriefDescription": "L2 load hits",
263
+
"Counter": "0,1,2,3",
300
264
"EventCode": "0x24",
301
265
"EventName": "L2_RQSTS.LD_HIT",
302
266
"SampleAfterValue": "200000",
···
305
267
},
306
268
{
307
269
"BriefDescription": "L2 load misses",
270
+
"Counter": "0,1,2,3",
308
271
"EventCode": "0x24",
309
272
"EventName": "L2_RQSTS.LD_MISS",
310
273
"SampleAfterValue": "200000",
···
313
274
},
314
275
{
315
276
"BriefDescription": "L2 requests",
277
+
"Counter": "0,1,2,3",
316
278
"EventCode": "0x24",
317
279
"EventName": "L2_RQSTS.LOADS",
318
280
"SampleAfterValue": "200000",
···
321
281
},
322
282
{
323
283
"BriefDescription": "All L2 misses",
284
+
"Counter": "0,1,2,3",
324
285
"EventCode": "0x24",
325
286
"EventName": "L2_RQSTS.MISS",
326
287
"SampleAfterValue": "200000",
···
329
288
},
330
289
{
331
290
"BriefDescription": "All L2 prefetches",
291
+
"Counter": "0,1,2,3",
332
292
"EventCode": "0x24",
333
293
"EventName": "L2_RQSTS.PREFETCHES",
334
294
"SampleAfterValue": "200000",
···
337
295
},
338
296
{
339
297
"BriefDescription": "L2 prefetch hits",
298
+
"Counter": "0,1,2,3",
340
299
"EventCode": "0x24",
341
300
"EventName": "L2_RQSTS.PREFETCH_HIT",
342
301
"SampleAfterValue": "200000",
···
345
302
},
346
303
{
347
304
"BriefDescription": "L2 prefetch misses",
305
+
"Counter": "0,1,2,3",
348
306
"EventCode": "0x24",
349
307
"EventName": "L2_RQSTS.PREFETCH_MISS",
350
308
"SampleAfterValue": "200000",
···
353
309
},
354
310
{
355
311
"BriefDescription": "All L2 requests",
312
+
"Counter": "0,1,2,3",
356
313
"EventCode": "0x24",
357
314
"EventName": "L2_RQSTS.REFERENCES",
358
315
"SampleAfterValue": "200000",
···
361
316
},
362
317
{
363
318
"BriefDescription": "L2 RFO requests",
319
+
"Counter": "0,1,2,3",
364
320
"EventCode": "0x24",
365
321
"EventName": "L2_RQSTS.RFOS",
366
322
"SampleAfterValue": "200000",
···
369
323
},
370
324
{
371
325
"BriefDescription": "L2 RFO hits",
326
+
"Counter": "0,1,2,3",
372
327
"EventCode": "0x24",
373
328
"EventName": "L2_RQSTS.RFO_HIT",
374
329
"SampleAfterValue": "200000",
···
377
330
},
378
331
{
379
332
"BriefDescription": "L2 RFO misses",
333
+
"Counter": "0,1,2,3",
380
334
"EventCode": "0x24",
381
335
"EventName": "L2_RQSTS.RFO_MISS",
382
336
"SampleAfterValue": "200000",
···
385
337
},
386
338
{
387
339
"BriefDescription": "All L2 transactions",
340
+
"Counter": "0,1,2,3",
388
341
"EventCode": "0xF0",
389
342
"EventName": "L2_TRANSACTIONS.ANY",
390
343
"SampleAfterValue": "200000",
···
393
344
},
394
345
{
395
346
"BriefDescription": "L2 fill transactions",
347
+
"Counter": "0,1,2,3",
396
348
"EventCode": "0xF0",
397
349
"EventName": "L2_TRANSACTIONS.FILL",
398
350
"SampleAfterValue": "200000",
···
401
351
},
402
352
{
403
353
"BriefDescription": "L2 instruction fetch transactions",
354
+
"Counter": "0,1,2,3",
404
355
"EventCode": "0xF0",
405
356
"EventName": "L2_TRANSACTIONS.IFETCH",
406
357
"SampleAfterValue": "200000",
···
409
358
},
410
359
{
411
360
"BriefDescription": "L1D writeback to L2 transactions",
361
+
"Counter": "0,1,2,3",
412
362
"EventCode": "0xF0",
413
363
"EventName": "L2_TRANSACTIONS.L1D_WB",
414
364
"SampleAfterValue": "200000",
···
417
365
},
418
366
{
419
367
"BriefDescription": "L2 Load transactions",
368
+
"Counter": "0,1,2,3",
420
369
"EventCode": "0xF0",
421
370
"EventName": "L2_TRANSACTIONS.LOAD",
422
371
"SampleAfterValue": "200000",
···
425
372
},
426
373
{
427
374
"BriefDescription": "L2 prefetch transactions",
375
+
"Counter": "0,1,2,3",
428
376
"EventCode": "0xF0",
429
377
"EventName": "L2_TRANSACTIONS.PREFETCH",
430
378
"SampleAfterValue": "200000",
···
433
379
},
434
380
{
435
381
"BriefDescription": "L2 RFO transactions",
382
+
"Counter": "0,1,2,3",
436
383
"EventCode": "0xF0",
437
384
"EventName": "L2_TRANSACTIONS.RFO",
438
385
"SampleAfterValue": "200000",
···
441
386
},
442
387
{
443
388
"BriefDescription": "L2 writeback to LLC transactions",
389
+
"Counter": "0,1,2,3",
444
390
"EventCode": "0xF0",
445
391
"EventName": "L2_TRANSACTIONS.WB",
446
392
"SampleAfterValue": "200000",
···
449
393
},
450
394
{
451
395
"BriefDescription": "L2 demand lock RFOs in E state",
396
+
"Counter": "0,1,2,3",
452
397
"EventCode": "0x27",
453
398
"EventName": "L2_WRITE.LOCK.E_STATE",
454
399
"SampleAfterValue": "100000",
···
457
400
},
458
401
{
459
402
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
403
+
"Counter": "0,1,2,3",
460
404
"EventCode": "0x27",
461
405
"EventName": "L2_WRITE.LOCK.HIT",
462
406
"SampleAfterValue": "100000",
···
465
407
},
466
408
{
467
409
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
410
+
"Counter": "0,1,2,3",
468
411
"EventCode": "0x27",
469
412
"EventName": "L2_WRITE.LOCK.I_STATE",
470
413
"SampleAfterValue": "100000",
···
473
414
},
474
415
{
475
416
"BriefDescription": "All demand L2 lock RFOs",
417
+
"Counter": "0,1,2,3",
476
418
"EventCode": "0x27",
477
419
"EventName": "L2_WRITE.LOCK.MESI",
478
420
"SampleAfterValue": "100000",
···
481
421
},
482
422
{
483
423
"BriefDescription": "L2 demand lock RFOs in M state",
424
+
"Counter": "0,1,2,3",
484
425
"EventCode": "0x27",
485
426
"EventName": "L2_WRITE.LOCK.M_STATE",
486
427
"SampleAfterValue": "100000",
···
489
428
},
490
429
{
491
430
"BriefDescription": "L2 demand lock RFOs in S state",
431
+
"Counter": "0,1,2,3",
492
432
"EventCode": "0x27",
493
433
"EventName": "L2_WRITE.LOCK.S_STATE",
494
434
"SampleAfterValue": "100000",
···
497
435
},
498
436
{
499
437
"BriefDescription": "All L2 demand store RFOs that hit the cache",
438
+
"Counter": "0,1,2,3",
500
439
"EventCode": "0x27",
501
440
"EventName": "L2_WRITE.RFO.HIT",
502
441
"SampleAfterValue": "100000",
···
505
442
},
506
443
{
507
444
"BriefDescription": "L2 demand store RFOs in I state (misses)",
445
+
"Counter": "0,1,2,3",
508
446
"EventCode": "0x27",
509
447
"EventName": "L2_WRITE.RFO.I_STATE",
510
448
"SampleAfterValue": "100000",
···
513
449
},
514
450
{
515
451
"BriefDescription": "All L2 demand store RFOs",
452
+
"Counter": "0,1,2,3",
516
453
"EventCode": "0x27",
517
454
"EventName": "L2_WRITE.RFO.MESI",
518
455
"SampleAfterValue": "100000",
···
521
456
},
522
457
{
523
458
"BriefDescription": "L2 demand store RFOs in M state",
459
+
"Counter": "0,1,2,3",
524
460
"EventCode": "0x27",
525
461
"EventName": "L2_WRITE.RFO.M_STATE",
526
462
"SampleAfterValue": "100000",
···
529
463
},
530
464
{
531
465
"BriefDescription": "L2 demand store RFOs in S state",
466
+
"Counter": "0,1,2,3",
532
467
"EventCode": "0x27",
533
468
"EventName": "L2_WRITE.RFO.S_STATE",
534
469
"SampleAfterValue": "100000",
···
537
470
},
538
471
{
539
472
"BriefDescription": "Longest latency cache miss",
473
+
"Counter": "0,1,2,3",
540
474
"EventCode": "0x2E",
541
475
"EventName": "LONGEST_LAT_CACHE.MISS",
542
476
"SampleAfterValue": "100000",
···
545
477
},
546
478
{
547
479
"BriefDescription": "Longest latency cache reference",
480
+
"Counter": "0,1,2,3",
548
481
"EventCode": "0x2E",
549
482
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
550
483
"SampleAfterValue": "200000",
···
553
484
},
554
485
{
555
486
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
487
+
"Counter": "3",
556
488
"EventCode": "0xB",
557
489
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
558
490
"MSRIndex": "0x3F6",
···
563
493
},
564
494
{
565
495
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
496
+
"Counter": "3",
566
497
"EventCode": "0xB",
567
498
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
568
499
"MSRIndex": "0x3F6",
···
574
503
},
575
504
{
576
505
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
506
+
"Counter": "3",
577
507
"EventCode": "0xB",
578
508
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
579
509
"MSRIndex": "0x3F6",
···
585
513
},
586
514
{
587
515
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
516
+
"Counter": "3",
588
517
"EventCode": "0xB",
589
518
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
590
519
"MSRIndex": "0x3F6",
···
596
523
},
597
524
{
598
525
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
526
+
"Counter": "3",
599
527
"EventCode": "0xB",
600
528
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
601
529
"MSRIndex": "0x3F6",
···
607
533
},
608
534
{
609
535
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
536
+
"Counter": "3",
610
537
"EventCode": "0xB",
611
538
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
612
539
"MSRIndex": "0x3F6",
···
618
543
},
619
544
{
620
545
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
546
+
"Counter": "3",
621
547
"EventCode": "0xB",
622
548
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
623
549
"MSRIndex": "0x3F6",
···
629
553
},
630
554
{
631
555
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
556
+
"Counter": "3",
632
557
"EventCode": "0xB",
633
558
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
634
559
"MSRIndex": "0x3F6",
···
640
563
},
641
564
{
642
565
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
566
+
"Counter": "3",
643
567
"EventCode": "0xB",
644
568
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
645
569
"MSRIndex": "0x3F6",
···
651
573
},
652
574
{
653
575
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
576
+
"Counter": "3",
654
577
"EventCode": "0xB",
655
578
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
656
579
"MSRIndex": "0x3F6",
···
662
583
},
663
584
{
664
585
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
586
+
"Counter": "3",
665
587
"EventCode": "0xB",
666
588
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
667
589
"MSRIndex": "0x3F6",
···
673
593
},
674
594
{
675
595
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
596
+
"Counter": "3",
676
597
"EventCode": "0xB",
677
598
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
678
599
"MSRIndex": "0x3F6",
···
684
603
},
685
604
{
686
605
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
606
+
"Counter": "3",
687
607
"EventCode": "0xB",
688
608
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
689
609
"MSRIndex": "0x3F6",
···
695
613
},
696
614
{
697
615
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
616
+
"Counter": "3",
698
617
"EventCode": "0xB",
699
618
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
700
619
"MSRIndex": "0x3F6",
···
706
623
},
707
624
{
708
625
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
626
+
"Counter": "3",
709
627
"EventCode": "0xB",
710
628
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
711
629
"MSRIndex": "0x3F6",
···
717
633
},
718
634
{
719
635
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
636
+
"Counter": "0,1,2,3",
720
637
"EventCode": "0xB",
721
638
"EventName": "MEM_INST_RETIRED.LOADS",
722
639
"PEBS": "1",
···
726
641
},
727
642
{
728
643
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
644
+
"Counter": "0,1,2,3",
729
645
"EventCode": "0xB",
730
646
"EventName": "MEM_INST_RETIRED.STORES",
731
647
"PEBS": "1",
···
735
649
},
736
650
{
737
651
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
652
+
"Counter": "0,1,2,3",
738
653
"EventCode": "0xCB",
739
654
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
740
655
"PEBS": "1",
···
744
657
},
745
658
{
746
659
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
660
+
"Counter": "0,1,2,3",
747
661
"EventCode": "0xCB",
748
662
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
749
663
"PEBS": "1",
···
753
665
},
754
666
{
755
667
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
668
+
"Counter": "0,1,2,3",
756
669
"EventCode": "0xCB",
757
670
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
758
671
"PEBS": "1",
···
762
673
},
763
674
{
764
675
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
676
+
"Counter": "0,1,2,3",
765
677
"EventCode": "0xCB",
766
678
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
767
679
"PEBS": "1",
···
771
681
},
772
682
{
773
683
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
684
+
"Counter": "0,1,2,3",
774
685
"EventCode": "0xCB",
775
686
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
776
687
"PEBS": "1",
···
780
689
},
781
690
{
782
691
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
692
+
"Counter": "0,1,2,3",
783
693
"EventCode": "0xCB",
784
694
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
785
695
"PEBS": "1",
···
789
697
},
790
698
{
791
699
"BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
700
+
"Counter": "0,1,2,3",
792
701
"EventCode": "0xF",
793
702
"EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
794
703
"PEBS": "1",
···
798
705
},
799
706
{
800
707
"BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
708
+
"Counter": "0,1,2,3",
801
709
"EventCode": "0xF",
802
710
"EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
803
711
"PEBS": "1",
···
807
713
},
808
714
{
809
715
"BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
716
+
"Counter": "0,1,2,3",
810
717
"EventCode": "0xF",
811
718
"EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
812
719
"PEBS": "1",
···
816
721
},
817
722
{
818
723
"BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
724
+
"Counter": "0,1,2,3",
819
725
"EventCode": "0xF",
820
726
"EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
821
727
"PEBS": "1",
···
825
729
},
826
730
{
827
731
"BriefDescription": "Load instructions retired IO (Precise Event)",
732
+
"Counter": "0,1,2,3",
828
733
"EventCode": "0xF",
829
734
"EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
830
735
"PEBS": "1",
···
834
737
},
835
738
{
836
739
"BriefDescription": "All offcore requests",
740
+
"Counter": "0,1,2,3",
837
741
"EventCode": "0xB0",
838
742
"EventName": "OFFCORE_REQUESTS.ANY",
839
743
"SampleAfterValue": "100000",
···
842
744
},
843
745
{
844
746
"BriefDescription": "Offcore read requests",
747
+
"Counter": "0,1,2,3",
845
748
"EventCode": "0xB0",
846
749
"EventName": "OFFCORE_REQUESTS.ANY.READ",
847
750
"SampleAfterValue": "100000",
···
850
751
},
851
752
{
852
753
"BriefDescription": "Offcore RFO requests",
754
+
"Counter": "0,1,2,3",
853
755
"EventCode": "0xB0",
854
756
"EventName": "OFFCORE_REQUESTS.ANY.RFO",
855
757
"SampleAfterValue": "100000",
···
858
758
},
859
759
{
860
760
"BriefDescription": "Offcore demand code read requests",
761
+
"Counter": "0,1,2,3",
861
762
"EventCode": "0xB0",
862
763
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
863
764
"SampleAfterValue": "100000",
···
866
765
},
867
766
{
868
767
"BriefDescription": "Offcore demand data read requests",
768
+
"Counter": "0,1,2,3",
869
769
"EventCode": "0xB0",
870
770
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
871
771
"SampleAfterValue": "100000",
···
874
772
},
875
773
{
876
774
"BriefDescription": "Offcore demand RFO requests",
775
+
"Counter": "0,1,2,3",
877
776
"EventCode": "0xB0",
878
777
"EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
879
778
"SampleAfterValue": "100000",
···
882
779
},
883
780
{
884
781
"BriefDescription": "Offcore L1 data cache writebacks",
782
+
"Counter": "0,1,2,3",
885
783
"EventCode": "0xB0",
886
784
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
887
785
"SampleAfterValue": "100000",
···
890
786
},
891
787
{
892
788
"BriefDescription": "Offcore uncached memory accesses",
789
+
"Counter": "0,1,2,3",
893
790
"EventCode": "0xB0",
894
791
"EventName": "OFFCORE_REQUESTS.UNCACHED_MEM",
895
792
"SampleAfterValue": "100000",
···
898
793
},
899
794
{
900
795
"BriefDescription": "Outstanding offcore reads",
796
+
"Counter": "0",
901
797
"EventCode": "0x60",
902
798
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
903
799
"SampleAfterValue": "2000000",
···
906
800
},
907
801
{
908
802
"BriefDescription": "Cycles offcore reads busy",
803
+
"Counter": "0",
909
804
"CounterMask": "1",
910
805
"EventCode": "0x60",
911
806
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
···
915
808
},
916
809
{
917
810
"BriefDescription": "Outstanding offcore demand code reads",
811
+
"Counter": "0",
918
812
"EventCode": "0x60",
919
813
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
920
814
"SampleAfterValue": "2000000",
···
923
815
},
924
816
{
925
817
"BriefDescription": "Cycles offcore demand code read busy",
818
+
"Counter": "0",
926
819
"CounterMask": "1",
927
820
"EventCode": "0x60",
928
821
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
···
932
823
},
933
824
{
934
825
"BriefDescription": "Outstanding offcore demand data reads",
826
+
"Counter": "0",
935
827
"EventCode": "0x60",
936
828
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
937
829
"SampleAfterValue": "2000000",
···
940
830
},
941
831
{
942
832
"BriefDescription": "Cycles offcore demand data read busy",
833
+
"Counter": "0",
943
834
"CounterMask": "1",
944
835
"EventCode": "0x60",
945
836
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
···
949
838
},
950
839
{
951
840
"BriefDescription": "Outstanding offcore demand RFOs",
841
+
"Counter": "0",
952
842
"EventCode": "0x60",
953
843
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
954
844
"SampleAfterValue": "2000000",
···
957
845
},
958
846
{
959
847
"BriefDescription": "Cycles offcore demand RFOs busy",
848
+
"Counter": "0",
960
849
"CounterMask": "1",
961
850
"EventCode": "0x60",
962
851
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
···
966
853
},
967
854
{
968
855
"BriefDescription": "Offcore requests blocked due to Super Queue full",
856
+
"Counter": "0,1,2,3",
969
857
"EventCode": "0xB2",
970
858
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
971
859
"SampleAfterValue": "100000",
···
974
860
},
975
861
{
976
862
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
863
+
"Counter": "0,1,2,3",
977
864
"EventCode": "0xB7, 0xBB",
978
865
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
979
866
"MSRIndex": "0x1a6,0x1a7",
···
984
869
},
985
870
{
986
871
"BriefDescription": "All offcore data reads",
872
+
"Counter": "0,1,2,3",
987
873
"EventCode": "0xB7, 0xBB",
988
874
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
989
875
"MSRIndex": "0x1a6,0x1a7",
···
994
878
},
995
879
{
996
880
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
881
+
"Counter": "0,1,2,3",
997
882
"EventCode": "0xB7, 0xBB",
998
883
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
999
884
"MSRIndex": "0x1a6,0x1a7",
···
1004
887
},
1005
888
{
1006
889
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
890
+
"Counter": "0,1,2,3",
1007
891
"EventCode": "0xB7, 0xBB",
1008
892
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
1009
893
"MSRIndex": "0x1a6,0x1a7",
···
1014
896
},
1015
897
{
1016
898
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
899
+
"Counter": "0,1,2,3",
1017
900
"EventCode": "0xB7, 0xBB",
1018
901
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
1019
902
"MSRIndex": "0x1a6,0x1a7",
···
1024
905
},
1025
906
{
1026
907
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
908
+
"Counter": "0,1,2,3",
1027
909
"EventCode": "0xB7, 0xBB",
1028
910
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
1029
911
"MSRIndex": "0x1a6,0x1a7",
···
1034
914
},
1035
915
{
1036
916
"BriefDescription": "Offcore data reads satisfied by the LLC",
917
+
"Counter": "0,1,2,3",
1037
918
"EventCode": "0xB7, 0xBB",
1038
919
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
1039
920
"MSRIndex": "0x1a6,0x1a7",
···
1044
923
},
1045
924
{
1046
925
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
926
+
"Counter": "0,1,2,3",
1047
927
"EventCode": "0xB7, 0xBB",
1048
928
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
1049
929
"MSRIndex": "0x1a6,0x1a7",
···
1054
932
},
1055
933
{
1056
934
"BriefDescription": "Offcore data reads satisfied by a remote cache",
935
+
"Counter": "0,1,2,3",
1057
936
"EventCode": "0xB7, 0xBB",
1058
937
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
1059
938
"MSRIndex": "0x1a6,0x1a7",
···
1064
941
},
1065
942
{
1066
943
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
944
+
"Counter": "0,1,2,3",
1067
945
"EventCode": "0xB7, 0xBB",
1068
946
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
1069
947
"MSRIndex": "0x1a6,0x1a7",
···
1074
950
},
1075
951
{
1076
952
"BriefDescription": "Offcore data reads that HIT in a remote cache",
953
+
"Counter": "0,1,2,3",
1077
954
"EventCode": "0xB7, 0xBB",
1078
955
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
1079
956
"MSRIndex": "0x1a6,0x1a7",
···
1084
959
},
1085
960
{
1086
961
"BriefDescription": "Offcore data reads that HITM in a remote cache",
962
+
"Counter": "0,1,2,3",
1087
963
"EventCode": "0xB7, 0xBB",
1088
964
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1089
965
"MSRIndex": "0x1a6,0x1a7",
···
1094
968
},
1095
969
{
1096
970
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
971
+
"Counter": "0,1,2,3",
1097
972
"EventCode": "0xB7, 0xBB",
1098
973
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1099
974
"MSRIndex": "0x1a6,0x1a7",
···
1104
977
},
1105
978
{
1106
979
"BriefDescription": "All offcore code reads",
980
+
"Counter": "0,1,2,3",
1107
981
"EventCode": "0xB7, 0xBB",
1108
982
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1109
983
"MSRIndex": "0x1a6,0x1a7",
···
1114
986
},
1115
987
{
1116
988
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
989
+
"Counter": "0,1,2,3",
1117
990
"EventCode": "0xB7, 0xBB",
1118
991
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1119
992
"MSRIndex": "0x1a6,0x1a7",
···
1124
995
},
1125
996
{
1126
997
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
998
+
"Counter": "0,1,2,3",
1127
999
"EventCode": "0xB7, 0xBB",
1128
1000
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1129
1001
"MSRIndex": "0x1a6,0x1a7",
···
1134
1004
},
1135
1005
{
1136
1006
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
1007
+
"Counter": "0,1,2,3",
1137
1008
"EventCode": "0xB7, 0xBB",
1138
1009
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1139
1010
"MSRIndex": "0x1a6,0x1a7",
···
1144
1013
},
1145
1014
{
1146
1015
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
1016
+
"Counter": "0,1,2,3",
1147
1017
"EventCode": "0xB7, 0xBB",
1148
1018
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1149
1019
"MSRIndex": "0x1a6,0x1a7",
···
1154
1022
},
1155
1023
{
1156
1024
"BriefDescription": "Offcore code reads satisfied by the LLC",
1025
+
"Counter": "0,1,2,3",
1157
1026
"EventCode": "0xB7, 0xBB",
1158
1027
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1159
1028
"MSRIndex": "0x1a6,0x1a7",
···
1164
1031
},
1165
1032
{
1166
1033
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
1034
+
"Counter": "0,1,2,3",
1167
1035
"EventCode": "0xB7, 0xBB",
1168
1036
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1169
1037
"MSRIndex": "0x1a6,0x1a7",
···
1174
1040
},
1175
1041
{
1176
1042
"BriefDescription": "Offcore code reads satisfied by a remote cache",
1043
+
"Counter": "0,1,2,3",
1177
1044
"EventCode": "0xB7, 0xBB",
1178
1045
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1179
1046
"MSRIndex": "0x1a6,0x1a7",
···
1184
1049
},
1185
1050
{
1186
1051
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1052
+
"Counter": "0,1,2,3",
1187
1053
"EventCode": "0xB7, 0xBB",
1188
1054
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1189
1055
"MSRIndex": "0x1a6,0x1a7",
···
1194
1058
},
1195
1059
{
1196
1060
"BriefDescription": "Offcore code reads that HIT in a remote cache",
1061
+
"Counter": "0,1,2,3",
1197
1062
"EventCode": "0xB7, 0xBB",
1198
1063
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1199
1064
"MSRIndex": "0x1a6,0x1a7",
···
1204
1067
},
1205
1068
{
1206
1069
"BriefDescription": "Offcore code reads that HITM in a remote cache",
1070
+
"Counter": "0,1,2,3",
1207
1071
"EventCode": "0xB7, 0xBB",
1208
1072
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1209
1073
"MSRIndex": "0x1a6,0x1a7",
···
1214
1076
},
1215
1077
{
1216
1078
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1079
+
"Counter": "0,1,2,3",
1217
1080
"EventCode": "0xB7, 0xBB",
1218
1081
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1219
1082
"MSRIndex": "0x1a6,0x1a7",
···
1224
1085
},
1225
1086
{
1226
1087
"BriefDescription": "All offcore requests",
1088
+
"Counter": "0,1,2,3",
1227
1089
"EventCode": "0xB7, 0xBB",
1228
1090
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1229
1091
"MSRIndex": "0x1a6,0x1a7",
···
1234
1094
},
1235
1095
{
1236
1096
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1097
+
"Counter": "0,1,2,3",
1237
1098
"EventCode": "0xB7, 0xBB",
1238
1099
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1239
1100
"MSRIndex": "0x1a6,0x1a7",
···
1244
1103
},
1245
1104
{
1246
1105
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1106
+
"Counter": "0,1,2,3",
1247
1107
"EventCode": "0xB7, 0xBB",
1248
1108
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1249
1109
"MSRIndex": "0x1a6,0x1a7",
···
1254
1112
},
1255
1113
{
1256
1114
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1115
+
"Counter": "0,1,2,3",
1257
1116
"EventCode": "0xB7, 0xBB",
1258
1117
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1259
1118
"MSRIndex": "0x1a6,0x1a7",
···
1264
1121
},
1265
1122
{
1266
1123
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
1124
+
"Counter": "0,1,2,3",
1267
1125
"EventCode": "0xB7, 0xBB",
1268
1126
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1269
1127
"MSRIndex": "0x1a6,0x1a7",
···
1274
1130
},
1275
1131
{
1276
1132
"BriefDescription": "Offcore requests satisfied by the LLC",
1133
+
"Counter": "0,1,2,3",
1277
1134
"EventCode": "0xB7, 0xBB",
1278
1135
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1279
1136
"MSRIndex": "0x1a6,0x1a7",
···
1284
1139
},
1285
1140
{
1286
1141
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1142
+
"Counter": "0,1,2,3",
1287
1143
"EventCode": "0xB7, 0xBB",
1288
1144
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1289
1145
"MSRIndex": "0x1a6,0x1a7",
···
1294
1148
},
1295
1149
{
1296
1150
"BriefDescription": "Offcore requests satisfied by a remote cache",
1151
+
"Counter": "0,1,2,3",
1297
1152
"EventCode": "0xB7, 0xBB",
1298
1153
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1299
1154
"MSRIndex": "0x1a6,0x1a7",
···
1304
1157
},
1305
1158
{
1306
1159
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1160
+
"Counter": "0,1,2,3",
1307
1161
"EventCode": "0xB7, 0xBB",
1308
1162
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1309
1163
"MSRIndex": "0x1a6,0x1a7",
···
1314
1166
},
1315
1167
{
1316
1168
"BriefDescription": "Offcore requests that HIT in a remote cache",
1169
+
"Counter": "0,1,2,3",
1317
1170
"EventCode": "0xB7, 0xBB",
1318
1171
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1319
1172
"MSRIndex": "0x1a6,0x1a7",
···
1324
1175
},
1325
1176
{
1326
1177
"BriefDescription": "Offcore requests that HITM in a remote cache",
1178
+
"Counter": "0,1,2,3",
1327
1179
"EventCode": "0xB7, 0xBB",
1328
1180
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1329
1181
"MSRIndex": "0x1a6,0x1a7",
···
1334
1184
},
1335
1185
{
1336
1186
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1187
+
"Counter": "0,1,2,3",
1337
1188
"EventCode": "0xB7, 0xBB",
1338
1189
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1339
1190
"MSRIndex": "0x1a6,0x1a7",
···
1344
1193
},
1345
1194
{
1346
1195
"BriefDescription": "All offcore RFO requests",
1196
+
"Counter": "0,1,2,3",
1347
1197
"EventCode": "0xB7, 0xBB",
1348
1198
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1349
1199
"MSRIndex": "0x1a6,0x1a7",
···
1354
1202
},
1355
1203
{
1356
1204
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1205
+
"Counter": "0,1,2,3",
1357
1206
"EventCode": "0xB7, 0xBB",
1358
1207
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1359
1208
"MSRIndex": "0x1a6,0x1a7",
···
1364
1211
},
1365
1212
{
1366
1213
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1214
+
"Counter": "0,1,2,3",
1367
1215
"EventCode": "0xB7, 0xBB",
1368
1216
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1369
1217
"MSRIndex": "0x1a6,0x1a7",
···
1374
1220
},
1375
1221
{
1376
1222
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1223
+
"Counter": "0,1,2,3",
1377
1224
"EventCode": "0xB7, 0xBB",
1378
1225
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1379
1226
"MSRIndex": "0x1a6,0x1a7",
···
1384
1229
},
1385
1230
{
1386
1231
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
1232
+
"Counter": "0,1,2,3",
1387
1233
"EventCode": "0xB7, 0xBB",
1388
1234
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1389
1235
"MSRIndex": "0x1a6,0x1a7",
···
1394
1238
},
1395
1239
{
1396
1240
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
1241
+
"Counter": "0,1,2,3",
1397
1242
"EventCode": "0xB7, 0xBB",
1398
1243
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1399
1244
"MSRIndex": "0x1a6,0x1a7",
···
1404
1247
},
1405
1248
{
1406
1249
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1250
+
"Counter": "0,1,2,3",
1407
1251
"EventCode": "0xB7, 0xBB",
1408
1252
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1409
1253
"MSRIndex": "0x1a6,0x1a7",
···
1414
1256
},
1415
1257
{
1416
1258
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1259
+
"Counter": "0,1,2,3",
1417
1260
"EventCode": "0xB7, 0xBB",
1418
1261
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1419
1262
"MSRIndex": "0x1a6,0x1a7",
···
1424
1265
},
1425
1266
{
1426
1267
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1268
+
"Counter": "0,1,2,3",
1427
1269
"EventCode": "0xB7, 0xBB",
1428
1270
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1429
1271
"MSRIndex": "0x1a6,0x1a7",
···
1434
1274
},
1435
1275
{
1436
1276
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1277
+
"Counter": "0,1,2,3",
1437
1278
"EventCode": "0xB7, 0xBB",
1438
1279
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1439
1280
"MSRIndex": "0x1a6,0x1a7",
···
1444
1283
},
1445
1284
{
1446
1285
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1286
+
"Counter": "0,1,2,3",
1447
1287
"EventCode": "0xB7, 0xBB",
1448
1288
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1449
1289
"MSRIndex": "0x1a6,0x1a7",
···
1454
1292
},
1455
1293
{
1456
1294
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
1295
+
"Counter": "0,1,2,3",
1457
1296
"EventCode": "0xB7, 0xBB",
1458
1297
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1459
1298
"MSRIndex": "0x1a6,0x1a7",
···
1464
1301
},
1465
1302
{
1466
1303
"BriefDescription": "All offcore writebacks",
1304
+
"Counter": "0,1,2,3",
1467
1305
"EventCode": "0xB7, 0xBB",
1468
1306
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1469
1307
"MSRIndex": "0x1a6,0x1a7",
···
1474
1310
},
1475
1311
{
1476
1312
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1313
+
"Counter": "0,1,2,3",
1477
1314
"EventCode": "0xB7, 0xBB",
1478
1315
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1479
1316
"MSRIndex": "0x1a6,0x1a7",
···
1484
1319
},
1485
1320
{
1486
1321
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1322
+
"Counter": "0,1,2,3",
1487
1323
"EventCode": "0xB7, 0xBB",
1488
1324
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1489
1325
"MSRIndex": "0x1a6,0x1a7",
···
1494
1328
},
1495
1329
{
1496
1330
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
1331
+
"Counter": "0,1,2,3",
1497
1332
"EventCode": "0xB7, 0xBB",
1498
1333
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1499
1334
"MSRIndex": "0x1a6,0x1a7",
···
1504
1337
},
1505
1338
{
1506
1339
"BriefDescription": "Offcore writebacks to the LLC",
1340
+
"Counter": "0,1,2,3",
1507
1341
"EventCode": "0xB7, 0xBB",
1508
1342
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1509
1343
"MSRIndex": "0x1a6,0x1a7",
···
1514
1346
},
1515
1347
{
1516
1348
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1349
+
"Counter": "0,1,2,3",
1517
1350
"EventCode": "0xB7, 0xBB",
1518
1351
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1519
1352
"MSRIndex": "0x1a6,0x1a7",
···
1524
1355
},
1525
1356
{
1526
1357
"BriefDescription": "Offcore writebacks to a remote cache",
1358
+
"Counter": "0,1,2,3",
1527
1359
"EventCode": "0xB7, 0xBB",
1528
1360
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1529
1361
"MSRIndex": "0x1a6,0x1a7",
···
1534
1364
},
1535
1365
{
1536
1366
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1367
+
"Counter": "0,1,2,3",
1537
1368
"EventCode": "0xB7, 0xBB",
1538
1369
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1539
1370
"MSRIndex": "0x1a6,0x1a7",
···
1544
1373
},
1545
1374
{
1546
1375
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
1376
+
"Counter": "0,1,2,3",
1547
1377
"EventCode": "0xB7, 0xBB",
1548
1378
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1549
1379
"MSRIndex": "0x1a6,0x1a7",
···
1554
1382
},
1555
1383
{
1556
1384
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
1385
+
"Counter": "0,1,2,3",
1557
1386
"EventCode": "0xB7, 0xBB",
1558
1387
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1559
1388
"MSRIndex": "0x1a6,0x1a7",
···
1564
1391
},
1565
1392
{
1566
1393
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1394
+
"Counter": "0,1,2,3",
1567
1395
"EventCode": "0xB7, 0xBB",
1568
1396
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1569
1397
"MSRIndex": "0x1a6,0x1a7",
···
1574
1400
},
1575
1401
{
1576
1402
"BriefDescription": "All offcore code or data read requests",
1403
+
"Counter": "0,1,2,3",
1577
1404
"EventCode": "0xB7, 0xBB",
1578
1405
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1579
1406
"MSRIndex": "0x1a6,0x1a7",
···
1584
1409
},
1585
1410
{
1586
1411
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1412
+
"Counter": "0,1,2,3",
1587
1413
"EventCode": "0xB7, 0xBB",
1588
1414
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1589
1415
"MSRIndex": "0x1a6,0x1a7",
···
1594
1418
},
1595
1419
{
1596
1420
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1421
+
"Counter": "0,1,2,3",
1597
1422
"EventCode": "0xB7, 0xBB",
1598
1423
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1599
1424
"MSRIndex": "0x1a6,0x1a7",
···
1604
1427
},
1605
1428
{
1606
1429
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1430
+
"Counter": "0,1,2,3",
1607
1431
"EventCode": "0xB7, 0xBB",
1608
1432
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1609
1433
"MSRIndex": "0x1a6,0x1a7",
···
1614
1436
},
1615
1437
{
1616
1438
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
1439
+
"Counter": "0,1,2,3",
1617
1440
"EventCode": "0xB7, 0xBB",
1618
1441
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1619
1442
"MSRIndex": "0x1a6,0x1a7",
···
1624
1445
},
1625
1446
{
1626
1447
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1448
+
"Counter": "0,1,2,3",
1627
1449
"EventCode": "0xB7, 0xBB",
1628
1450
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1629
1451
"MSRIndex": "0x1a6,0x1a7",
···
1634
1454
},
1635
1455
{
1636
1456
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1457
+
"Counter": "0,1,2,3",
1637
1458
"EventCode": "0xB7, 0xBB",
1638
1459
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1639
1460
"MSRIndex": "0x1a6,0x1a7",
···
1644
1463
},
1645
1464
{
1646
1465
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1466
+
"Counter": "0,1,2,3",
1647
1467
"EventCode": "0xB7, 0xBB",
1648
1468
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1649
1469
"MSRIndex": "0x1a6,0x1a7",
···
1654
1472
},
1655
1473
{
1656
1474
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1475
+
"Counter": "0,1,2,3",
1657
1476
"EventCode": "0xB7, 0xBB",
1658
1477
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1659
1478
"MSRIndex": "0x1a6,0x1a7",
···
1664
1481
},
1665
1482
{
1666
1483
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1484
+
"Counter": "0,1,2,3",
1667
1485
"EventCode": "0xB7, 0xBB",
1668
1486
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1669
1487
"MSRIndex": "0x1a6,0x1a7",
···
1674
1490
},
1675
1491
{
1676
1492
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1493
+
"Counter": "0,1,2,3",
1677
1494
"EventCode": "0xB7, 0xBB",
1678
1495
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1679
1496
"MSRIndex": "0x1a6,0x1a7",
···
1684
1499
},
1685
1500
{
1686
1501
"BriefDescription": "Offcore request = all data, response = any cache_dram",
1502
+
"Counter": "0,1,2,3",
1687
1503
"EventCode": "0xB7, 0xBB",
1688
1504
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1689
1505
"MSRIndex": "0x1a6,0x1a7",
···
1694
1508
},
1695
1509
{
1696
1510
"BriefDescription": "Offcore request = all data, response = any location",
1511
+
"Counter": "0,1,2,3",
1697
1512
"EventCode": "0xB7, 0xBB",
1698
1513
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1699
1514
"MSRIndex": "0x1a6,0x1a7",
···
1704
1517
},
1705
1518
{
1706
1519
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
1520
+
"Counter": "0,1,2,3",
1707
1521
"EventCode": "0xB7, 0xBB",
1708
1522
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1709
1523
"MSRIndex": "0x1a6,0x1a7",
···
1714
1526
},
1715
1527
{
1716
1528
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
1529
+
"Counter": "0,1,2,3",
1717
1530
"EventCode": "0xB7, 0xBB",
1718
1531
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1719
1532
"MSRIndex": "0x1a6,0x1a7",
···
1724
1535
},
1725
1536
{
1726
1537
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
1538
+
"Counter": "0,1,2,3",
1727
1539
"EventCode": "0xB7, 0xBB",
1728
1540
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1729
1541
"MSRIndex": "0x1a6,0x1a7",
···
1734
1544
},
1735
1545
{
1736
1546
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
1547
+
"Counter": "0,1,2,3",
1737
1548
"EventCode": "0xB7, 0xBB",
1738
1549
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1739
1550
"MSRIndex": "0x1a6,0x1a7",
···
1744
1553
},
1745
1554
{
1746
1555
"BriefDescription": "Offcore request = all data, response = local cache",
1556
+
"Counter": "0,1,2,3",
1747
1557
"EventCode": "0xB7, 0xBB",
1748
1558
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1749
1559
"MSRIndex": "0x1a6,0x1a7",
···
1754
1562
},
1755
1563
{
1756
1564
"BriefDescription": "Offcore request = all data, response = local cache or dram",
1565
+
"Counter": "0,1,2,3",
1757
1566
"EventCode": "0xB7, 0xBB",
1758
1567
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1759
1568
"MSRIndex": "0x1a6,0x1a7",
···
1764
1571
},
1765
1572
{
1766
1573
"BriefDescription": "Offcore request = all data, response = remote cache",
1574
+
"Counter": "0,1,2,3",
1767
1575
"EventCode": "0xB7, 0xBB",
1768
1576
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1769
1577
"MSRIndex": "0x1a6,0x1a7",
···
1774
1580
},
1775
1581
{
1776
1582
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
1583
+
"Counter": "0,1,2,3",
1777
1584
"EventCode": "0xB7, 0xBB",
1778
1585
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1779
1586
"MSRIndex": "0x1a6,0x1a7",
···
1784
1589
},
1785
1590
{
1786
1591
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
1592
+
"Counter": "0,1,2,3",
1787
1593
"EventCode": "0xB7, 0xBB",
1788
1594
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1789
1595
"MSRIndex": "0x1a6,0x1a7",
···
1794
1598
},
1795
1599
{
1796
1600
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
1601
+
"Counter": "0,1,2,3",
1797
1602
"EventCode": "0xB7, 0xBB",
1798
1603
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1799
1604
"MSRIndex": "0x1a6,0x1a7",
···
1804
1607
},
1805
1608
{
1806
1609
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1610
+
"Counter": "0,1,2,3",
1807
1611
"EventCode": "0xB7, 0xBB",
1808
1612
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1809
1613
"MSRIndex": "0x1a6,0x1a7",
···
1814
1616
},
1815
1617
{
1816
1618
"BriefDescription": "All offcore demand data requests",
1619
+
"Counter": "0,1,2,3",
1817
1620
"EventCode": "0xB7, 0xBB",
1818
1621
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1819
1622
"MSRIndex": "0x1a6,0x1a7",
···
1824
1625
},
1825
1626
{
1826
1627
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1628
+
"Counter": "0,1,2,3",
1827
1629
"EventCode": "0xB7, 0xBB",
1828
1630
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1829
1631
"MSRIndex": "0x1a6,0x1a7",
···
1834
1634
},
1835
1635
{
1836
1636
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1637
+
"Counter": "0,1,2,3",
1837
1638
"EventCode": "0xB7, 0xBB",
1838
1639
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1839
1640
"MSRIndex": "0x1a6,0x1a7",
···
1844
1643
},
1845
1644
{
1846
1645
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1646
+
"Counter": "0,1,2,3",
1847
1647
"EventCode": "0xB7, 0xBB",
1848
1648
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1849
1649
"MSRIndex": "0x1a6,0x1a7",
···
1854
1652
},
1855
1653
{
1856
1654
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
1655
+
"Counter": "0,1,2,3",
1857
1656
"EventCode": "0xB7, 0xBB",
1858
1657
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1859
1658
"MSRIndex": "0x1a6,0x1a7",
···
1864
1661
},
1865
1662
{
1866
1663
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
1664
+
"Counter": "0,1,2,3",
1867
1665
"EventCode": "0xB7, 0xBB",
1868
1666
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1869
1667
"MSRIndex": "0x1a6,0x1a7",
···
1874
1670
},
1875
1671
{
1876
1672
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1673
+
"Counter": "0,1,2,3",
1877
1674
"EventCode": "0xB7, 0xBB",
1878
1675
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1879
1676
"MSRIndex": "0x1a6,0x1a7",
···
1884
1679
},
1885
1680
{
1886
1681
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
1682
+
"Counter": "0,1,2,3",
1887
1683
"EventCode": "0xB7, 0xBB",
1888
1684
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
1889
1685
"MSRIndex": "0x1a6,0x1a7",
···
1894
1688
},
1895
1689
{
1896
1690
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
1691
+
"Counter": "0,1,2,3",
1897
1692
"EventCode": "0xB7, 0xBB",
1898
1693
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
1899
1694
"MSRIndex": "0x1a6,0x1a7",
···
1904
1697
},
1905
1698
{
1906
1699
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
1700
+
"Counter": "0,1,2,3",
1907
1701
"EventCode": "0xB7, 0xBB",
1908
1702
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
1909
1703
"MSRIndex": "0x1a6,0x1a7",
···
1914
1706
},
1915
1707
{
1916
1708
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
1709
+
"Counter": "0,1,2,3",
1917
1710
"EventCode": "0xB7, 0xBB",
1918
1711
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1919
1712
"MSRIndex": "0x1a6,0x1a7",
···
1924
1715
},
1925
1716
{
1926
1717
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
1718
+
"Counter": "0,1,2,3",
1927
1719
"EventCode": "0xB7, 0xBB",
1928
1720
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1929
1721
"MSRIndex": "0x1a6,0x1a7",
···
1934
1724
},
1935
1725
{
1936
1726
"BriefDescription": "All offcore demand data reads",
1727
+
"Counter": "0,1,2,3",
1937
1728
"EventCode": "0xB7, 0xBB",
1938
1729
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1939
1730
"MSRIndex": "0x1a6,0x1a7",
···
1944
1733
},
1945
1734
{
1946
1735
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
1736
+
"Counter": "0,1,2,3",
1947
1737
"EventCode": "0xB7, 0xBB",
1948
1738
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1949
1739
"MSRIndex": "0x1a6,0x1a7",
···
1954
1742
},
1955
1743
{
1956
1744
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
1745
+
"Counter": "0,1,2,3",
1957
1746
"EventCode": "0xB7, 0xBB",
1958
1747
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1959
1748
"MSRIndex": "0x1a6,0x1a7",
···
1964
1751
},
1965
1752
{
1966
1753
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
1754
+
"Counter": "0,1,2,3",
1967
1755
"EventCode": "0xB7, 0xBB",
1968
1756
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1969
1757
"MSRIndex": "0x1a6,0x1a7",
···
1974
1760
},
1975
1761
{
1976
1762
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
1763
+
"Counter": "0,1,2,3",
1977
1764
"EventCode": "0xB7, 0xBB",
1978
1765
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1979
1766
"MSRIndex": "0x1a6,0x1a7",
···
1984
1769
},
1985
1770
{
1986
1771
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
1772
+
"Counter": "0,1,2,3",
1987
1773
"EventCode": "0xB7, 0xBB",
1988
1774
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1989
1775
"MSRIndex": "0x1a6,0x1a7",
···
1994
1778
},
1995
1779
{
1996
1780
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
1781
+
"Counter": "0,1,2,3",
1997
1782
"EventCode": "0xB7, 0xBB",
1998
1783
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
1999
1784
"MSRIndex": "0x1a6,0x1a7",
···
2004
1787
},
2005
1788
{
2006
1789
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
1790
+
"Counter": "0,1,2,3",
2007
1791
"EventCode": "0xB7, 0xBB",
2008
1792
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
2009
1793
"MSRIndex": "0x1a6,0x1a7",
···
2014
1796
},
2015
1797
{
2016
1798
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
1799
+
"Counter": "0,1,2,3",
2017
1800
"EventCode": "0xB7, 0xBB",
2018
1801
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
2019
1802
"MSRIndex": "0x1a6,0x1a7",
···
2024
1805
},
2025
1806
{
2026
1807
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
1808
+
"Counter": "0,1,2,3",
2027
1809
"EventCode": "0xB7, 0xBB",
2028
1810
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
2029
1811
"MSRIndex": "0x1a6,0x1a7",
···
2034
1814
},
2035
1815
{
2036
1816
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
1817
+
"Counter": "0,1,2,3",
2037
1818
"EventCode": "0xB7, 0xBB",
2038
1819
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
2039
1820
"MSRIndex": "0x1a6,0x1a7",
···
2044
1823
},
2045
1824
{
2046
1825
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
1826
+
"Counter": "0,1,2,3",
2047
1827
"EventCode": "0xB7, 0xBB",
2048
1828
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
2049
1829
"MSRIndex": "0x1a6,0x1a7",
···
2054
1832
},
2055
1833
{
2056
1834
"BriefDescription": "All offcore demand code reads",
1835
+
"Counter": "0,1,2,3",
2057
1836
"EventCode": "0xB7, 0xBB",
2058
1837
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
2059
1838
"MSRIndex": "0x1a6,0x1a7",
···
2064
1841
},
2065
1842
{
2066
1843
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
1844
+
"Counter": "0,1,2,3",
2067
1845
"EventCode": "0xB7, 0xBB",
2068
1846
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
2069
1847
"MSRIndex": "0x1a6,0x1a7",
···
2074
1850
},
2075
1851
{
2076
1852
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
1853
+
"Counter": "0,1,2,3",
2077
1854
"EventCode": "0xB7, 0xBB",
2078
1855
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
2079
1856
"MSRIndex": "0x1a6,0x1a7",
···
2084
1859
},
2085
1860
{
2086
1861
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
1862
+
"Counter": "0,1,2,3",
2087
1863
"EventCode": "0xB7, 0xBB",
2088
1864
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2089
1865
"MSRIndex": "0x1a6,0x1a7",
···
2094
1868
},
2095
1869
{
2096
1870
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
1871
+
"Counter": "0,1,2,3",
2097
1872
"EventCode": "0xB7, 0xBB",
2098
1873
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2099
1874
"MSRIndex": "0x1a6,0x1a7",
···
2104
1877
},
2105
1878
{
2106
1879
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
1880
+
"Counter": "0,1,2,3",
2107
1881
"EventCode": "0xB7, 0xBB",
2108
1882
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2109
1883
"MSRIndex": "0x1a6,0x1a7",
···
2114
1886
},
2115
1887
{
2116
1888
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
1889
+
"Counter": "0,1,2,3",
2117
1890
"EventCode": "0xB7, 0xBB",
2118
1891
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
2119
1892
"MSRIndex": "0x1a6,0x1a7",
···
2124
1895
},
2125
1896
{
2126
1897
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
1898
+
"Counter": "0,1,2,3",
2127
1899
"EventCode": "0xB7, 0xBB",
2128
1900
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
2129
1901
"MSRIndex": "0x1a6,0x1a7",
···
2134
1904
},
2135
1905
{
2136
1906
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
1907
+
"Counter": "0,1,2,3",
2137
1908
"EventCode": "0xB7, 0xBB",
2138
1909
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
2139
1910
"MSRIndex": "0x1a6,0x1a7",
···
2144
1913
},
2145
1914
{
2146
1915
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
1916
+
"Counter": "0,1,2,3",
2147
1917
"EventCode": "0xB7, 0xBB",
2148
1918
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
2149
1919
"MSRIndex": "0x1a6,0x1a7",
···
2154
1922
},
2155
1923
{
2156
1924
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
1925
+
"Counter": "0,1,2,3",
2157
1926
"EventCode": "0xB7, 0xBB",
2158
1927
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2159
1928
"MSRIndex": "0x1a6,0x1a7",
···
2164
1931
},
2165
1932
{
2166
1933
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
1934
+
"Counter": "0,1,2,3",
2167
1935
"EventCode": "0xB7, 0xBB",
2168
1936
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2169
1937
"MSRIndex": "0x1a6,0x1a7",
···
2174
1940
},
2175
1941
{
2176
1942
"BriefDescription": "All offcore demand RFO requests",
1943
+
"Counter": "0,1,2,3",
2177
1944
"EventCode": "0xB7, 0xBB",
2178
1945
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2179
1946
"MSRIndex": "0x1a6,0x1a7",
···
2184
1949
},
2185
1950
{
2186
1951
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
1952
+
"Counter": "0,1,2,3",
2187
1953
"EventCode": "0xB7, 0xBB",
2188
1954
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2189
1955
"MSRIndex": "0x1a6,0x1a7",
···
2194
1958
},
2195
1959
{
2196
1960
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
1961
+
"Counter": "0,1,2,3",
2197
1962
"EventCode": "0xB7, 0xBB",
2198
1963
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2199
1964
"MSRIndex": "0x1a6,0x1a7",
···
2204
1967
},
2205
1968
{
2206
1969
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
1970
+
"Counter": "0,1,2,3",
2207
1971
"EventCode": "0xB7, 0xBB",
2208
1972
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2209
1973
"MSRIndex": "0x1a6,0x1a7",
···
2214
1976
},
2215
1977
{
2216
1978
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
1979
+
"Counter": "0,1,2,3",
2217
1980
"EventCode": "0xB7, 0xBB",
2218
1981
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2219
1982
"MSRIndex": "0x1a6,0x1a7",
···
2224
1985
},
2225
1986
{
2226
1987
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
1988
+
"Counter": "0,1,2,3",
2227
1989
"EventCode": "0xB7, 0xBB",
2228
1990
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2229
1991
"MSRIndex": "0x1a6,0x1a7",
···
2234
1994
},
2235
1995
{
2236
1996
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
1997
+
"Counter": "0,1,2,3",
2237
1998
"EventCode": "0xB7, 0xBB",
2238
1999
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
2239
2000
"MSRIndex": "0x1a6,0x1a7",
···
2244
2003
},
2245
2004
{
2246
2005
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
2006
+
"Counter": "0,1,2,3",
2247
2007
"EventCode": "0xB7, 0xBB",
2248
2008
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2249
2009
"MSRIndex": "0x1a6,0x1a7",
···
2254
2012
},
2255
2013
{
2256
2014
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
2015
+
"Counter": "0,1,2,3",
2257
2016
"EventCode": "0xB7, 0xBB",
2258
2017
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2259
2018
"MSRIndex": "0x1a6,0x1a7",
···
2264
2021
},
2265
2022
{
2266
2023
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
2024
+
"Counter": "0,1,2,3",
2267
2025
"EventCode": "0xB7, 0xBB",
2268
2026
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2269
2027
"MSRIndex": "0x1a6,0x1a7",
···
2274
2030
},
2275
2031
{
2276
2032
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
2033
+
"Counter": "0,1,2,3",
2277
2034
"EventCode": "0xB7, 0xBB",
2278
2035
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2279
2036
"MSRIndex": "0x1a6,0x1a7",
···
2284
2039
},
2285
2040
{
2286
2041
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
2042
+
"Counter": "0,1,2,3",
2287
2043
"EventCode": "0xB7, 0xBB",
2288
2044
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2289
2045
"MSRIndex": "0x1a6,0x1a7",
···
2294
2048
},
2295
2049
{
2296
2050
"BriefDescription": "All offcore other requests",
2051
+
"Counter": "0,1,2,3",
2297
2052
"EventCode": "0xB7, 0xBB",
2298
2053
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2299
2054
"MSRIndex": "0x1a6,0x1a7",
···
2304
2057
},
2305
2058
{
2306
2059
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2060
+
"Counter": "0,1,2,3",
2307
2061
"EventCode": "0xB7, 0xBB",
2308
2062
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2309
2063
"MSRIndex": "0x1a6,0x1a7",
···
2314
2066
},
2315
2067
{
2316
2068
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2069
+
"Counter": "0,1,2,3",
2317
2070
"EventCode": "0xB7, 0xBB",
2318
2071
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2319
2072
"MSRIndex": "0x1a6,0x1a7",
···
2324
2075
},
2325
2076
{
2326
2077
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2078
+
"Counter": "0,1,2,3",
2327
2079
"EventCode": "0xB7, 0xBB",
2328
2080
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2329
2081
"MSRIndex": "0x1a6,0x1a7",
···
2334
2084
},
2335
2085
{
2336
2086
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
2087
+
"Counter": "0,1,2,3",
2337
2088
"EventCode": "0xB7, 0xBB",
2338
2089
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2339
2090
"MSRIndex": "0x1a6,0x1a7",
···
2344
2093
},
2345
2094
{
2346
2095
"BriefDescription": "Offcore other requests satisfied by the LLC",
2096
+
"Counter": "0,1,2,3",
2347
2097
"EventCode": "0xB7, 0xBB",
2348
2098
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2349
2099
"MSRIndex": "0x1a6,0x1a7",
···
2354
2102
},
2355
2103
{
2356
2104
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2105
+
"Counter": "0,1,2,3",
2357
2106
"EventCode": "0xB7, 0xBB",
2358
2107
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2359
2108
"MSRIndex": "0x1a6,0x1a7",
···
2364
2111
},
2365
2112
{
2366
2113
"BriefDescription": "Offcore other requests satisfied by a remote cache",
2114
+
"Counter": "0,1,2,3",
2367
2115
"EventCode": "0xB7, 0xBB",
2368
2116
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2369
2117
"MSRIndex": "0x1a6,0x1a7",
···
2374
2120
},
2375
2121
{
2376
2122
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2123
+
"Counter": "0,1,2,3",
2377
2124
"EventCode": "0xB7, 0xBB",
2378
2125
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2379
2126
"MSRIndex": "0x1a6,0x1a7",
···
2384
2129
},
2385
2130
{
2386
2131
"BriefDescription": "Offcore other requests that HIT in a remote cache",
2132
+
"Counter": "0,1,2,3",
2387
2133
"EventCode": "0xB7, 0xBB",
2388
2134
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2389
2135
"MSRIndex": "0x1a6,0x1a7",
···
2394
2138
},
2395
2139
{
2396
2140
"BriefDescription": "Offcore other requests that HITM in a remote cache",
2141
+
"Counter": "0,1,2,3",
2397
2142
"EventCode": "0xB7, 0xBB",
2398
2143
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2399
2144
"MSRIndex": "0x1a6,0x1a7",
···
2404
2147
},
2405
2148
{
2406
2149
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2150
+
"Counter": "0,1,2,3",
2407
2151
"EventCode": "0xB7, 0xBB",
2408
2152
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2409
2153
"MSRIndex": "0x1a6,0x1a7",
···
2414
2156
},
2415
2157
{
2416
2158
"BriefDescription": "All offcore prefetch data requests",
2159
+
"Counter": "0,1,2,3",
2417
2160
"EventCode": "0xB7, 0xBB",
2418
2161
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2419
2162
"MSRIndex": "0x1a6,0x1a7",
···
2424
2165
},
2425
2166
{
2426
2167
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2168
+
"Counter": "0,1,2,3",
2427
2169
"EventCode": "0xB7, 0xBB",
2428
2170
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2429
2171
"MSRIndex": "0x1a6,0x1a7",
···
2434
2174
},
2435
2175
{
2436
2176
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2177
+
"Counter": "0,1,2,3",
2437
2178
"EventCode": "0xB7, 0xBB",
2438
2179
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2439
2180
"MSRIndex": "0x1a6,0x1a7",
···
2444
2183
},
2445
2184
{
2446
2185
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2186
+
"Counter": "0,1,2,3",
2447
2187
"EventCode": "0xB7, 0xBB",
2448
2188
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2449
2189
"MSRIndex": "0x1a6,0x1a7",
···
2454
2192
},
2455
2193
{
2456
2194
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
2195
+
"Counter": "0,1,2,3",
2457
2196
"EventCode": "0xB7, 0xBB",
2458
2197
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2459
2198
"MSRIndex": "0x1a6,0x1a7",
···
2464
2201
},
2465
2202
{
2466
2203
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2204
+
"Counter": "0,1,2,3",
2467
2205
"EventCode": "0xB7, 0xBB",
2468
2206
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2469
2207
"MSRIndex": "0x1a6,0x1a7",
···
2474
2210
},
2475
2211
{
2476
2212
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2213
+
"Counter": "0,1,2,3",
2477
2214
"EventCode": "0xB7, 0xBB",
2478
2215
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2479
2216
"MSRIndex": "0x1a6,0x1a7",
···
2484
2219
},
2485
2220
{
2486
2221
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2222
+
"Counter": "0,1,2,3",
2487
2223
"EventCode": "0xB7, 0xBB",
2488
2224
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2489
2225
"MSRIndex": "0x1a6,0x1a7",
···
2494
2228
},
2495
2229
{
2496
2230
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2231
+
"Counter": "0,1,2,3",
2497
2232
"EventCode": "0xB7, 0xBB",
2498
2233
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2499
2234
"MSRIndex": "0x1a6,0x1a7",
···
2504
2237
},
2505
2238
{
2506
2239
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2240
+
"Counter": "0,1,2,3",
2507
2241
"EventCode": "0xB7, 0xBB",
2508
2242
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2509
2243
"MSRIndex": "0x1a6,0x1a7",
···
2514
2246
},
2515
2247
{
2516
2248
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2249
+
"Counter": "0,1,2,3",
2517
2250
"EventCode": "0xB7, 0xBB",
2518
2251
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2519
2252
"MSRIndex": "0x1a6,0x1a7",
···
2524
2255
},
2525
2256
{
2526
2257
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2258
+
"Counter": "0,1,2,3",
2527
2259
"EventCode": "0xB7, 0xBB",
2528
2260
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2529
2261
"MSRIndex": "0x1a6,0x1a7",
···
2534
2264
},
2535
2265
{
2536
2266
"BriefDescription": "All offcore prefetch data reads",
2267
+
"Counter": "0,1,2,3",
2537
2268
"EventCode": "0xB7, 0xBB",
2538
2269
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2539
2270
"MSRIndex": "0x1a6,0x1a7",
···
2544
2273
},
2545
2274
{
2546
2275
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2276
+
"Counter": "0,1,2,3",
2547
2277
"EventCode": "0xB7, 0xBB",
2548
2278
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2549
2279
"MSRIndex": "0x1a6,0x1a7",
···
2554
2282
},
2555
2283
{
2556
2284
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2285
+
"Counter": "0,1,2,3",
2557
2286
"EventCode": "0xB7, 0xBB",
2558
2287
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2559
2288
"MSRIndex": "0x1a6,0x1a7",
···
2564
2291
},
2565
2292
{
2566
2293
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2294
+
"Counter": "0,1,2,3",
2567
2295
"EventCode": "0xB7, 0xBB",
2568
2296
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2569
2297
"MSRIndex": "0x1a6,0x1a7",
···
2574
2300
},
2575
2301
{
2576
2302
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
2303
+
"Counter": "0,1,2,3",
2577
2304
"EventCode": "0xB7, 0xBB",
2578
2305
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2579
2306
"MSRIndex": "0x1a6,0x1a7",
···
2584
2309
},
2585
2310
{
2586
2311
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2312
+
"Counter": "0,1,2,3",
2587
2313
"EventCode": "0xB7, 0xBB",
2588
2314
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2589
2315
"MSRIndex": "0x1a6,0x1a7",
···
2594
2318
},
2595
2319
{
2596
2320
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2321
+
"Counter": "0,1,2,3",
2597
2322
"EventCode": "0xB7, 0xBB",
2598
2323
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2599
2324
"MSRIndex": "0x1a6,0x1a7",
···
2604
2327
},
2605
2328
{
2606
2329
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2330
+
"Counter": "0,1,2,3",
2607
2331
"EventCode": "0xB7, 0xBB",
2608
2332
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2609
2333
"MSRIndex": "0x1a6,0x1a7",
···
2614
2336
},
2615
2337
{
2616
2338
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2339
+
"Counter": "0,1,2,3",
2617
2340
"EventCode": "0xB7, 0xBB",
2618
2341
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2619
2342
"MSRIndex": "0x1a6,0x1a7",
···
2624
2345
},
2625
2346
{
2626
2347
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2348
+
"Counter": "0,1,2,3",
2627
2349
"EventCode": "0xB7, 0xBB",
2628
2350
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2629
2351
"MSRIndex": "0x1a6,0x1a7",
···
2634
2354
},
2635
2355
{
2636
2356
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2357
+
"Counter": "0,1,2,3",
2637
2358
"EventCode": "0xB7, 0xBB",
2638
2359
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2639
2360
"MSRIndex": "0x1a6,0x1a7",
···
2644
2363
},
2645
2364
{
2646
2365
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2366
+
"Counter": "0,1,2,3",
2647
2367
"EventCode": "0xB7, 0xBB",
2648
2368
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2649
2369
"MSRIndex": "0x1a6,0x1a7",
···
2654
2372
},
2655
2373
{
2656
2374
"BriefDescription": "All offcore prefetch code reads",
2375
+
"Counter": "0,1,2,3",
2657
2376
"EventCode": "0xB7, 0xBB",
2658
2377
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2659
2378
"MSRIndex": "0x1a6,0x1a7",
···
2664
2381
},
2665
2382
{
2666
2383
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2384
+
"Counter": "0,1,2,3",
2667
2385
"EventCode": "0xB7, 0xBB",
2668
2386
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2669
2387
"MSRIndex": "0x1a6,0x1a7",
···
2674
2390
},
2675
2391
{
2676
2392
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2393
+
"Counter": "0,1,2,3",
2677
2394
"EventCode": "0xB7, 0xBB",
2678
2395
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2679
2396
"MSRIndex": "0x1a6,0x1a7",
···
2684
2399
},
2685
2400
{
2686
2401
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2402
+
"Counter": "0,1,2,3",
2687
2403
"EventCode": "0xB7, 0xBB",
2688
2404
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2689
2405
"MSRIndex": "0x1a6,0x1a7",
···
2694
2408
},
2695
2409
{
2696
2410
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
2411
+
"Counter": "0,1,2,3",
2697
2412
"EventCode": "0xB7, 0xBB",
2698
2413
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2699
2414
"MSRIndex": "0x1a6,0x1a7",
···
2704
2417
},
2705
2418
{
2706
2419
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2420
+
"Counter": "0,1,2,3",
2707
2421
"EventCode": "0xB7, 0xBB",
2708
2422
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2709
2423
"MSRIndex": "0x1a6,0x1a7",
···
2714
2426
},
2715
2427
{
2716
2428
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2429
+
"Counter": "0,1,2,3",
2717
2430
"EventCode": "0xB7, 0xBB",
2718
2431
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2719
2432
"MSRIndex": "0x1a6,0x1a7",
···
2724
2435
},
2725
2436
{
2726
2437
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2438
+
"Counter": "0,1,2,3",
2727
2439
"EventCode": "0xB7, 0xBB",
2728
2440
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2729
2441
"MSRIndex": "0x1a6,0x1a7",
···
2734
2444
},
2735
2445
{
2736
2446
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2447
+
"Counter": "0,1,2,3",
2737
2448
"EventCode": "0xB7, 0xBB",
2738
2449
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2739
2450
"MSRIndex": "0x1a6,0x1a7",
···
2744
2453
},
2745
2454
{
2746
2455
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2456
+
"Counter": "0,1,2,3",
2747
2457
"EventCode": "0xB7, 0xBB",
2748
2458
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2749
2459
"MSRIndex": "0x1a6,0x1a7",
···
2754
2462
},
2755
2463
{
2756
2464
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2465
+
"Counter": "0,1,2,3",
2757
2466
"EventCode": "0xB7, 0xBB",
2758
2467
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2759
2468
"MSRIndex": "0x1a6,0x1a7",
···
2764
2471
},
2765
2472
{
2766
2473
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2474
+
"Counter": "0,1,2,3",
2767
2475
"EventCode": "0xB7, 0xBB",
2768
2476
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2769
2477
"MSRIndex": "0x1a6,0x1a7",
···
2774
2480
},
2775
2481
{
2776
2482
"BriefDescription": "All offcore prefetch RFO requests",
2483
+
"Counter": "0,1,2,3",
2777
2484
"EventCode": "0xB7, 0xBB",
2778
2485
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2779
2486
"MSRIndex": "0x1a6,0x1a7",
···
2784
2489
},
2785
2490
{
2786
2491
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
2492
+
"Counter": "0,1,2,3",
2787
2493
"EventCode": "0xB7, 0xBB",
2788
2494
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2789
2495
"MSRIndex": "0x1a6,0x1a7",
···
2794
2498
},
2795
2499
{
2796
2500
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
2501
+
"Counter": "0,1,2,3",
2797
2502
"EventCode": "0xB7, 0xBB",
2798
2503
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2799
2504
"MSRIndex": "0x1a6,0x1a7",
···
2804
2507
},
2805
2508
{
2806
2509
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
2510
+
"Counter": "0,1,2,3",
2807
2511
"EventCode": "0xB7, 0xBB",
2808
2512
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2809
2513
"MSRIndex": "0x1a6,0x1a7",
···
2814
2516
},
2815
2517
{
2816
2518
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
2519
+
"Counter": "0,1,2,3",
2817
2520
"EventCode": "0xB7, 0xBB",
2818
2521
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2819
2522
"MSRIndex": "0x1a6,0x1a7",
···
2824
2525
},
2825
2526
{
2826
2527
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
2528
+
"Counter": "0,1,2,3",
2827
2529
"EventCode": "0xB7, 0xBB",
2828
2530
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2829
2531
"MSRIndex": "0x1a6,0x1a7",
···
2834
2534
},
2835
2535
{
2836
2536
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
2537
+
"Counter": "0,1,2,3",
2837
2538
"EventCode": "0xB7, 0xBB",
2838
2539
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
2839
2540
"MSRIndex": "0x1a6,0x1a7",
···
2844
2543
},
2845
2544
{
2846
2545
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
2546
+
"Counter": "0,1,2,3",
2847
2547
"EventCode": "0xB7, 0xBB",
2848
2548
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
2849
2549
"MSRIndex": "0x1a6,0x1a7",
···
2854
2552
},
2855
2553
{
2856
2554
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
2555
+
"Counter": "0,1,2,3",
2857
2556
"EventCode": "0xB7, 0xBB",
2858
2557
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
2859
2558
"MSRIndex": "0x1a6,0x1a7",
···
2864
2561
},
2865
2562
{
2866
2563
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
2564
+
"Counter": "0,1,2,3",
2867
2565
"EventCode": "0xB7, 0xBB",
2868
2566
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
2869
2567
"MSRIndex": "0x1a6,0x1a7",
···
2874
2570
},
2875
2571
{
2876
2572
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
2573
+
"Counter": "0,1,2,3",
2877
2574
"EventCode": "0xB7, 0xBB",
2878
2575
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2879
2576
"MSRIndex": "0x1a6,0x1a7",
···
2884
2579
},
2885
2580
{
2886
2581
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
2582
+
"Counter": "0,1,2,3",
2887
2583
"EventCode": "0xB7, 0xBB",
2888
2584
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2889
2585
"MSRIndex": "0x1a6,0x1a7",
···
2894
2588
},
2895
2589
{
2896
2590
"BriefDescription": "All offcore prefetch requests",
2591
+
"Counter": "0,1,2,3",
2897
2592
"EventCode": "0xB7, 0xBB",
2898
2593
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2899
2594
"MSRIndex": "0x1a6,0x1a7",
···
2904
2597
},
2905
2598
{
2906
2599
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
2600
+
"Counter": "0,1,2,3",
2907
2601
"EventCode": "0xB7, 0xBB",
2908
2602
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2909
2603
"MSRIndex": "0x1a6,0x1a7",
···
2914
2606
},
2915
2607
{
2916
2608
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
2609
+
"Counter": "0,1,2,3",
2917
2610
"EventCode": "0xB7, 0xBB",
2918
2611
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2919
2612
"MSRIndex": "0x1a6,0x1a7",
···
2924
2615
},
2925
2616
{
2926
2617
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
2618
+
"Counter": "0,1,2,3",
2927
2619
"EventCode": "0xB7, 0xBB",
2928
2620
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2929
2621
"MSRIndex": "0x1a6,0x1a7",
···
2934
2624
},
2935
2625
{
2936
2626
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
2627
+
"Counter": "0,1,2,3",
2937
2628
"EventCode": "0xB7, 0xBB",
2938
2629
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2939
2630
"MSRIndex": "0x1a6,0x1a7",
···
2944
2633
},
2945
2634
{
2946
2635
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
2636
+
"Counter": "0,1,2,3",
2947
2637
"EventCode": "0xB7, 0xBB",
2948
2638
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2949
2639
"MSRIndex": "0x1a6,0x1a7",
···
2954
2642
},
2955
2643
{
2956
2644
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
2645
+
"Counter": "0,1,2,3",
2957
2646
"EventCode": "0xB7, 0xBB",
2958
2647
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
2959
2648
"MSRIndex": "0x1a6,0x1a7",
···
2964
2651
},
2965
2652
{
2966
2653
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
2654
+
"Counter": "0,1,2,3",
2967
2655
"EventCode": "0xB7, 0xBB",
2968
2656
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
2969
2657
"MSRIndex": "0x1a6,0x1a7",
···
2974
2660
},
2975
2661
{
2976
2662
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
2663
+
"Counter": "0,1,2,3",
2977
2664
"EventCode": "0xB7, 0xBB",
2978
2665
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
2979
2666
"MSRIndex": "0x1a6,0x1a7",
···
2984
2669
},
2985
2670
{
2986
2671
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
2672
+
"Counter": "0,1,2,3",
2987
2673
"EventCode": "0xB7, 0xBB",
2988
2674
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
2989
2675
"MSRIndex": "0x1a6,0x1a7",
···
2994
2678
},
2995
2679
{
2996
2680
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
2681
+
"Counter": "0,1,2,3",
2997
2682
"EventCode": "0xB7, 0xBB",
2998
2683
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2999
2684
"MSRIndex": "0x1a6,0x1a7",
···
3004
2687
},
3005
2688
{
3006
2689
"BriefDescription": "Super Queue LRU hints sent to LLC",
2690
+
"Counter": "0,1,2,3",
3007
2691
"EventCode": "0xF4",
3008
2692
"EventName": "SQ_MISC.LRU_HINTS",
3009
2693
"SampleAfterValue": "2000000",
···
3012
2694
},
3013
2695
{
3014
2696
"BriefDescription": "Super Queue lock splits across a cache line",
2697
+
"Counter": "0,1,2,3",
3015
2698
"EventCode": "0xF4",
3016
2699
"EventName": "SQ_MISC.SPLIT_LOCK",
3017
2700
"SampleAfterValue": "2000000",
···
3020
2701
},
3021
2702
{
3022
2703
"BriefDescription": "Loads delayed with at-Retirement block code",
2704
+
"Counter": "0,1,2,3",
3023
2705
"EventCode": "0x6",
3024
2706
"EventName": "STORE_BLOCKS.AT_RET",
3025
2707
"SampleAfterValue": "200000",
···
3028
2708
},
3029
2709
{
3030
2710
"BriefDescription": "Cacheable loads delayed with L1D block code",
2711
+
"Counter": "0,1,2,3",
3031
2712
"EventCode": "0x6",
3032
2713
"EventName": "STORE_BLOCKS.L1D_BLOCK",
3033
2714
"SampleAfterValue": "200000",
+7
tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json
+7
tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json
+28
tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
+28
tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "X87 Floating point assists (Precise Event)",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xF7",
5
6
"EventName": "FP_ASSIST.ALL",
6
7
"PEBS": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0xF7",
14
14
"EventName": "FP_ASSIST.INPUT",
15
15
"PEBS": "1",
···
19
17
},
20
18
{
21
19
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xF7",
23
22
"EventName": "FP_ASSIST.OUTPUT",
24
23
"PEBS": "1",
···
28
25
},
29
26
{
30
27
"BriefDescription": "MMX Uops",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0x10",
32
30
"EventName": "FP_COMP_OPS_EXE.MMX",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "SSE2 integer Uops",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0x10",
40
37
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "SSE* FP double precision Uops",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0x10",
48
44
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "SSE and SSE2 FP Uops",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0x10",
56
51
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "SSE FP packed Uops",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0x10",
64
58
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "SSE FP scalar Uops",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0x10",
72
65
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "SSE* FP single precision Uops",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0x10",
80
72
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Computational floating-point operations executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x10",
88
79
"EventName": "FP_COMP_OPS_EXE.X87",
89
80
"SampleAfterValue": "2000000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "All Floating Point to and from MMX transitions",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0xCC",
96
86
"EventName": "FP_MMX_TRANS.ANY",
97
87
"SampleAfterValue": "2000000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Transitions from MMX to Floating Point instructions",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0xCC",
104
93
"EventName": "FP_MMX_TRANS.TO_FP",
105
94
"SampleAfterValue": "2000000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Transitions from Floating Point to MMX instructions",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0xCC",
112
100
"EventName": "FP_MMX_TRANS.TO_MMX",
113
101
"SampleAfterValue": "2000000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "128 bit SIMD integer pack operations",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x12",
120
107
"EventName": "SIMD_INT_128.PACK",
121
108
"SampleAfterValue": "200000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "128 bit SIMD integer arithmetic operations",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x12",
128
114
"EventName": "SIMD_INT_128.PACKED_ARITH",
129
115
"SampleAfterValue": "200000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "128 bit SIMD integer logical operations",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x12",
136
121
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
137
122
"SampleAfterValue": "200000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "128 bit SIMD integer multiply operations",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x12",
144
128
"EventName": "SIMD_INT_128.PACKED_MPY",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "128 bit SIMD integer shift operations",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x12",
152
135
"EventName": "SIMD_INT_128.PACKED_SHIFT",
153
136
"SampleAfterValue": "200000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x12",
160
142
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "128 bit SIMD integer unpack operations",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0x12",
168
149
"EventName": "SIMD_INT_128.UNPACK",
169
150
"SampleAfterValue": "200000",
···
172
151
},
173
152
{
174
153
"BriefDescription": "SIMD integer 64 bit pack operations",
154
+
"Counter": "0,1,2,3",
175
155
"EventCode": "0xFD",
176
156
"EventName": "SIMD_INT_64.PACK",
177
157
"SampleAfterValue": "200000",
···
180
158
},
181
159
{
182
160
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
161
+
"Counter": "0,1,2,3",
183
162
"EventCode": "0xFD",
184
163
"EventName": "SIMD_INT_64.PACKED_ARITH",
185
164
"SampleAfterValue": "200000",
···
188
165
},
189
166
{
190
167
"BriefDescription": "SIMD integer 64 bit logical operations",
168
+
"Counter": "0,1,2,3",
191
169
"EventCode": "0xFD",
192
170
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
193
171
"SampleAfterValue": "200000",
···
196
172
},
197
173
{
198
174
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
175
+
"Counter": "0,1,2,3",
199
176
"EventCode": "0xFD",
200
177
"EventName": "SIMD_INT_64.PACKED_MPY",
201
178
"SampleAfterValue": "200000",
···
204
179
},
205
180
{
206
181
"BriefDescription": "SIMD integer 64 bit shift operations",
182
+
"Counter": "0,1,2,3",
207
183
"EventCode": "0xFD",
208
184
"EventName": "SIMD_INT_64.PACKED_SHIFT",
209
185
"SampleAfterValue": "200000",
···
212
186
},
213
187
{
214
188
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
189
+
"Counter": "0,1,2,3",
215
190
"EventCode": "0xFD",
216
191
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
217
192
"SampleAfterValue": "200000",
···
220
193
},
221
194
{
222
195
"BriefDescription": "SIMD integer 64 bit unpack operations",
196
+
"Counter": "0,1,2,3",
223
197
"EventCode": "0xFD",
224
198
"EventName": "SIMD_INT_64.UNPACK",
225
199
"SampleAfterValue": "200000",
+3
tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
+3
tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Instructions decoded",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD0",
5
6
"EventName": "MACRO_INSTS.DECODED",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Macro-fused instructions decoded",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0xA6",
13
13
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "Two Uop instructions decoded",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x19",
21
20
"EventName": "TWO_UOP_INSTS_DECODED",
22
21
"SampleAfterValue": "2000000",
+67
tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
+67
tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Offcore data reads satisfied by any DRAM",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xB7, 0xBB",
5
6
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
6
7
"MSRIndex": "0x1a6,0x1a7",
···
11
10
},
12
11
{
13
12
"BriefDescription": "Offcore data reads that missed the LLC",
13
+
"Counter": "0,1,2,3",
14
14
"EventCode": "0xB7, 0xBB",
15
15
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
16
16
"MSRIndex": "0x1a6,0x1a7",
···
21
19
},
22
20
{
23
21
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
22
+
"Counter": "0,1,2,3",
24
23
"EventCode": "0xB7, 0xBB",
25
24
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
26
25
"MSRIndex": "0x1a6,0x1a7",
···
31
28
},
32
29
{
33
30
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
31
+
"Counter": "0,1,2,3",
34
32
"EventCode": "0xB7, 0xBB",
35
33
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
36
34
"MSRIndex": "0x1a6,0x1a7",
···
41
37
},
42
38
{
43
39
"BriefDescription": "Offcore code reads satisfied by any DRAM",
40
+
"Counter": "0,1,2,3",
44
41
"EventCode": "0xB7, 0xBB",
45
42
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
46
43
"MSRIndex": "0x1a6,0x1a7",
···
51
46
},
52
47
{
53
48
"BriefDescription": "Offcore code reads that missed the LLC",
49
+
"Counter": "0,1,2,3",
54
50
"EventCode": "0xB7, 0xBB",
55
51
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
56
52
"MSRIndex": "0x1a6,0x1a7",
···
61
55
},
62
56
{
63
57
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
58
+
"Counter": "0,1,2,3",
64
59
"EventCode": "0xB7, 0xBB",
65
60
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
66
61
"MSRIndex": "0x1a6,0x1a7",
···
71
64
},
72
65
{
73
66
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
67
+
"Counter": "0,1,2,3",
74
68
"EventCode": "0xB7, 0xBB",
75
69
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
76
70
"MSRIndex": "0x1a6,0x1a7",
···
81
73
},
82
74
{
83
75
"BriefDescription": "Offcore requests satisfied by any DRAM",
76
+
"Counter": "0,1,2,3",
84
77
"EventCode": "0xB7, 0xBB",
85
78
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
86
79
"MSRIndex": "0x1a6,0x1a7",
···
91
82
},
92
83
{
93
84
"BriefDescription": "Offcore requests that missed the LLC",
85
+
"Counter": "0,1,2,3",
94
86
"EventCode": "0xB7, 0xBB",
95
87
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
96
88
"MSRIndex": "0x1a6,0x1a7",
···
101
91
},
102
92
{
103
93
"BriefDescription": "Offcore requests satisfied by the local DRAM",
94
+
"Counter": "0,1,2,3",
104
95
"EventCode": "0xB7, 0xBB",
105
96
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
106
97
"MSRIndex": "0x1a6,0x1a7",
···
111
100
},
112
101
{
113
102
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
103
+
"Counter": "0,1,2,3",
114
104
"EventCode": "0xB7, 0xBB",
115
105
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
116
106
"MSRIndex": "0x1a6,0x1a7",
···
121
109
},
122
110
{
123
111
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
112
+
"Counter": "0,1,2,3",
124
113
"EventCode": "0xB7, 0xBB",
125
114
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
126
115
"MSRIndex": "0x1a6,0x1a7",
···
131
118
},
132
119
{
133
120
"BriefDescription": "Offcore RFO requests that missed the LLC",
121
+
"Counter": "0,1,2,3",
134
122
"EventCode": "0xB7, 0xBB",
135
123
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
136
124
"MSRIndex": "0x1a6,0x1a7",
···
141
127
},
142
128
{
143
129
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
130
+
"Counter": "0,1,2,3",
144
131
"EventCode": "0xB7, 0xBB",
145
132
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
146
133
"MSRIndex": "0x1a6,0x1a7",
···
151
136
},
152
137
{
153
138
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
139
+
"Counter": "0,1,2,3",
154
140
"EventCode": "0xB7, 0xBB",
155
141
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
156
142
"MSRIndex": "0x1a6,0x1a7",
···
161
145
},
162
146
{
163
147
"BriefDescription": "Offcore writebacks to any DRAM",
148
+
"Counter": "0,1,2,3",
164
149
"EventCode": "0xB7, 0xBB",
165
150
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
166
151
"MSRIndex": "0x1a6,0x1a7",
···
171
154
},
172
155
{
173
156
"BriefDescription": "Offcore writebacks that missed the LLC",
157
+
"Counter": "0,1,2,3",
174
158
"EventCode": "0xB7, 0xBB",
175
159
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
176
160
"MSRIndex": "0x1a6,0x1a7",
···
181
163
},
182
164
{
183
165
"BriefDescription": "Offcore writebacks to the local DRAM",
166
+
"Counter": "0,1,2,3",
184
167
"EventCode": "0xB7, 0xBB",
185
168
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
186
169
"MSRIndex": "0x1a6,0x1a7",
···
191
172
},
192
173
{
193
174
"BriefDescription": "Offcore writebacks to a remote DRAM",
175
+
"Counter": "0,1,2,3",
194
176
"EventCode": "0xB7, 0xBB",
195
177
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
196
178
"MSRIndex": "0x1a6,0x1a7",
···
201
181
},
202
182
{
203
183
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
184
+
"Counter": "0,1,2,3",
204
185
"EventCode": "0xB7, 0xBB",
205
186
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
206
187
"MSRIndex": "0x1a6,0x1a7",
···
211
190
},
212
191
{
213
192
"BriefDescription": "Offcore code or data read requests that missed the LLC",
193
+
"Counter": "0,1,2,3",
214
194
"EventCode": "0xB7, 0xBB",
215
195
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
216
196
"MSRIndex": "0x1a6,0x1a7",
···
221
199
},
222
200
{
223
201
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
202
+
"Counter": "0,1,2,3",
224
203
"EventCode": "0xB7, 0xBB",
225
204
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
226
205
"MSRIndex": "0x1a6,0x1a7",
···
231
208
},
232
209
{
233
210
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
211
+
"Counter": "0,1,2,3",
234
212
"EventCode": "0xB7, 0xBB",
235
213
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
236
214
"MSRIndex": "0x1a6,0x1a7",
···
241
217
},
242
218
{
243
219
"BriefDescription": "Offcore request = all data, response = any DRAM",
220
+
"Counter": "0,1,2,3",
244
221
"EventCode": "0xB7, 0xBB",
245
222
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
246
223
"MSRIndex": "0x1a6,0x1a7",
···
251
226
},
252
227
{
253
228
"BriefDescription": "Offcore request = all data, response = any LLC miss",
229
+
"Counter": "0,1,2,3",
254
230
"EventCode": "0xB7, 0xBB",
255
231
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
256
232
"MSRIndex": "0x1a6,0x1a7",
···
261
235
},
262
236
{
263
237
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
238
+
"Counter": "0,1,2,3",
264
239
"EventCode": "0xB7, 0xBB",
265
240
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
266
241
"MSRIndex": "0x1a6,0x1a7",
···
271
244
},
272
245
{
273
246
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
247
+
"Counter": "0,1,2,3",
274
248
"EventCode": "0xB7, 0xBB",
275
249
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
276
250
"MSRIndex": "0x1a6,0x1a7",
···
281
253
},
282
254
{
283
255
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
256
+
"Counter": "0,1,2,3",
284
257
"EventCode": "0xB7, 0xBB",
285
258
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
286
259
"MSRIndex": "0x1a6,0x1a7",
···
291
262
},
292
263
{
293
264
"BriefDescription": "Offcore demand data requests that missed the LLC",
265
+
"Counter": "0,1,2,3",
294
266
"EventCode": "0xB7, 0xBB",
295
267
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
296
268
"MSRIndex": "0x1a6,0x1a7",
···
301
271
},
302
272
{
303
273
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
274
+
"Counter": "0,1,2,3",
304
275
"EventCode": "0xB7, 0xBB",
305
276
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
306
277
"MSRIndex": "0x1a6,0x1a7",
···
311
280
},
312
281
{
313
282
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
283
+
"Counter": "0,1,2,3",
314
284
"EventCode": "0xB7, 0xBB",
315
285
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
316
286
"MSRIndex": "0x1a6,0x1a7",
···
321
289
},
322
290
{
323
291
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
292
+
"Counter": "0,1,2,3",
324
293
"EventCode": "0xB7, 0xBB",
325
294
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
326
295
"MSRIndex": "0x1a6,0x1a7",
···
331
298
},
332
299
{
333
300
"BriefDescription": "Offcore demand data reads that missed the LLC",
301
+
"Counter": "0,1,2,3",
334
302
"EventCode": "0xB7, 0xBB",
335
303
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
336
304
"MSRIndex": "0x1a6,0x1a7",
···
341
307
},
342
308
{
343
309
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
310
+
"Counter": "0,1,2,3",
344
311
"EventCode": "0xB7, 0xBB",
345
312
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
346
313
"MSRIndex": "0x1a6,0x1a7",
···
351
316
},
352
317
{
353
318
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
319
+
"Counter": "0,1,2,3",
354
320
"EventCode": "0xB7, 0xBB",
355
321
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
356
322
"MSRIndex": "0x1a6,0x1a7",
···
361
325
},
362
326
{
363
327
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
328
+
"Counter": "0,1,2,3",
364
329
"EventCode": "0xB7, 0xBB",
365
330
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
366
331
"MSRIndex": "0x1a6,0x1a7",
···
371
334
},
372
335
{
373
336
"BriefDescription": "Offcore demand code reads that missed the LLC",
337
+
"Counter": "0,1,2,3",
374
338
"EventCode": "0xB7, 0xBB",
375
339
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
376
340
"MSRIndex": "0x1a6,0x1a7",
···
381
343
},
382
344
{
383
345
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
346
+
"Counter": "0,1,2,3",
384
347
"EventCode": "0xB7, 0xBB",
385
348
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
386
349
"MSRIndex": "0x1a6,0x1a7",
···
391
352
},
392
353
{
393
354
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
355
+
"Counter": "0,1,2,3",
394
356
"EventCode": "0xB7, 0xBB",
395
357
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
396
358
"MSRIndex": "0x1a6,0x1a7",
···
401
361
},
402
362
{
403
363
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
364
+
"Counter": "0,1,2,3",
404
365
"EventCode": "0xB7, 0xBB",
405
366
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
406
367
"MSRIndex": "0x1a6,0x1a7",
···
411
370
},
412
371
{
413
372
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
373
+
"Counter": "0,1,2,3",
414
374
"EventCode": "0xB7, 0xBB",
415
375
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
416
376
"MSRIndex": "0x1a6,0x1a7",
···
421
379
},
422
380
{
423
381
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
382
+
"Counter": "0,1,2,3",
424
383
"EventCode": "0xB7, 0xBB",
425
384
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
426
385
"MSRIndex": "0x1a6,0x1a7",
···
431
388
},
432
389
{
433
390
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
391
+
"Counter": "0,1,2,3",
434
392
"EventCode": "0xB7, 0xBB",
435
393
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
436
394
"MSRIndex": "0x1a6,0x1a7",
···
441
397
},
442
398
{
443
399
"BriefDescription": "Offcore other requests satisfied by any DRAM",
400
+
"Counter": "0,1,2,3",
444
401
"EventCode": "0xB7, 0xBB",
445
402
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
446
403
"MSRIndex": "0x1a6,0x1a7",
···
451
406
},
452
407
{
453
408
"BriefDescription": "Offcore other requests that missed the LLC",
409
+
"Counter": "0,1,2,3",
454
410
"EventCode": "0xB7, 0xBB",
455
411
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
456
412
"MSRIndex": "0x1a6,0x1a7",
···
461
415
},
462
416
{
463
417
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
418
+
"Counter": "0,1,2,3",
464
419
"EventCode": "0xB7, 0xBB",
465
420
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
466
421
"MSRIndex": "0x1a6,0x1a7",
···
471
424
},
472
425
{
473
426
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
427
+
"Counter": "0,1,2,3",
474
428
"EventCode": "0xB7, 0xBB",
475
429
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
476
430
"MSRIndex": "0x1a6,0x1a7",
···
481
433
},
482
434
{
483
435
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
436
+
"Counter": "0,1,2,3",
484
437
"EventCode": "0xB7, 0xBB",
485
438
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
486
439
"MSRIndex": "0x1a6,0x1a7",
···
491
442
},
492
443
{
493
444
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
445
+
"Counter": "0,1,2,3",
494
446
"EventCode": "0xB7, 0xBB",
495
447
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
496
448
"MSRIndex": "0x1a6,0x1a7",
···
501
451
},
502
452
{
503
453
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
454
+
"Counter": "0,1,2,3",
504
455
"EventCode": "0xB7, 0xBB",
505
456
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
506
457
"MSRIndex": "0x1a6,0x1a7",
···
511
460
},
512
461
{
513
462
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
463
+
"Counter": "0,1,2,3",
514
464
"EventCode": "0xB7, 0xBB",
515
465
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
516
466
"MSRIndex": "0x1a6,0x1a7",
···
521
469
},
522
470
{
523
471
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
472
+
"Counter": "0,1,2,3",
524
473
"EventCode": "0xB7, 0xBB",
525
474
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
526
475
"MSRIndex": "0x1a6,0x1a7",
···
531
478
},
532
479
{
533
480
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
481
+
"Counter": "0,1,2,3",
534
482
"EventCode": "0xB7, 0xBB",
535
483
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
536
484
"MSRIndex": "0x1a6,0x1a7",
···
541
487
},
542
488
{
543
489
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
490
+
"Counter": "0,1,2,3",
544
491
"EventCode": "0xB7, 0xBB",
545
492
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
546
493
"MSRIndex": "0x1a6,0x1a7",
···
551
496
},
552
497
{
553
498
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
499
+
"Counter": "0,1,2,3",
554
500
"EventCode": "0xB7, 0xBB",
555
501
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
556
502
"MSRIndex": "0x1a6,0x1a7",
···
561
505
},
562
506
{
563
507
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
508
+
"Counter": "0,1,2,3",
564
509
"EventCode": "0xB7, 0xBB",
565
510
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
566
511
"MSRIndex": "0x1a6,0x1a7",
···
571
514
},
572
515
{
573
516
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
517
+
"Counter": "0,1,2,3",
574
518
"EventCode": "0xB7, 0xBB",
575
519
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
576
520
"MSRIndex": "0x1a6,0x1a7",
···
581
523
},
582
524
{
583
525
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
526
+
"Counter": "0,1,2,3",
584
527
"EventCode": "0xB7, 0xBB",
585
528
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
586
529
"MSRIndex": "0x1a6,0x1a7",
···
591
532
},
592
533
{
593
534
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
535
+
"Counter": "0,1,2,3",
594
536
"EventCode": "0xB7, 0xBB",
595
537
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
596
538
"MSRIndex": "0x1a6,0x1a7",
···
601
541
},
602
542
{
603
543
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
544
+
"Counter": "0,1,2,3",
604
545
"EventCode": "0xB7, 0xBB",
605
546
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
606
547
"MSRIndex": "0x1a6,0x1a7",
···
611
550
},
612
551
{
613
552
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
553
+
"Counter": "0,1,2,3",
614
554
"EventCode": "0xB7, 0xBB",
615
555
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
616
556
"MSRIndex": "0x1a6,0x1a7",
···
621
559
},
622
560
{
623
561
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
562
+
"Counter": "0,1,2,3",
624
563
"EventCode": "0xB7, 0xBB",
625
564
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
626
565
"MSRIndex": "0x1a6,0x1a7",
···
631
568
},
632
569
{
633
570
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
571
+
"Counter": "0,1,2,3",
634
572
"EventCode": "0xB7, 0xBB",
635
573
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
636
574
"MSRIndex": "0x1a6,0x1a7",
···
641
577
},
642
578
{
643
579
"BriefDescription": "Offcore prefetch requests that missed the LLC",
580
+
"Counter": "0,1,2,3",
644
581
"EventCode": "0xB7, 0xBB",
645
582
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
646
583
"MSRIndex": "0x1a6,0x1a7",
···
651
586
},
652
587
{
653
588
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
589
+
"Counter": "0,1,2,3",
654
590
"EventCode": "0xB7, 0xBB",
655
591
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
656
592
"MSRIndex": "0x1a6,0x1a7",
···
661
595
},
662
596
{
663
597
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
598
+
"Counter": "0,1,2,3",
664
599
"EventCode": "0xB7, 0xBB",
665
600
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
666
601
"MSRIndex": "0x1a6,0x1a7",
+28
tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
+28
tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "ES segment renames",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xD5",
5
6
"EventName": "ES_REG_RENAMES",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "I/O transactions",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x6C",
13
13
"EventName": "IO_TRANSACTIONS",
14
14
"SampleAfterValue": "2000000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "L1I instruction fetch stall cycles",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x80",
21
20
"EventName": "L1I.CYCLES_STALLED",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "L1I instruction fetch hits",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x80",
29
27
"EventName": "L1I.HITS",
30
28
"SampleAfterValue": "2000000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "L1I instruction fetch misses",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x80",
37
34
"EventName": "L1I.MISSES",
38
35
"SampleAfterValue": "2000000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "L1I Instruction fetches",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x80",
45
41
"EventName": "L1I.READS",
46
42
"SampleAfterValue": "2000000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "Large ITLB hit",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x82",
53
48
"EventName": "LARGE_ITLB.HIT",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "Loads that partially overlap an earlier store",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0x3",
61
55
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "All loads dispatched",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x13",
69
62
"EventName": "LOAD_DISPATCH.ANY",
70
63
"SampleAfterValue": "2000000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "Loads dispatched from the MOB",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x13",
77
69
"EventName": "LOAD_DISPATCH.MOB",
78
70
"SampleAfterValue": "2000000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "Loads dispatched that bypass the MOB",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x13",
85
76
"EventName": "LOAD_DISPATCH.RS",
86
77
"SampleAfterValue": "2000000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "Loads dispatched from stage 305",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0x13",
93
83
"EventName": "LOAD_DISPATCH.RS_DELAYED",
94
84
"SampleAfterValue": "2000000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "False dependencies due to partial address aliasing",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x7",
101
90
"EventName": "PARTIAL_ADDRESS_ALIAS",
102
91
"SampleAfterValue": "200000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "All Store buffer stall cycles",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0x4",
109
97
"EventName": "SB_DRAIN.ANY",
110
98
"SampleAfterValue": "200000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "Segment rename stall cycles",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0xD4",
117
104
"EventName": "SEG_RENAME_STALLS",
118
105
"SampleAfterValue": "2000000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "Snoop code requests",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0xB4",
125
111
"EventName": "SNOOPQ_REQUESTS.CODE",
126
112
"SampleAfterValue": "100000",
···
129
113
},
130
114
{
131
115
"BriefDescription": "Snoop data requests",
116
+
"Counter": "0,1,2,3",
132
117
"EventCode": "0xB4",
133
118
"EventName": "SNOOPQ_REQUESTS.DATA",
134
119
"SampleAfterValue": "100000",
···
137
120
},
138
121
{
139
122
"BriefDescription": "Snoop invalidate requests",
123
+
"Counter": "0,1,2,3",
140
124
"EventCode": "0xB4",
141
125
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
142
126
"SampleAfterValue": "100000",
···
145
127
},
146
128
{
147
129
"BriefDescription": "Outstanding snoop code requests",
130
+
"Counter": "0",
148
131
"EventCode": "0xB3",
149
132
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
150
133
"SampleAfterValue": "2000000",
···
153
134
},
154
135
{
155
136
"BriefDescription": "Cycles snoop code requests queued",
137
+
"Counter": "0",
156
138
"CounterMask": "1",
157
139
"EventCode": "0xB3",
158
140
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
···
162
142
},
163
143
{
164
144
"BriefDescription": "Outstanding snoop data requests",
145
+
"Counter": "0",
165
146
"EventCode": "0xB3",
166
147
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
167
148
"SampleAfterValue": "2000000",
···
170
149
},
171
150
{
172
151
"BriefDescription": "Cycles snoop data requests queued",
152
+
"Counter": "0",
173
153
"CounterMask": "1",
174
154
"EventCode": "0xB3",
175
155
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
···
179
157
},
180
158
{
181
159
"BriefDescription": "Outstanding snoop invalidate requests",
160
+
"Counter": "0",
182
161
"EventCode": "0xB3",
183
162
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
184
163
"SampleAfterValue": "2000000",
···
187
164
},
188
165
{
189
166
"BriefDescription": "Cycles snoop invalidate requests queued",
167
+
"Counter": "0",
190
168
"CounterMask": "1",
191
169
"EventCode": "0xB3",
192
170
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
···
196
172
},
197
173
{
198
174
"BriefDescription": "Thread responded HIT to snoop",
175
+
"Counter": "0,1,2,3",
199
176
"EventCode": "0xB8",
200
177
"EventName": "SNOOP_RESPONSE.HIT",
201
178
"SampleAfterValue": "100000",
···
204
179
},
205
180
{
206
181
"BriefDescription": "Thread responded HITE to snoop",
182
+
"Counter": "0,1,2,3",
207
183
"EventCode": "0xB8",
208
184
"EventName": "SNOOP_RESPONSE.HITE",
209
185
"SampleAfterValue": "100000",
···
212
186
},
213
187
{
214
188
"BriefDescription": "Thread responded HITM to snoop",
189
+
"Counter": "0,1,2,3",
215
190
"EventCode": "0xB8",
216
191
"EventName": "SNOOP_RESPONSE.HITM",
217
192
"SampleAfterValue": "100000",
···
220
193
},
221
194
{
222
195
"BriefDescription": "Super Queue full stall cycles",
196
+
"Counter": "0,1,2,3",
223
197
"EventCode": "0xF6",
224
198
"EventName": "SQ_FULL_STALL_CYCLES",
225
199
"SampleAfterValue": "2000000",
+111
tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
+111
tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles the divider is busy",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x14",
5
6
"EventName": "ARITH.CYCLES_DIV_BUSY",
6
7
"SampleAfterValue": "2000000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Divide Operations executed",
11
+
"Counter": "0,1,2,3",
12
12
"CounterMask": "1",
13
13
"EdgeDetect": "1",
14
14
"EventCode": "0x14",
···
20
18
},
21
19
{
22
20
"BriefDescription": "Multiply operations executed",
21
+
"Counter": "0,1,2,3",
23
22
"EventCode": "0x14",
24
23
"EventName": "ARITH.MUL",
25
24
"SampleAfterValue": "2000000",
···
28
25
},
29
26
{
30
27
"BriefDescription": "BACLEAR asserted with bad target address",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0xE6",
32
30
"EventName": "BACLEAR.BAD_TARGET",
33
31
"SampleAfterValue": "2000000",
···
36
32
},
37
33
{
38
34
"BriefDescription": "BACLEAR asserted, regardless of cause",
35
+
"Counter": "0,1,2,3",
39
36
"EventCode": "0xE6",
40
37
"EventName": "BACLEAR.CLEAR",
41
38
"SampleAfterValue": "2000000",
···
44
39
},
45
40
{
46
41
"BriefDescription": "Instruction queue forced BACLEAR",
42
+
"Counter": "0,1,2,3",
47
43
"EventCode": "0xA7",
48
44
"EventName": "BACLEAR_FORCE_IQ",
49
45
"SampleAfterValue": "2000000",
···
52
46
},
53
47
{
54
48
"BriefDescription": "Early Branch Prediciton Unit clears",
49
+
"Counter": "0,1,2,3",
55
50
"EventCode": "0xE8",
56
51
"EventName": "BPU_CLEARS.EARLY",
57
52
"SampleAfterValue": "2000000",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Late Branch Prediction Unit clears",
56
+
"Counter": "0,1,2,3",
63
57
"EventCode": "0xE8",
64
58
"EventName": "BPU_CLEARS.LATE",
65
59
"SampleAfterValue": "2000000",
···
68
60
},
69
61
{
70
62
"BriefDescription": "Branch prediction unit missed call or return",
63
+
"Counter": "0,1,2,3",
71
64
"EventCode": "0xE5",
72
65
"EventName": "BPU_MISSED_CALL_RET",
73
66
"SampleAfterValue": "2000000",
···
76
67
},
77
68
{
78
69
"BriefDescription": "Branch instructions decoded",
70
+
"Counter": "0,1,2,3",
79
71
"EventCode": "0xE0",
80
72
"EventName": "BR_INST_DECODED",
81
73
"SampleAfterValue": "2000000",
···
84
74
},
85
75
{
86
76
"BriefDescription": "Branch instructions executed",
77
+
"Counter": "0,1,2,3",
87
78
"EventCode": "0x88",
88
79
"EventName": "BR_INST_EXEC.ANY",
89
80
"SampleAfterValue": "200000",
···
92
81
},
93
82
{
94
83
"BriefDescription": "Conditional branch instructions executed",
84
+
"Counter": "0,1,2,3",
95
85
"EventCode": "0x88",
96
86
"EventName": "BR_INST_EXEC.COND",
97
87
"SampleAfterValue": "200000",
···
100
88
},
101
89
{
102
90
"BriefDescription": "Unconditional branches executed",
91
+
"Counter": "0,1,2,3",
103
92
"EventCode": "0x88",
104
93
"EventName": "BR_INST_EXEC.DIRECT",
105
94
"SampleAfterValue": "200000",
···
108
95
},
109
96
{
110
97
"BriefDescription": "Unconditional call branches executed",
98
+
"Counter": "0,1,2,3",
111
99
"EventCode": "0x88",
112
100
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
113
101
"SampleAfterValue": "20000",
···
116
102
},
117
103
{
118
104
"BriefDescription": "Indirect call branches executed",
105
+
"Counter": "0,1,2,3",
119
106
"EventCode": "0x88",
120
107
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
121
108
"SampleAfterValue": "20000",
···
124
109
},
125
110
{
126
111
"BriefDescription": "Indirect non call branches executed",
112
+
"Counter": "0,1,2,3",
127
113
"EventCode": "0x88",
128
114
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
129
115
"SampleAfterValue": "20000",
···
132
116
},
133
117
{
134
118
"BriefDescription": "Call branches executed",
119
+
"Counter": "0,1,2,3",
135
120
"EventCode": "0x88",
136
121
"EventName": "BR_INST_EXEC.NEAR_CALLS",
137
122
"SampleAfterValue": "20000",
···
140
123
},
141
124
{
142
125
"BriefDescription": "All non call branches executed",
126
+
"Counter": "0,1,2,3",
143
127
"EventCode": "0x88",
144
128
"EventName": "BR_INST_EXEC.NON_CALLS",
145
129
"SampleAfterValue": "200000",
···
148
130
},
149
131
{
150
132
"BriefDescription": "Indirect return branches executed",
133
+
"Counter": "0,1,2,3",
151
134
"EventCode": "0x88",
152
135
"EventName": "BR_INST_EXEC.RETURN_NEAR",
153
136
"SampleAfterValue": "20000",
···
156
137
},
157
138
{
158
139
"BriefDescription": "Taken branches executed",
140
+
"Counter": "0,1,2,3",
159
141
"EventCode": "0x88",
160
142
"EventName": "BR_INST_EXEC.TAKEN",
161
143
"SampleAfterValue": "200000",
···
164
144
},
165
145
{
166
146
"BriefDescription": "Retired branch instructions (Precise Event)",
147
+
"Counter": "0,1,2,3",
167
148
"EventCode": "0xC4",
168
149
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
169
150
"PEBS": "1",
···
173
152
},
174
153
{
175
154
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
155
+
"Counter": "0,1,2,3",
176
156
"EventCode": "0xC4",
177
157
"EventName": "BR_INST_RETIRED.CONDITIONAL",
178
158
"PEBS": "1",
···
182
160
},
183
161
{
184
162
"BriefDescription": "Retired near call instructions (Precise Event)",
163
+
"Counter": "0,1,2,3",
185
164
"EventCode": "0xC4",
186
165
"EventName": "BR_INST_RETIRED.NEAR_CALL",
187
166
"PEBS": "1",
···
191
168
},
192
169
{
193
170
"BriefDescription": "Mispredicted branches executed",
171
+
"Counter": "0,1,2,3",
194
172
"EventCode": "0x89",
195
173
"EventName": "BR_MISP_EXEC.ANY",
196
174
"SampleAfterValue": "20000",
···
199
175
},
200
176
{
201
177
"BriefDescription": "Mispredicted conditional branches executed",
178
+
"Counter": "0,1,2,3",
202
179
"EventCode": "0x89",
203
180
"EventName": "BR_MISP_EXEC.COND",
204
181
"SampleAfterValue": "20000",
···
207
182
},
208
183
{
209
184
"BriefDescription": "Mispredicted unconditional branches executed",
185
+
"Counter": "0,1,2,3",
210
186
"EventCode": "0x89",
211
187
"EventName": "BR_MISP_EXEC.DIRECT",
212
188
"SampleAfterValue": "20000",
···
215
189
},
216
190
{
217
191
"BriefDescription": "Mispredicted non call branches executed",
192
+
"Counter": "0,1,2,3",
218
193
"EventCode": "0x89",
219
194
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
220
195
"SampleAfterValue": "2000",
···
223
196
},
224
197
{
225
198
"BriefDescription": "Mispredicted indirect call branches executed",
199
+
"Counter": "0,1,2,3",
226
200
"EventCode": "0x89",
227
201
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
228
202
"SampleAfterValue": "2000",
···
231
203
},
232
204
{
233
205
"BriefDescription": "Mispredicted indirect non call branches executed",
206
+
"Counter": "0,1,2,3",
234
207
"EventCode": "0x89",
235
208
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
236
209
"SampleAfterValue": "2000",
···
239
210
},
240
211
{
241
212
"BriefDescription": "Mispredicted call branches executed",
213
+
"Counter": "0,1,2,3",
242
214
"EventCode": "0x89",
243
215
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
244
216
"SampleAfterValue": "2000",
···
247
217
},
248
218
{
249
219
"BriefDescription": "Mispredicted non call branches executed",
220
+
"Counter": "0,1,2,3",
250
221
"EventCode": "0x89",
251
222
"EventName": "BR_MISP_EXEC.NON_CALLS",
252
223
"SampleAfterValue": "20000",
···
255
224
},
256
225
{
257
226
"BriefDescription": "Mispredicted return branches executed",
227
+
"Counter": "0,1,2,3",
258
228
"EventCode": "0x89",
259
229
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
260
230
"SampleAfterValue": "2000",
···
263
231
},
264
232
{
265
233
"BriefDescription": "Mispredicted taken branches executed",
234
+
"Counter": "0,1,2,3",
266
235
"EventCode": "0x89",
267
236
"EventName": "BR_MISP_EXEC.TAKEN",
268
237
"SampleAfterValue": "20000",
···
271
238
},
272
239
{
273
240
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
241
+
"Counter": "0,1,2,3",
274
242
"EventCode": "0xC5",
275
243
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
276
244
"PEBS": "1",
···
280
246
},
281
247
{
282
248
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
249
+
"Counter": "0,1,2,3",
283
250
"EventCode": "0xC5",
284
251
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
285
252
"PEBS": "1",
···
289
254
},
290
255
{
291
256
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
257
+
"Counter": "0,1,2,3",
292
258
"EventCode": "0xC5",
293
259
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
294
260
"PEBS": "1",
···
298
262
},
299
263
{
300
264
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
265
+
"Counter": "Fixed counter 3",
301
266
"EventName": "CPU_CLK_UNHALTED.REF",
302
267
"SampleAfterValue": "2000000"
303
268
},
304
269
{
305
270
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
271
+
"Counter": "0,1,2,3",
306
272
"EventCode": "0x3C",
307
273
"EventName": "CPU_CLK_UNHALTED.REF_P",
308
274
"SampleAfterValue": "100000",
···
312
274
},
313
275
{
314
276
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
277
+
"Counter": "Fixed counter 2",
315
278
"EventName": "CPU_CLK_UNHALTED.THREAD",
316
279
"SampleAfterValue": "2000000"
317
280
},
318
281
{
319
282
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
283
+
"Counter": "0,1,2,3",
320
284
"EventCode": "0x3C",
321
285
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
322
286
"SampleAfterValue": "2000000"
323
287
},
324
288
{
325
289
"BriefDescription": "Total CPU cycles",
290
+
"Counter": "0,1,2,3",
326
291
"CounterMask": "2",
327
292
"EventCode": "0x3C",
328
293
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
···
334
293
},
335
294
{
336
295
"BriefDescription": "Any Instruction Length Decoder stall cycles",
296
+
"Counter": "0,1,2,3",
337
297
"EventCode": "0x87",
338
298
"EventName": "ILD_STALL.ANY",
339
299
"SampleAfterValue": "2000000",
···
342
300
},
343
301
{
344
302
"BriefDescription": "Instruction Queue full stall cycles",
303
+
"Counter": "0,1,2,3",
345
304
"EventCode": "0x87",
346
305
"EventName": "ILD_STALL.IQ_FULL",
347
306
"SampleAfterValue": "2000000",
···
350
307
},
351
308
{
352
309
"BriefDescription": "Length Change Prefix stall cycles",
310
+
"Counter": "0,1,2,3",
353
311
"EventCode": "0x87",
354
312
"EventName": "ILD_STALL.LCP",
355
313
"SampleAfterValue": "2000000",
···
358
314
},
359
315
{
360
316
"BriefDescription": "Stall cycles due to BPU MRU bypass",
317
+
"Counter": "0,1,2,3",
361
318
"EventCode": "0x87",
362
319
"EventName": "ILD_STALL.MRU",
363
320
"SampleAfterValue": "2000000",
···
366
321
},
367
322
{
368
323
"BriefDescription": "Regen stall cycles",
324
+
"Counter": "0,1,2,3",
369
325
"EventCode": "0x87",
370
326
"EventName": "ILD_STALL.REGEN",
371
327
"SampleAfterValue": "2000000",
···
374
328
},
375
329
{
376
330
"BriefDescription": "Instructions that must be decoded by decoder 0",
331
+
"Counter": "0,1,2,3",
377
332
"EventCode": "0x18",
378
333
"EventName": "INST_DECODED.DEC0",
379
334
"SampleAfterValue": "2000000",
···
382
335
},
383
336
{
384
337
"BriefDescription": "Instructions written to instruction queue.",
338
+
"Counter": "0,1,2,3",
385
339
"EventCode": "0x17",
386
340
"EventName": "INST_QUEUE_WRITES",
387
341
"SampleAfterValue": "2000000",
···
390
342
},
391
343
{
392
344
"BriefDescription": "Cycles instructions are written to the instruction queue",
345
+
"Counter": "0,1,2,3",
393
346
"EventCode": "0x1E",
394
347
"EventName": "INST_QUEUE_WRITE_CYCLES",
395
348
"SampleAfterValue": "2000000",
···
398
349
},
399
350
{
400
351
"BriefDescription": "Instructions retired (fixed counter)",
352
+
"Counter": "Fixed counter 1",
401
353
"EventName": "INST_RETIRED.ANY",
402
354
"SampleAfterValue": "2000000"
403
355
},
404
356
{
405
357
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
358
+
"Counter": "0,1,2,3",
406
359
"EventCode": "0xC0",
407
360
"EventName": "INST_RETIRED.ANY_P",
408
361
"PEBS": "1",
···
413
362
},
414
363
{
415
364
"BriefDescription": "Retired MMX instructions (Precise Event)",
365
+
"Counter": "0,1,2,3",
416
366
"EventCode": "0xC0",
417
367
"EventName": "INST_RETIRED.MMX",
418
368
"PEBS": "1",
···
422
370
},
423
371
{
424
372
"BriefDescription": "Total cycles (Precise Event)",
373
+
"Counter": "0,1,2,3",
425
374
"CounterMask": "16",
426
375
"EventCode": "0xC0",
427
376
"EventName": "INST_RETIRED.TOTAL_CYCLES",
···
433
380
},
434
381
{
435
382
"BriefDescription": "Total cycles (Precise Event)",
383
+
"Counter": "0,1,2,3",
436
384
"CounterMask": "16",
437
385
"EventCode": "0xC0",
438
386
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
···
444
390
},
445
391
{
446
392
"BriefDescription": "Retired floating-point operations (Precise Event)",
393
+
"Counter": "0,1,2,3",
447
394
"EventCode": "0xC0",
448
395
"EventName": "INST_RETIRED.X87",
449
396
"PEBS": "1",
···
453
398
},
454
399
{
455
400
"BriefDescription": "Load operations conflicting with software prefetches",
401
+
"Counter": "0,1",
456
402
"EventCode": "0x4C",
457
403
"EventName": "LOAD_HIT_PRE",
458
404
"SampleAfterValue": "200000",
···
461
405
},
462
406
{
463
407
"BriefDescription": "Cycles when uops were delivered by the LSD",
408
+
"Counter": "0,1,2,3",
464
409
"CounterMask": "1",
465
410
"EventCode": "0xA8",
466
411
"EventName": "LSD.ACTIVE",
···
470
413
},
471
414
{
472
415
"BriefDescription": "Cycles no uops were delivered by the LSD",
416
+
"Counter": "0,1,2,3",
473
417
"CounterMask": "1",
474
418
"EventCode": "0xA8",
475
419
"EventName": "LSD.INACTIVE",
···
480
422
},
481
423
{
482
424
"BriefDescription": "Loops that can't stream from the instruction queue",
425
+
"Counter": "0,1,2,3",
483
426
"EventCode": "0x20",
484
427
"EventName": "LSD_OVERFLOW",
485
428
"SampleAfterValue": "2000000",
···
488
429
},
489
430
{
490
431
"BriefDescription": "Cycles machine clear asserted",
432
+
"Counter": "0,1,2,3",
491
433
"EventCode": "0xC3",
492
434
"EventName": "MACHINE_CLEARS.CYCLES",
493
435
"SampleAfterValue": "20000",
···
496
436
},
497
437
{
498
438
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
439
+
"Counter": "0,1,2,3",
499
440
"EventCode": "0xC3",
500
441
"EventName": "MACHINE_CLEARS.MEM_ORDER",
501
442
"SampleAfterValue": "20000",
···
504
443
},
505
444
{
506
445
"BriefDescription": "Self-Modifying Code detected",
446
+
"Counter": "0,1,2,3",
507
447
"EventCode": "0xC3",
508
448
"EventName": "MACHINE_CLEARS.SMC",
509
449
"SampleAfterValue": "20000",
···
512
450
},
513
451
{
514
452
"BriefDescription": "All RAT stall cycles",
453
+
"Counter": "0,1,2,3",
515
454
"EventCode": "0xD2",
516
455
"EventName": "RAT_STALLS.ANY",
517
456
"SampleAfterValue": "2000000",
···
520
457
},
521
458
{
522
459
"BriefDescription": "Flag stall cycles",
460
+
"Counter": "0,1,2,3",
523
461
"EventCode": "0xD2",
524
462
"EventName": "RAT_STALLS.FLAGS",
525
463
"SampleAfterValue": "2000000",
···
528
464
},
529
465
{
530
466
"BriefDescription": "Partial register stall cycles",
467
+
"Counter": "0,1,2,3",
531
468
"EventCode": "0xD2",
532
469
"EventName": "RAT_STALLS.REGISTERS",
533
470
"SampleAfterValue": "2000000",
···
536
471
},
537
472
{
538
473
"BriefDescription": "ROB read port stalls cycles",
474
+
"Counter": "0,1,2,3",
539
475
"EventCode": "0xD2",
540
476
"EventName": "RAT_STALLS.ROB_READ_PORT",
541
477
"SampleAfterValue": "2000000",
···
544
478
},
545
479
{
546
480
"BriefDescription": "Scoreboard stall cycles",
481
+
"Counter": "0,1,2,3",
547
482
"EventCode": "0xD2",
548
483
"EventName": "RAT_STALLS.SCOREBOARD",
549
484
"SampleAfterValue": "2000000",
···
552
485
},
553
486
{
554
487
"BriefDescription": "Resource related stall cycles",
488
+
"Counter": "0,1,2,3",
555
489
"EventCode": "0xA2",
556
490
"EventName": "RESOURCE_STALLS.ANY",
557
491
"SampleAfterValue": "2000000",
···
560
492
},
561
493
{
562
494
"BriefDescription": "FPU control word write stall cycles",
495
+
"Counter": "0,1,2,3",
563
496
"EventCode": "0xA2",
564
497
"EventName": "RESOURCE_STALLS.FPCW",
565
498
"SampleAfterValue": "2000000",
···
568
499
},
569
500
{
570
501
"BriefDescription": "Load buffer stall cycles",
502
+
"Counter": "0,1,2,3",
571
503
"EventCode": "0xA2",
572
504
"EventName": "RESOURCE_STALLS.LOAD",
573
505
"SampleAfterValue": "2000000",
···
576
506
},
577
507
{
578
508
"BriefDescription": "MXCSR rename stall cycles",
509
+
"Counter": "0,1,2,3",
579
510
"EventCode": "0xA2",
580
511
"EventName": "RESOURCE_STALLS.MXCSR",
581
512
"SampleAfterValue": "2000000",
···
584
513
},
585
514
{
586
515
"BriefDescription": "Other Resource related stall cycles",
516
+
"Counter": "0,1,2,3",
587
517
"EventCode": "0xA2",
588
518
"EventName": "RESOURCE_STALLS.OTHER",
589
519
"SampleAfterValue": "2000000",
···
592
520
},
593
521
{
594
522
"BriefDescription": "ROB full stall cycles",
523
+
"Counter": "0,1,2,3",
595
524
"EventCode": "0xA2",
596
525
"EventName": "RESOURCE_STALLS.ROB_FULL",
597
526
"SampleAfterValue": "2000000",
···
600
527
},
601
528
{
602
529
"BriefDescription": "Reservation Station full stall cycles",
530
+
"Counter": "0,1,2,3",
603
531
"EventCode": "0xA2",
604
532
"EventName": "RESOURCE_STALLS.RS_FULL",
605
533
"SampleAfterValue": "2000000",
···
608
534
},
609
535
{
610
536
"BriefDescription": "Store buffer stall cycles",
537
+
"Counter": "0,1,2,3",
611
538
"EventCode": "0xA2",
612
539
"EventName": "RESOURCE_STALLS.STORE",
613
540
"SampleAfterValue": "2000000",
···
616
541
},
617
542
{
618
543
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
544
+
"Counter": "0,1,2,3",
619
545
"EventCode": "0xC7",
620
546
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
621
547
"PEBS": "1",
···
625
549
},
626
550
{
627
551
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
552
+
"Counter": "0,1,2,3",
628
553
"EventCode": "0xC7",
629
554
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
630
555
"PEBS": "1",
···
634
557
},
635
558
{
636
559
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
560
+
"Counter": "0,1,2,3",
637
561
"EventCode": "0xC7",
638
562
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
639
563
"PEBS": "1",
···
643
565
},
644
566
{
645
567
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
568
+
"Counter": "0,1,2,3",
646
569
"EventCode": "0xC7",
647
570
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
648
571
"PEBS": "1",
···
652
573
},
653
574
{
654
575
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
576
+
"Counter": "0,1,2,3",
655
577
"EventCode": "0xC7",
656
578
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
657
579
"PEBS": "1",
···
661
581
},
662
582
{
663
583
"BriefDescription": "Stack pointer instructions decoded",
584
+
"Counter": "0,1,2,3",
664
585
"EventCode": "0xD1",
665
586
"EventName": "UOPS_DECODED.ESP_FOLDING",
666
587
"SampleAfterValue": "2000000",
···
669
588
},
670
589
{
671
590
"BriefDescription": "Stack pointer sync operations",
591
+
"Counter": "0,1,2,3",
672
592
"EventCode": "0xD1",
673
593
"EventName": "UOPS_DECODED.ESP_SYNC",
674
594
"SampleAfterValue": "2000000",
···
677
595
},
678
596
{
679
597
"BriefDescription": "Uops decoded by Microcode Sequencer",
598
+
"Counter": "0,1,2,3",
680
599
"CounterMask": "1",
681
600
"EventCode": "0xD1",
682
601
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
···
686
603
},
687
604
{
688
605
"BriefDescription": "Cycles no Uops are decoded",
606
+
"Counter": "0,1,2,3",
689
607
"CounterMask": "1",
690
608
"EventCode": "0xD1",
691
609
"EventName": "UOPS_DECODED.STALL_CYCLES",
···
697
613
{
698
614
"AnyThread": "1",
699
615
"BriefDescription": "Cycles Uops executed on any port (core count)",
616
+
"Counter": "0,1,2,3",
700
617
"CounterMask": "1",
701
618
"EventCode": "0xB1",
702
619
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
···
707
622
{
708
623
"AnyThread": "1",
709
624
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
625
+
"Counter": "0,1,2,3",
710
626
"CounterMask": "1",
711
627
"EventCode": "0xB1",
712
628
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
···
717
631
{
718
632
"AnyThread": "1",
719
633
"BriefDescription": "Uops executed on any port (core count)",
634
+
"Counter": "0,1,2,3",
720
635
"CounterMask": "1",
721
636
"EdgeDetect": "1",
722
637
"EventCode": "0xB1",
···
729
642
{
730
643
"AnyThread": "1",
731
644
"BriefDescription": "Uops executed on ports 0-4 (core count)",
645
+
"Counter": "0,1,2,3",
732
646
"CounterMask": "1",
733
647
"EdgeDetect": "1",
734
648
"EventCode": "0xB1",
···
741
653
{
742
654
"AnyThread": "1",
743
655
"BriefDescription": "Cycles no Uops issued on any port (core count)",
656
+
"Counter": "0,1,2,3",
744
657
"CounterMask": "1",
745
658
"EventCode": "0xB1",
746
659
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
···
752
663
{
753
664
"AnyThread": "1",
754
665
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
666
+
"Counter": "0,1,2,3",
755
667
"CounterMask": "1",
756
668
"EventCode": "0xB1",
757
669
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
···
762
672
},
763
673
{
764
674
"BriefDescription": "Uops executed on port 0",
675
+
"Counter": "0,1,2,3",
765
676
"EventCode": "0xB1",
766
677
"EventName": "UOPS_EXECUTED.PORT0",
767
678
"SampleAfterValue": "2000000",
···
770
679
},
771
680
{
772
681
"BriefDescription": "Uops issued on ports 0, 1 or 5",
682
+
"Counter": "0,1,2,3",
773
683
"EventCode": "0xB1",
774
684
"EventName": "UOPS_EXECUTED.PORT015",
775
685
"SampleAfterValue": "2000000",
···
778
686
},
779
687
{
780
688
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
689
+
"Counter": "0,1,2,3",
781
690
"CounterMask": "1",
782
691
"EventCode": "0xB1",
783
692
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
···
788
695
},
789
696
{
790
697
"BriefDescription": "Uops executed on port 1",
698
+
"Counter": "0,1,2,3",
791
699
"EventCode": "0xB1",
792
700
"EventName": "UOPS_EXECUTED.PORT1",
793
701
"SampleAfterValue": "2000000",
···
797
703
{
798
704
"AnyThread": "1",
799
705
"BriefDescription": "Uops issued on ports 2, 3 or 4",
706
+
"Counter": "0,1,2,3",
800
707
"EventCode": "0xB1",
801
708
"EventName": "UOPS_EXECUTED.PORT234_CORE",
802
709
"SampleAfterValue": "2000000",
···
806
711
{
807
712
"AnyThread": "1",
808
713
"BriefDescription": "Uops executed on port 2 (core count)",
714
+
"Counter": "0,1,2,3",
809
715
"EventCode": "0xB1",
810
716
"EventName": "UOPS_EXECUTED.PORT2_CORE",
811
717
"SampleAfterValue": "2000000",
···
815
719
{
816
720
"AnyThread": "1",
817
721
"BriefDescription": "Uops executed on port 3 (core count)",
722
+
"Counter": "0,1,2,3",
818
723
"EventCode": "0xB1",
819
724
"EventName": "UOPS_EXECUTED.PORT3_CORE",
820
725
"SampleAfterValue": "2000000",
···
824
727
{
825
728
"AnyThread": "1",
826
729
"BriefDescription": "Uops executed on port 4 (core count)",
730
+
"Counter": "0,1,2,3",
827
731
"EventCode": "0xB1",
828
732
"EventName": "UOPS_EXECUTED.PORT4_CORE",
829
733
"SampleAfterValue": "2000000",
···
832
734
},
833
735
{
834
736
"BriefDescription": "Uops executed on port 5",
737
+
"Counter": "0,1,2,3",
835
738
"EventCode": "0xB1",
836
739
"EventName": "UOPS_EXECUTED.PORT5",
837
740
"SampleAfterValue": "2000000",
···
840
741
},
841
742
{
842
743
"BriefDescription": "Uops issued",
744
+
"Counter": "0,1,2,3",
843
745
"EventCode": "0xE",
844
746
"EventName": "UOPS_ISSUED.ANY",
845
747
"SampleAfterValue": "2000000",
···
849
749
{
850
750
"AnyThread": "1",
851
751
"BriefDescription": "Cycles no Uops were issued on any thread",
752
+
"Counter": "0,1,2,3",
852
753
"CounterMask": "1",
853
754
"EventCode": "0xE",
854
755
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
···
860
759
{
861
760
"AnyThread": "1",
862
761
"BriefDescription": "Cycles Uops were issued on either thread",
762
+
"Counter": "0,1,2,3",
863
763
"CounterMask": "1",
864
764
"EventCode": "0xE",
865
765
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
···
869
767
},
870
768
{
871
769
"BriefDescription": "Fused Uops issued",
770
+
"Counter": "0,1,2,3",
872
771
"EventCode": "0xE",
873
772
"EventName": "UOPS_ISSUED.FUSED",
874
773
"SampleAfterValue": "2000000",
···
877
774
},
878
775
{
879
776
"BriefDescription": "Cycles no Uops were issued",
777
+
"Counter": "0,1,2,3",
880
778
"CounterMask": "1",
881
779
"EventCode": "0xE",
882
780
"EventName": "UOPS_ISSUED.STALL_CYCLES",
···
887
783
},
888
784
{
889
785
"BriefDescription": "Cycles Uops are being retired",
786
+
"Counter": "0,1,2,3",
890
787
"CounterMask": "1",
891
788
"EventCode": "0xC2",
892
789
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
···
897
792
},
898
793
{
899
794
"BriefDescription": "Uops retired (Precise Event)",
795
+
"Counter": "0,1,2,3",
900
796
"EventCode": "0xC2",
901
797
"EventName": "UOPS_RETIRED.ANY",
902
798
"PEBS": "1",
···
906
800
},
907
801
{
908
802
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
803
+
"Counter": "0,1,2,3",
909
804
"EventCode": "0xC2",
910
805
"EventName": "UOPS_RETIRED.MACRO_FUSED",
911
806
"PEBS": "1",
···
915
808
},
916
809
{
917
810
"BriefDescription": "Retirement slots used (Precise Event)",
811
+
"Counter": "0,1,2,3",
918
812
"EventCode": "0xC2",
919
813
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
920
814
"PEBS": "1",
···
924
816
},
925
817
{
926
818
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
819
+
"Counter": "0,1,2,3",
927
820
"CounterMask": "1",
928
821
"EventCode": "0xC2",
929
822
"EventName": "UOPS_RETIRED.STALL_CYCLES",
···
935
826
},
936
827
{
937
828
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
829
+
"Counter": "0,1,2,3",
938
830
"CounterMask": "16",
939
831
"EventCode": "0xC2",
940
832
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
···
946
836
},
947
837
{
948
838
"BriefDescription": "Uop unfusions due to FP exceptions",
839
+
"Counter": "0,1,2,3",
949
840
"EventCode": "0xDB",
950
841
"EventName": "UOP_UNFUSION",
951
842
"SampleAfterValue": "2000000",
+18
tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
+18
tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "DTLB load misses",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x8",
5
6
"EventName": "DTLB_LOAD_MISSES.ANY",
6
7
"SampleAfterValue": "200000",
···
9
8
},
10
9
{
11
10
"BriefDescription": "DTLB load miss caused by low part of address",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x8",
13
13
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
14
14
"SampleAfterValue": "200000",
···
17
15
},
18
16
{
19
17
"BriefDescription": "DTLB second level hit",
18
+
"Counter": "0,1,2,3",
20
19
"EventCode": "0x8",
21
20
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
22
21
"SampleAfterValue": "2000000",
···
25
22
},
26
23
{
27
24
"BriefDescription": "DTLB load miss page walks complete",
25
+
"Counter": "0,1,2,3",
28
26
"EventCode": "0x8",
29
27
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
30
28
"SampleAfterValue": "200000",
···
33
29
},
34
30
{
35
31
"BriefDescription": "DTLB load miss page walk cycles",
32
+
"Counter": "0,1,2,3",
36
33
"EventCode": "0x8",
37
34
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
38
35
"SampleAfterValue": "200000",
···
41
36
},
42
37
{
43
38
"BriefDescription": "DTLB misses",
39
+
"Counter": "0,1,2,3",
44
40
"EventCode": "0x49",
45
41
"EventName": "DTLB_MISSES.ANY",
46
42
"SampleAfterValue": "200000",
···
49
43
},
50
44
{
51
45
"BriefDescription": "DTLB miss large page walks",
46
+
"Counter": "0,1,2,3",
52
47
"EventCode": "0x49",
53
48
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
54
49
"SampleAfterValue": "200000",
···
57
50
},
58
51
{
59
52
"BriefDescription": "DTLB first level misses but second level hit",
53
+
"Counter": "0,1,2,3",
60
54
"EventCode": "0x49",
61
55
"EventName": "DTLB_MISSES.STLB_HIT",
62
56
"SampleAfterValue": "200000",
···
65
57
},
66
58
{
67
59
"BriefDescription": "DTLB miss page walks",
60
+
"Counter": "0,1,2,3",
68
61
"EventCode": "0x49",
69
62
"EventName": "DTLB_MISSES.WALK_COMPLETED",
70
63
"SampleAfterValue": "200000",
···
73
64
},
74
65
{
75
66
"BriefDescription": "DTLB miss page walk cycles",
67
+
"Counter": "0,1,2,3",
76
68
"EventCode": "0x49",
77
69
"EventName": "DTLB_MISSES.WALK_CYCLES",
78
70
"SampleAfterValue": "2000000",
···
81
71
},
82
72
{
83
73
"BriefDescription": "Extended Page Table walk cycles",
74
+
"Counter": "0,1,2,3",
84
75
"EventCode": "0x4F",
85
76
"EventName": "EPT.WALK_CYCLES",
86
77
"SampleAfterValue": "2000000",
···
89
78
},
90
79
{
91
80
"BriefDescription": "ITLB flushes",
81
+
"Counter": "0,1,2,3",
92
82
"EventCode": "0xAE",
93
83
"EventName": "ITLB_FLUSH",
94
84
"SampleAfterValue": "2000000",
···
97
85
},
98
86
{
99
87
"BriefDescription": "ITLB miss",
88
+
"Counter": "0,1,2,3",
100
89
"EventCode": "0x85",
101
90
"EventName": "ITLB_MISSES.ANY",
102
91
"SampleAfterValue": "200000",
···
105
92
},
106
93
{
107
94
"BriefDescription": "ITLB miss page walks",
95
+
"Counter": "0,1,2,3",
108
96
"EventCode": "0x85",
109
97
"EventName": "ITLB_MISSES.WALK_COMPLETED",
110
98
"SampleAfterValue": "200000",
···
113
99
},
114
100
{
115
101
"BriefDescription": "ITLB miss page walk cycles",
102
+
"Counter": "0,1,2,3",
116
103
"EventCode": "0x85",
117
104
"EventName": "ITLB_MISSES.WALK_CYCLES",
118
105
"SampleAfterValue": "2000000",
···
121
106
},
122
107
{
123
108
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
109
+
"Counter": "0,1,2,3",
124
110
"EventCode": "0xC8",
125
111
"EventName": "ITLB_MISS_RETIRED",
126
112
"PEBS": "1",
···
130
114
},
131
115
{
132
116
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
117
+
"Counter": "0,1,2,3",
133
118
"EventCode": "0xCB",
134
119
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
135
120
"PEBS": "1",
···
139
122
},
140
123
{
141
124
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
125
+
"Counter": "0,1,2,3",
142
126
"EventCode": "0xC",
143
127
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
144
128
"PEBS": "1",