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clk: renesas: r9a09g077: Add TSU module clock

The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a TSU
peripheral which is controlled by a module clock.

The TSU module clock is enabled in register MSTPCRD (0x30c), at bit 7,
resulting in a (0x30c - 0x300) / 4 * 100 + 7 = 307 index.

Add it to the list of module clocks.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023081925.2412325-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Cosmin Tanislav and committed by
Geert Uytterhoeven 79276fb0 66a470ab

+1
+1
drivers/clk/renesas/r9a09g077-cpg.c
··· 191 191 DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH), 192 192 DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH), 193 193 DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM), 194 + DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL), 194 195 DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM), 195 196 DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM), 196 197 DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),