Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
media: i2c: imx290: Define more register macros
Define macros for all registers programmed by the driver for which
documentation is available to increase readability. This starts making
use of 16-bit registers in the register arrays, so the value field has
to be increased to 32 bits.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
authored by
Laurent Pinchart
and committed by
Sakari Ailus
79d99ae8
e611f3da
+124
-95
+124
-95
drivers/media/i2c/imx290.c
+124
-95
drivers/media/i2c/imx290.c
···
31
31
#define IMX290_STANDBY IMX290_REG_8BIT(0x3000)
32
32
#define IMX290_REGHOLD IMX290_REG_8BIT(0x3001)
33
33
#define IMX290_XMSTA IMX290_REG_8BIT(0x3002)
34
+
#define IMX290_ADBIT IMX290_REG_8BIT(0x3005)
35
+
#define IMX290_ADBIT_10BIT (0 << 0)
36
+
#define IMX290_ADBIT_12BIT (1 << 0)
37
+
#define IMX290_CTRL_07 IMX290_REG_8BIT(0x3007)
38
+
#define IMX290_VREVERSE BIT(0)
39
+
#define IMX290_HREVERSE BIT(1)
40
+
#define IMX290_WINMODE_1080P (0 << 4)
41
+
#define IMX290_WINMODE_720P (1 << 4)
42
+
#define IMX290_WINMODE_CROP (4 << 4)
34
43
#define IMX290_FR_FDG_SEL IMX290_REG_8BIT(0x3009)
35
44
#define IMX290_BLKLEVEL IMX290_REG_16BIT(0x300a)
36
45
#define IMX290_GAIN IMX290_REG_8BIT(0x3014)
46
+
#define IMX290_VMAX IMX290_REG_24BIT(0x3018)
37
47
#define IMX290_HMAX IMX290_REG_16BIT(0x301c)
48
+
#define IMX290_SHS1 IMX290_REG_24BIT(0x3020)
49
+
#define IMX290_WINWV_OB IMX290_REG_8BIT(0x303a)
50
+
#define IMX290_WINPV IMX290_REG_16BIT(0x303c)
51
+
#define IMX290_WINWV IMX290_REG_16BIT(0x303e)
52
+
#define IMX290_WINPH IMX290_REG_16BIT(0x3040)
53
+
#define IMX290_WINWH IMX290_REG_16BIT(0x3042)
54
+
#define IMX290_OUT_CTRL IMX290_REG_8BIT(0x3046)
55
+
#define IMX290_ODBIT_10BIT (0 << 0)
56
+
#define IMX290_ODBIT_12BIT (1 << 0)
57
+
#define IMX290_OPORTSEL_PARALLEL (0x0 << 4)
58
+
#define IMX290_OPORTSEL_LVDS_2CH (0xd << 4)
59
+
#define IMX290_OPORTSEL_LVDS_4CH (0xe << 4)
60
+
#define IMX290_OPORTSEL_LVDS_8CH (0xf << 4)
61
+
#define IMX290_XSOUTSEL IMX290_REG_8BIT(0x304b)
62
+
#define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0)
63
+
#define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0)
64
+
#define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2)
65
+
#define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2)
66
+
#define IMX290_INCKSEL1 IMX290_REG_8BIT(0x305c)
67
+
#define IMX290_INCKSEL2 IMX290_REG_8BIT(0x305d)
68
+
#define IMX290_INCKSEL3 IMX290_REG_8BIT(0x305e)
69
+
#define IMX290_INCKSEL4 IMX290_REG_8BIT(0x305f)
38
70
#define IMX290_PGCTRL IMX290_REG_8BIT(0x308c)
71
+
#define IMX290_ADBIT1 IMX290_REG_8BIT(0x3129)
72
+
#define IMX290_ADBIT1_10BIT 0x1d
73
+
#define IMX290_ADBIT1_12BIT 0x00
74
+
#define IMX290_INCKSEL5 IMX290_REG_8BIT(0x315e)
75
+
#define IMX290_INCKSEL6 IMX290_REG_8BIT(0x3164)
76
+
#define IMX290_ADBIT2 IMX290_REG_8BIT(0x317c)
77
+
#define IMX290_ADBIT2_10BIT 0x12
78
+
#define IMX290_ADBIT2_12BIT 0x00
39
79
#define IMX290_CHIP_ID IMX290_REG_16BIT(0x319a)
80
+
#define IMX290_ADBIT3 IMX290_REG_8BIT(0x31ec)
81
+
#define IMX290_ADBIT3_10BIT 0x37
82
+
#define IMX290_ADBIT3_12BIT 0x0e
83
+
#define IMX290_REPETITION IMX290_REG_8BIT(0x3405)
40
84
#define IMX290_PHY_LANE_NUM IMX290_REG_8BIT(0x3407)
85
+
#define IMX290_OPB_SIZE_V IMX290_REG_8BIT(0x3414)
86
+
#define IMX290_Y_OUT_SIZE IMX290_REG_16BIT(0x3418)
87
+
#define IMX290_CSI_DT_FMT IMX290_REG_16BIT(0x3441)
88
+
#define IMX290_CSI_DT_FMT_RAW10 0x0a0a
89
+
#define IMX290_CSI_DT_FMT_RAW12 0x0c0c
41
90
#define IMX290_CSI_LANE_MODE IMX290_REG_8BIT(0x3443)
91
+
#define IMX290_EXTCK_FREQ IMX290_REG_16BIT(0x3444)
92
+
#define IMX290_TCLKPOST IMX290_REG_16BIT(0x3446)
93
+
#define IMX290_THSZERO IMX290_REG_16BIT(0x3448)
94
+
#define IMX290_THSPREPARE IMX290_REG_16BIT(0x344a)
95
+
#define IMX290_TCLKTRAIL IMX290_REG_16BIT(0x344c)
96
+
#define IMX290_THSTRAIL IMX290_REG_16BIT(0x344e)
97
+
#define IMX290_TCLKZERO IMX290_REG_16BIT(0x3450)
98
+
#define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452)
99
+
#define IMX290_TLPX IMX290_REG_16BIT(0x3454)
100
+
#define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472)
42
101
43
102
#define IMX290_PGCTRL_REGEN BIT(0)
44
103
#define IMX290_PGCTRL_THRU BIT(1)
···
113
54
114
55
struct imx290_regval {
115
56
u32 reg;
116
-
u8 val;
57
+
u32 val;
117
58
};
118
59
119
60
struct imx290_mode {
···
175
116
};
176
117
177
118
static const struct imx290_regval imx290_global_init_settings[] = {
178
-
{ IMX290_REG_8BIT(0x3007), 0x00 },
179
-
{ IMX290_REG_8BIT(0x3018), 0x65 },
180
-
{ IMX290_REG_8BIT(0x3019), 0x04 },
181
-
{ IMX290_REG_8BIT(0x301a), 0x00 },
182
-
{ IMX290_REG_8BIT(0x3444), 0x20 },
183
-
{ IMX290_REG_8BIT(0x3445), 0x25 },
184
-
{ IMX290_REG_8BIT(0x303a), 0x0c },
185
-
{ IMX290_REG_8BIT(0x3040), 0x00 },
186
-
{ IMX290_REG_8BIT(0x3041), 0x00 },
187
-
{ IMX290_REG_8BIT(0x303c), 0x00 },
188
-
{ IMX290_REG_8BIT(0x303d), 0x00 },
189
-
{ IMX290_REG_8BIT(0x3042), 0x9c },
190
-
{ IMX290_REG_8BIT(0x3043), 0x07 },
191
-
{ IMX290_REG_8BIT(0x303e), 0x49 },
192
-
{ IMX290_REG_8BIT(0x303f), 0x04 },
193
-
{ IMX290_REG_8BIT(0x304b), 0x0a },
119
+
{ IMX290_CTRL_07, IMX290_WINMODE_1080P },
120
+
{ IMX290_VMAX, 1125 },
121
+
{ IMX290_EXTCK_FREQ, 0x2520 },
122
+
{ IMX290_WINWV_OB, 12 },
123
+
{ IMX290_WINPH, 0 },
124
+
{ IMX290_WINPV, 0 },
125
+
{ IMX290_WINWH, 1948 },
126
+
{ IMX290_WINWV, 1097 },
127
+
{ IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC |
128
+
IMX290_XSOUTSEL_XHSOUTSEL_HSYNC },
194
129
{ IMX290_REG_8BIT(0x300f), 0x00 },
195
130
{ IMX290_REG_8BIT(0x3010), 0x21 },
196
131
{ IMX290_REG_8BIT(0x3012), 0x64 },
···
230
177
231
178
static const struct imx290_regval imx290_1080p_settings[] = {
232
179
/* mode settings */
233
-
{ IMX290_REG_8BIT(0x3007), 0x00 },
234
-
{ IMX290_REG_8BIT(0x303a), 0x0c },
235
-
{ IMX290_REG_8BIT(0x3414), 0x0a },
236
-
{ IMX290_REG_8BIT(0x3472), 0x80 },
237
-
{ IMX290_REG_8BIT(0x3473), 0x07 },
238
-
{ IMX290_REG_8BIT(0x3418), 0x38 },
239
-
{ IMX290_REG_8BIT(0x3419), 0x04 },
180
+
{ IMX290_CTRL_07, IMX290_WINMODE_1080P },
181
+
{ IMX290_WINWV_OB, 12 },
182
+
{ IMX290_OPB_SIZE_V, 10 },
183
+
{ IMX290_X_OUT_SIZE, 1920 },
184
+
{ IMX290_Y_OUT_SIZE, 1080 },
240
185
{ IMX290_REG_8BIT(0x3012), 0x64 },
241
186
{ IMX290_REG_8BIT(0x3013), 0x00 },
242
-
{ IMX290_REG_8BIT(0x305c), 0x18 },
243
-
{ IMX290_REG_8BIT(0x305d), 0x03 },
244
-
{ IMX290_REG_8BIT(0x305e), 0x20 },
245
-
{ IMX290_REG_8BIT(0x305f), 0x01 },
246
-
{ IMX290_REG_8BIT(0x315e), 0x1a },
247
-
{ IMX290_REG_8BIT(0x3164), 0x1a },
187
+
{ IMX290_INCKSEL1, 0x18 },
188
+
{ IMX290_INCKSEL2, 0x03 },
189
+
{ IMX290_INCKSEL3, 0x20 },
190
+
{ IMX290_INCKSEL4, 0x01 },
191
+
{ IMX290_INCKSEL5, 0x1a },
192
+
{ IMX290_INCKSEL6, 0x1a },
248
193
{ IMX290_REG_8BIT(0x3480), 0x49 },
249
194
/* data rate settings */
250
-
{ IMX290_REG_8BIT(0x3405), 0x10 },
251
-
{ IMX290_REG_8BIT(0x3446), 0x57 },
252
-
{ IMX290_REG_8BIT(0x3447), 0x00 },
253
-
{ IMX290_REG_8BIT(0x3448), 0x37 },
254
-
{ IMX290_REG_8BIT(0x3449), 0x00 },
255
-
{ IMX290_REG_8BIT(0x344a), 0x1f },
256
-
{ IMX290_REG_8BIT(0x344b), 0x00 },
257
-
{ IMX290_REG_8BIT(0x344c), 0x1f },
258
-
{ IMX290_REG_8BIT(0x344d), 0x00 },
259
-
{ IMX290_REG_8BIT(0x344e), 0x1f },
260
-
{ IMX290_REG_8BIT(0x344f), 0x00 },
261
-
{ IMX290_REG_8BIT(0x3450), 0x77 },
262
-
{ IMX290_REG_8BIT(0x3451), 0x00 },
263
-
{ IMX290_REG_8BIT(0x3452), 0x1f },
264
-
{ IMX290_REG_8BIT(0x3453), 0x00 },
265
-
{ IMX290_REG_8BIT(0x3454), 0x17 },
266
-
{ IMX290_REG_8BIT(0x3455), 0x00 },
195
+
{ IMX290_REPETITION, 0x10 },
196
+
{ IMX290_TCLKPOST, 87 },
197
+
{ IMX290_THSZERO, 55 },
198
+
{ IMX290_THSPREPARE, 31 },
199
+
{ IMX290_TCLKTRAIL, 31 },
200
+
{ IMX290_THSTRAIL, 31 },
201
+
{ IMX290_TCLKZERO, 119 },
202
+
{ IMX290_TCLKPREPARE, 31 },
203
+
{ IMX290_TLPX, 23 },
267
204
};
268
205
269
206
static const struct imx290_regval imx290_720p_settings[] = {
270
207
/* mode settings */
271
-
{ IMX290_REG_8BIT(0x3007), 0x10 },
272
-
{ IMX290_REG_8BIT(0x303a), 0x06 },
273
-
{ IMX290_REG_8BIT(0x3414), 0x04 },
274
-
{ IMX290_REG_8BIT(0x3472), 0x00 },
275
-
{ IMX290_REG_8BIT(0x3473), 0x05 },
276
-
{ IMX290_REG_8BIT(0x3418), 0xd0 },
277
-
{ IMX290_REG_8BIT(0x3419), 0x02 },
208
+
{ IMX290_CTRL_07, IMX290_WINMODE_720P },
209
+
{ IMX290_WINWV_OB, 6 },
210
+
{ IMX290_OPB_SIZE_V, 4 },
211
+
{ IMX290_X_OUT_SIZE, 1280 },
212
+
{ IMX290_Y_OUT_SIZE, 720 },
278
213
{ IMX290_REG_8BIT(0x3012), 0x64 },
279
214
{ IMX290_REG_8BIT(0x3013), 0x00 },
280
-
{ IMX290_REG_8BIT(0x305c), 0x20 },
281
-
{ IMX290_REG_8BIT(0x305d), 0x00 },
282
-
{ IMX290_REG_8BIT(0x305e), 0x20 },
283
-
{ IMX290_REG_8BIT(0x305f), 0x01 },
284
-
{ IMX290_REG_8BIT(0x315e), 0x1a },
285
-
{ IMX290_REG_8BIT(0x3164), 0x1a },
215
+
{ IMX290_INCKSEL1, 0x20 },
216
+
{ IMX290_INCKSEL2, 0x00 },
217
+
{ IMX290_INCKSEL3, 0x20 },
218
+
{ IMX290_INCKSEL4, 0x01 },
219
+
{ IMX290_INCKSEL5, 0x1a },
220
+
{ IMX290_INCKSEL6, 0x1a },
286
221
{ IMX290_REG_8BIT(0x3480), 0x49 },
287
222
/* data rate settings */
288
-
{ IMX290_REG_8BIT(0x3405), 0x10 },
289
-
{ IMX290_REG_8BIT(0x3446), 0x4f },
290
-
{ IMX290_REG_8BIT(0x3447), 0x00 },
291
-
{ IMX290_REG_8BIT(0x3448), 0x2f },
292
-
{ IMX290_REG_8BIT(0x3449), 0x00 },
293
-
{ IMX290_REG_8BIT(0x344a), 0x17 },
294
-
{ IMX290_REG_8BIT(0x344b), 0x00 },
295
-
{ IMX290_REG_8BIT(0x344c), 0x17 },
296
-
{ IMX290_REG_8BIT(0x344d), 0x00 },
297
-
{ IMX290_REG_8BIT(0x344e), 0x17 },
298
-
{ IMX290_REG_8BIT(0x344f), 0x00 },
299
-
{ IMX290_REG_8BIT(0x3450), 0x57 },
300
-
{ IMX290_REG_8BIT(0x3451), 0x00 },
301
-
{ IMX290_REG_8BIT(0x3452), 0x17 },
302
-
{ IMX290_REG_8BIT(0x3453), 0x00 },
303
-
{ IMX290_REG_8BIT(0x3454), 0x17 },
304
-
{ IMX290_REG_8BIT(0x3455), 0x00 },
223
+
{ IMX290_REPETITION, 0x10 },
224
+
{ IMX290_TCLKPOST, 79 },
225
+
{ IMX290_THSZERO, 47 },
226
+
{ IMX290_THSPREPARE, 23 },
227
+
{ IMX290_TCLKTRAIL, 23 },
228
+
{ IMX290_THSTRAIL, 23 },
229
+
{ IMX290_TCLKZERO, 87 },
230
+
{ IMX290_TCLKPREPARE, 23 },
231
+
{ IMX290_TLPX, 23 },
305
232
};
306
233
307
234
static const struct imx290_regval imx290_10bit_settings[] = {
308
-
{ IMX290_REG_8BIT(0x3005), 0x00},
309
-
{ IMX290_REG_8BIT(0x3046), 0x00},
310
-
{ IMX290_REG_8BIT(0x3129), 0x1d},
311
-
{ IMX290_REG_8BIT(0x317c), 0x12},
312
-
{ IMX290_REG_8BIT(0x31ec), 0x37},
313
-
{ IMX290_REG_8BIT(0x3441), 0x0a},
314
-
{ IMX290_REG_8BIT(0x3442), 0x0a},
315
-
{ IMX290_REG_8BIT(0x300a), 0x3c},
316
-
{ IMX290_REG_8BIT(0x300b), 0x00},
235
+
{ IMX290_ADBIT, IMX290_ADBIT_10BIT },
236
+
{ IMX290_OUT_CTRL, IMX290_ODBIT_10BIT },
237
+
{ IMX290_ADBIT1, IMX290_ADBIT1_10BIT },
238
+
{ IMX290_ADBIT2, IMX290_ADBIT2_10BIT },
239
+
{ IMX290_ADBIT3, IMX290_ADBIT3_10BIT },
240
+
{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 },
241
+
{ IMX290_BLKLEVEL, 60 },
317
242
};
318
243
319
244
static const struct imx290_regval imx290_12bit_settings[] = {
320
-
{ IMX290_REG_8BIT(0x3005), 0x01 },
321
-
{ IMX290_REG_8BIT(0x3046), 0x01 },
322
-
{ IMX290_REG_8BIT(0x3129), 0x00 },
323
-
{ IMX290_REG_8BIT(0x317c), 0x00 },
324
-
{ IMX290_REG_8BIT(0x31ec), 0x0e },
325
-
{ IMX290_REG_8BIT(0x3441), 0x0c },
326
-
{ IMX290_REG_8BIT(0x3442), 0x0c },
327
-
{ IMX290_REG_8BIT(0x300a), 0xf0 },
328
-
{ IMX290_REG_8BIT(0x300b), 0x00 },
245
+
{ IMX290_ADBIT, IMX290_ADBIT_12BIT },
246
+
{ IMX290_OUT_CTRL, IMX290_ODBIT_12BIT },
247
+
{ IMX290_ADBIT1, IMX290_ADBIT1_12BIT },
248
+
{ IMX290_ADBIT2, IMX290_ADBIT2_12BIT },
249
+
{ IMX290_ADBIT3, IMX290_ADBIT3_12BIT },
250
+
{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 },
251
+
{ IMX290_BLKLEVEL, 240 },
329
252
};
330
253
331
254
/* supported link frequencies */