riscv: Add usercfi state for task and save/restore of CSR_SSP on trap entry/exit

Carve out space in the RISC-V architecture-specific thread struct for
cfi status and shadow stack in usermode.

This patch:
- defines a new structure cfi_status with status bit for cfi feature
- defines shadow stack pointer, base and size in cfi_status structure
- defines offsets to new member fields in thread in asm-offsets.c
- saves and restores shadow stack pointer on trap entry (U --> S) and exit
(S --> U)

Shadow stack save/restore is gated on feature availability and is
implemented using alternatives. CSR_SSP can be context-switched in
'switch_to' as well, but as soon as kernel shadow stack support gets
rolled in, the shadow stack pointer will need to be switched at trap
entry/exit point (much like 'sp'). It can be argued that a kernel
using a shadow stack deployment scenario may not be as prevalent as
user mode using this feature. But even if there is some minimal
deployment of kernel shadow stack, that means that it needs to be
supported. Thus save/restore of shadow stack pointer is implemented
in entry.S instead of in 'switch_to.h'.

Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6
Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com>
Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-5-b55691eacf4f@rivosinc.com
[pjw@kernel.org: cleaned up patch description]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

authored by

Deepak Gupta and committed by

Paul Walmsley 4 months ago 79dd4f2f 41a2452c

+62

5 changed files

expand all

arch

riscv

include

asm

processor.h

thread_info.h

usercfi.h

kernel

asm-offsets.c

entry.S

arch/riscv/include/asm/processor.h

··· 16 16 #include <asm/insn-def.h> 17 17 #include <asm/alternative-macros.h> 18 18 #include <asm/hwcap.h> 19 + #include <asm/usercfi.h> 19 20 20 21 #define arch_get_mmap_end(addr, len, flags) \ 21 22 ({ \

arch/riscv/include/asm/thread_info.h

··· 73 73 */ 74 74 unsigned long a0, a1, a2; 75 75 #endif 76 + #ifdef CONFIG_RISCV_USER_CFI 77 + struct cfi_state user_cfi_state; 78 + #endif 76 79 }; 77 80 78 81 #ifdef CONFIG_SHADOW_CALL_STACK

+23

arch/riscv/include/asm/usercfi.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 2 + * Copyright (C) 2024 Rivos, Inc. 3 + * Deepak Gupta <debug@rivosinc.com> 4 + */ 5 + #ifndef _ASM_RISCV_USERCFI_H 6 + #define _ASM_RISCV_USERCFI_H 7 + 8 + #ifndef __ASSEMBLER__ 9 + #include <linux/types.h> 10 + 11 + #ifdef CONFIG_RISCV_USER_CFI 12 + struct cfi_state { 13 + unsigned long ubcfi_en : 1; /* Enable for backward cfi. */ 14 + unsigned long user_shdw_stk; /* Current user shadow stack pointer */ 15 + unsigned long shdw_stk_base; /* Base address of shadow stack */ 16 + unsigned long shdw_stk_size; /* size of shadow stack */ 17 + }; 18 + 19 + #endif /* CONFIG_RISCV_USER_CFI */ 20 + 21 + #endif /* __ASSEMBLER__ */ 22 + 23 + #endif /* _ASM_RISCV_USERCFI_H */

arch/riscv/kernel/asm-offsets.c

··· 51 51 #endif 52 52 53 53 OFFSET(TASK_TI_CPU_NUM, task_struct, thread_info.cpu); 54 + #ifdef CONFIG_RISCV_USER_CFI 55 + OFFSET(TASK_TI_CFI_STATE, task_struct, thread_info.user_cfi_state); 56 + OFFSET(TASK_TI_USER_SSP, task_struct, thread_info.user_cfi_state.user_shdw_stk); 57 + #endif 54 58 OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]); 55 59 OFFSET(TASK_THREAD_F1, task_struct, thread.fstate.f[1]); 56 60 OFFSET(TASK_THREAD_F2, task_struct, thread.fstate.f[2]);

+31

arch/riscv/kernel/entry.S

··· 92 92 REG_L a0, TASK_TI_A0(tp) 93 93 .endm 94 94 95 + /* 96 + * If previous mode was U, capture shadow stack pointer and save it away 97 + * Zero CSR_SSP at the same time for sanitization. 98 + */ 99 + .macro save_userssp tmp, status 100 + ALTERNATIVE("nops(4)", 101 + __stringify( \ 102 + andi \tmp, \status, SR_SPP; \ 103 + bnez \tmp, skip_ssp_save; \ 104 + csrrw \tmp, CSR_SSP, x0; \ 105 + REG_S \tmp, TASK_TI_USER_SSP(tp); \ 106 + skip_ssp_save:), 107 + 0, 108 + RISCV_ISA_EXT_ZICFISS, 109 + CONFIG_RISCV_USER_CFI) 110 + .endm 111 + 112 + .macro restore_userssp tmp, status 113 + ALTERNATIVE("nops(4)", 114 + __stringify( \ 115 + andi \tmp, \status, SR_SPP; \ 116 + bnez \tmp, skip_ssp_restore; \ 117 + REG_L \tmp, TASK_TI_USER_SSP(tp); \ 118 + csrw CSR_SSP, \tmp; \ 119 + skip_ssp_restore:), 120 + 0, 121 + RISCV_ISA_EXT_ZICFISS, 122 + CONFIG_RISCV_USER_CFI) 123 + .endm 95 124 96 125 SYM_CODE_START(handle_exception) 97 126 /* ··· 177 148 178 149 REG_L s0, TASK_TI_USER_SP(tp) 179 150 csrrc s1, CSR_STATUS, t0 151 + save_userssp s2, s1 180 152 csrr s2, CSR_EPC 181 153 csrr s3, CSR_TVAL 182 154 csrr s4, CSR_CAUSE ··· 273 243 call riscv_v_context_nesting_end 274 244 #endif 275 245 REG_L a0, PT_STATUS(sp) 246 + restore_userssp s3, a0 276 247 /* 277 248 * The current load reservation is effectively part of the processor's 278 249 * state, in the sense that load reservations cannot be shared between

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