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mtd: rawnand: loongson1: Rename the prefix from ls1x to loongson

I am going to introduce the NAND controllers of the Loongson-2K series
CPUs, which are similar to Loongson-1.

As preparation, rename all prefixes from Loongson1-specific to
Loongson-generic.

No functional change intended.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

authored by

Binbin Zhou and committed by
Miquel Raynal 7a1e3a45 b2d2c2b8

+171 -164
+1 -1
MAINTAINERS
··· 16992 16992 F: arch/mips/include/asm/mach-loongson32/ 16993 16993 F: arch/mips/loongson32/ 16994 16994 F: drivers/*/*loongson1* 16995 - F: drivers/mtd/nand/raw/loongson1-nand-controller.c 16995 + F: drivers/mtd/nand/raw/loongson-nand-controller.c 16996 16996 F: drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c 16997 16997 F: sound/soc/loongson/loongson1_ac97.c 16998 16998
+3 -3
drivers/mtd/nand/raw/Kconfig
··· 436 436 Enables support for the NAND controller found on 437 437 the Nuvoton MA35 series SoCs. 438 438 439 - config MTD_NAND_LOONGSON1 440 - tristate "Loongson1 NAND controller" 439 + config MTD_NAND_LOONGSON 440 + tristate "Loongson NAND controller" 441 441 depends on LOONGSON1_APB_DMA || COMPILE_TEST 442 442 select REGMAP_MMIO 443 443 help 444 - Enables support for NAND controller on Loongson1 SoCs. 444 + Enables support for NAND controller on Loongson family chips. 445 445 446 446 comment "Misc" 447 447
+1 -1
drivers/mtd/nand/raw/Makefile
··· 58 58 obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o 59 59 obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o 60 60 obj-$(CONFIG_MTD_NAND_NUVOTON_MA35) += nuvoton-ma35d1-nand-controller.o 61 - obj-$(CONFIG_MTD_NAND_LOONGSON1) += loongson1-nand-controller.o 61 + obj-$(CONFIG_MTD_NAND_LOONGSON) += loongson-nand-controller.o 62 62 63 63 nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o 64 64 nand-objs += nand_onfi.o
+166 -159
drivers/mtd/nand/raw/loongson1-nand-controller.c drivers/mtd/nand/raw/loongson-nand-controller.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0-or-later 2 2 /* 3 - * NAND Controller Driver for Loongson-1 SoC 3 + * NAND Controller Driver for Loongson family chips 4 4 * 5 5 * Copyright (C) 2015-2025 Keguang Zhang <keguang.zhang@gmail.com> 6 6 */ ··· 17 17 #include <linux/regmap.h> 18 18 #include <linux/sizes.h> 19 19 20 - /* Loongson-1 NAND Controller Registers */ 21 - #define LS1X_NAND_CMD 0x0 22 - #define LS1X_NAND_ADDR1 0x4 23 - #define LS1X_NAND_ADDR2 0x8 24 - #define LS1X_NAND_TIMING 0xc 25 - #define LS1X_NAND_IDL 0x10 26 - #define LS1X_NAND_IDH_STATUS 0x14 27 - #define LS1X_NAND_PARAM 0x18 28 - #define LS1X_NAND_OP_NUM 0x1c 20 + /* Loongson NAND Controller Registers */ 21 + #define LOONGSON_NAND_CMD 0x0 22 + #define LOONGSON_NAND_ADDR1 0x4 23 + #define LOONGSON_NAND_ADDR2 0x8 24 + #define LOONGSON_NAND_TIMING 0xc 25 + #define LOONGSON_NAND_IDL 0x10 26 + #define LOONGSON_NAND_IDH_STATUS 0x14 27 + #define LOONGSON_NAND_PARAM 0x18 28 + #define LOONGSON_NAND_OP_NUM 0x1c 29 29 30 - /* NAND Command Register Bits */ 31 - #define LS1X_NAND_CMD_OP_DONE BIT(10) 32 - #define LS1X_NAND_CMD_OP_SPARE BIT(9) 33 - #define LS1X_NAND_CMD_OP_MAIN BIT(8) 34 - #define LS1X_NAND_CMD_STATUS BIT(7) 35 - #define LS1X_NAND_CMD_RESET BIT(6) 36 - #define LS1X_NAND_CMD_READID BIT(5) 37 - #define LS1X_NAND_CMD_BLOCKS_ERASE BIT(4) 38 - #define LS1X_NAND_CMD_ERASE BIT(3) 39 - #define LS1X_NAND_CMD_WRITE BIT(2) 40 - #define LS1X_NAND_CMD_READ BIT(1) 41 - #define LS1X_NAND_CMD_VALID BIT(0) 30 + /* Bitfields of nand command register */ 31 + #define LOONGSON_NAND_CMD_OP_DONE BIT(10) 32 + #define LOONGSON_NAND_CMD_OP_SPARE BIT(9) 33 + #define LOONGSON_NAND_CMD_OP_MAIN BIT(8) 34 + #define LOONGSON_NAND_CMD_STATUS BIT(7) 35 + #define LOONGSON_NAND_CMD_RESET BIT(6) 36 + #define LOONGSON_NAND_CMD_READID BIT(5) 37 + #define LOONGSON_NAND_CMD_BLOCKS_ERASE BIT(4) 38 + #define LOONGSON_NAND_CMD_ERASE BIT(3) 39 + #define LOONGSON_NAND_CMD_WRITE BIT(2) 40 + #define LOONGSON_NAND_CMD_READ BIT(1) 41 + #define LOONGSON_NAND_CMD_VALID BIT(0) 42 42 43 - #define LS1X_NAND_WAIT_CYCLE_MASK GENMASK(7, 0) 44 - #define LS1X_NAND_HOLD_CYCLE_MASK GENMASK(15, 8) 45 - #define LS1X_NAND_CELL_SIZE_MASK GENMASK(11, 8) 43 + /* Bitfields of nand timing register */ 44 + #define LOONGSON_NAND_WAIT_CYCLE_MASK GENMASK(7, 0) 45 + #define LOONGSON_NAND_HOLD_CYCLE_MASK GENMASK(15, 8) 46 46 47 - #define LS1X_NAND_COL_ADDR_CYC 2U 48 - #define LS1X_NAND_MAX_ADDR_CYC 5U 47 + /* Bitfields of nand parameter register */ 48 + #define LOONGSON_NAND_CELL_SIZE_MASK GENMASK(11, 8) 49 49 50 - #define BITS_PER_WORD (4 * BITS_PER_BYTE) 50 + #define LOONGSON_NAND_COL_ADDR_CYC 2U 51 + #define LOONGSON_NAND_MAX_ADDR_CYC 5U 51 52 52 - struct ls1x_nand_host; 53 + #define BITS_PER_WORD (4 * BITS_PER_BYTE) 53 54 54 - struct ls1x_nand_op { 55 - char addrs[LS1X_NAND_MAX_ADDR_CYC]; 55 + struct loongson_nand_host; 56 + 57 + struct loongson_nand_op { 58 + char addrs[LOONGSON_NAND_MAX_ADDR_CYC]; 56 59 unsigned int naddrs; 57 60 unsigned int addrs_offset; 58 61 unsigned int aligned_offset; ··· 72 69 char *buf; 73 70 }; 74 71 75 - struct ls1x_nand_data { 72 + struct loongson_nand_data { 76 73 unsigned int status_field; 77 74 unsigned int op_scope_field; 78 75 unsigned int hold_cycle; 79 76 unsigned int wait_cycle; 80 - void (*set_addr)(struct ls1x_nand_host *host, struct ls1x_nand_op *op); 77 + void (*set_addr)(struct loongson_nand_host *host, struct loongson_nand_op *op); 81 78 }; 82 79 83 - struct ls1x_nand_host { 80 + struct loongson_nand_host { 84 81 struct device *dev; 85 82 struct nand_chip chip; 86 83 struct nand_controller controller; 87 - const struct ls1x_nand_data *data; 84 + const struct loongson_nand_data *data; 88 85 void __iomem *reg_base; 89 86 struct regmap *regmap; 90 87 /* DMA Engine stuff */ ··· 94 91 struct completion dma_complete; 95 92 }; 96 93 97 - static const struct regmap_config ls1x_nand_regmap_config = { 94 + static const struct regmap_config loongson_nand_regmap_config = { 98 95 .reg_bits = 32, 99 96 .val_bits = 32, 100 97 .reg_stride = 4, 101 98 }; 102 99 103 - static int ls1x_nand_op_cmd_mapping(struct nand_chip *chip, struct ls1x_nand_op *op, u8 opcode) 100 + static int loongson_nand_op_cmd_mapping(struct nand_chip *chip, struct loongson_nand_op *op, 101 + u8 opcode) 104 102 { 105 - struct ls1x_nand_host *host = nand_get_controller_data(chip); 103 + struct loongson_nand_host *host = nand_get_controller_data(chip); 106 104 107 105 op->row_start = chip->page_shift + 1; 108 106 109 107 /* The controller abstracts the following NAND operations. */ 110 108 switch (opcode) { 111 109 case NAND_CMD_STATUS: 112 - op->cmd_reg = LS1X_NAND_CMD_STATUS; 110 + op->cmd_reg = LOONGSON_NAND_CMD_STATUS; 113 111 break; 114 112 case NAND_CMD_RESET: 115 - op->cmd_reg = LS1X_NAND_CMD_RESET; 113 + op->cmd_reg = LOONGSON_NAND_CMD_RESET; 116 114 break; 117 115 case NAND_CMD_READID: 118 116 op->is_readid = true; 119 - op->cmd_reg = LS1X_NAND_CMD_READID; 117 + op->cmd_reg = LOONGSON_NAND_CMD_READID; 120 118 break; 121 119 case NAND_CMD_ERASE1: 122 120 op->is_erase = true; 123 - op->addrs_offset = LS1X_NAND_COL_ADDR_CYC; 121 + op->addrs_offset = LOONGSON_NAND_COL_ADDR_CYC; 124 122 break; 125 123 case NAND_CMD_ERASE2: 126 124 if (!op->is_erase) 127 125 return -EOPNOTSUPP; 128 126 /* During erasing, row_start differs from the default value. */ 129 127 op->row_start = chip->page_shift; 130 - op->cmd_reg = LS1X_NAND_CMD_ERASE; 128 + op->cmd_reg = LOONGSON_NAND_CMD_ERASE; 131 129 break; 132 130 case NAND_CMD_SEQIN: 133 131 op->is_write = true; ··· 136 132 case NAND_CMD_PAGEPROG: 137 133 if (!op->is_write) 138 134 return -EOPNOTSUPP; 139 - op->cmd_reg = LS1X_NAND_CMD_WRITE; 135 + op->cmd_reg = LOONGSON_NAND_CMD_WRITE; 140 136 break; 141 137 case NAND_CMD_READ0: 142 138 op->is_read = true; ··· 144 140 case NAND_CMD_READSTART: 145 141 if (!op->is_read) 146 142 return -EOPNOTSUPP; 147 - op->cmd_reg = LS1X_NAND_CMD_READ; 143 + op->cmd_reg = LOONGSON_NAND_CMD_READ; 148 144 break; 149 145 case NAND_CMD_RNDOUT: 150 146 op->is_change_column = true; ··· 152 148 case NAND_CMD_RNDOUTSTART: 153 149 if (!op->is_change_column) 154 150 return -EOPNOTSUPP; 155 - op->cmd_reg = LS1X_NAND_CMD_READ; 151 + op->cmd_reg = LOONGSON_NAND_CMD_READ; 156 152 break; 157 153 default: 158 154 dev_dbg(host->dev, "unsupported opcode: %u\n", opcode); ··· 162 158 return 0; 163 159 } 164 160 165 - static int ls1x_nand_parse_instructions(struct nand_chip *chip, 166 - const struct nand_subop *subop, struct ls1x_nand_op *op) 161 + static int loongson_nand_parse_instructions(struct nand_chip *chip, const struct nand_subop *subop, 162 + struct loongson_nand_op *op) 167 163 { 168 164 unsigned int op_id; 169 165 int ret; ··· 175 171 176 172 switch (instr->type) { 177 173 case NAND_OP_CMD_INSTR: 178 - ret = ls1x_nand_op_cmd_mapping(chip, op, instr->ctx.cmd.opcode); 174 + ret = loongson_nand_op_cmd_mapping(chip, op, instr->ctx.cmd.opcode); 179 175 if (ret < 0) 180 176 return ret; 181 177 182 178 break; 183 179 case NAND_OP_ADDR_INSTR: 184 180 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 185 - if (naddrs > LS1X_NAND_MAX_ADDR_CYC) 181 + if (naddrs > LOONGSON_NAND_MAX_ADDR_CYC) 186 182 return -EOPNOTSUPP; 187 183 op->naddrs = naddrs; 188 184 offset = nand_subop_get_addr_start_off(subop, op_id); ··· 210 206 return 0; 211 207 } 212 208 213 - static void ls1b_nand_set_addr(struct ls1x_nand_host *host, struct ls1x_nand_op *op) 209 + static void ls1b_nand_set_addr(struct loongson_nand_host *host, struct loongson_nand_op *op) 214 210 { 215 211 struct nand_chip *chip = &host->chip; 216 212 int i; 217 213 218 - for (i = 0; i < LS1X_NAND_MAX_ADDR_CYC; i++) { 214 + for (i = 0; i < LOONGSON_NAND_MAX_ADDR_CYC; i++) { 219 215 int shift, mask, val; 220 216 221 - if (i < LS1X_NAND_COL_ADDR_CYC) { 217 + if (i < LOONGSON_NAND_COL_ADDR_CYC) { 222 218 shift = i * BITS_PER_BYTE; 223 219 mask = (u32)0xff << shift; 224 220 mask &= GENMASK(chip->page_shift, 0); 225 221 val = (u32)op->addrs[i] << shift; 226 - regmap_update_bits(host->regmap, LS1X_NAND_ADDR1, mask, val); 222 + regmap_update_bits(host->regmap, LOONGSON_NAND_ADDR1, mask, val); 227 223 } else if (!op->is_change_column) { 228 - shift = op->row_start + (i - LS1X_NAND_COL_ADDR_CYC) * BITS_PER_BYTE; 224 + shift = op->row_start + (i - LOONGSON_NAND_COL_ADDR_CYC) * BITS_PER_BYTE; 229 225 mask = (u32)0xff << shift; 230 226 val = (u32)op->addrs[i] << shift; 231 - regmap_update_bits(host->regmap, LS1X_NAND_ADDR1, mask, val); 227 + regmap_update_bits(host->regmap, LOONGSON_NAND_ADDR1, mask, val); 232 228 233 229 if (i == 4) { 234 230 mask = (u32)0xff >> (BITS_PER_WORD - shift); 235 231 val = (u32)op->addrs[i] >> (BITS_PER_WORD - shift); 236 - regmap_update_bits(host->regmap, LS1X_NAND_ADDR2, mask, val); 232 + regmap_update_bits(host->regmap, LOONGSON_NAND_ADDR2, mask, val); 237 233 } 238 234 } 239 235 } 240 236 } 241 237 242 - static void ls1c_nand_set_addr(struct ls1x_nand_host *host, struct ls1x_nand_op *op) 238 + static void ls1c_nand_set_addr(struct loongson_nand_host *host, struct loongson_nand_op *op) 243 239 { 244 240 int i; 245 241 246 - for (i = 0; i < LS1X_NAND_MAX_ADDR_CYC; i++) { 242 + for (i = 0; i < LOONGSON_NAND_MAX_ADDR_CYC; i++) { 247 243 int shift, mask, val; 248 244 249 - if (i < LS1X_NAND_COL_ADDR_CYC) { 245 + if (i < LOONGSON_NAND_COL_ADDR_CYC) { 250 246 shift = i * BITS_PER_BYTE; 251 247 mask = (u32)0xff << shift; 252 248 val = (u32)op->addrs[i] << shift; 253 - regmap_update_bits(host->regmap, LS1X_NAND_ADDR1, mask, val); 249 + regmap_update_bits(host->regmap, LOONGSON_NAND_ADDR1, mask, val); 254 250 } else if (!op->is_change_column) { 255 - shift = (i - LS1X_NAND_COL_ADDR_CYC) * BITS_PER_BYTE; 251 + shift = (i - LOONGSON_NAND_COL_ADDR_CYC) * BITS_PER_BYTE; 256 252 mask = (u32)0xff << shift; 257 253 val = (u32)op->addrs[i] << shift; 258 - regmap_update_bits(host->regmap, LS1X_NAND_ADDR2, mask, val); 254 + regmap_update_bits(host->regmap, LOONGSON_NAND_ADDR2, mask, val); 259 255 } 260 256 } 261 257 } 262 258 263 - static void ls1x_nand_trigger_op(struct ls1x_nand_host *host, struct ls1x_nand_op *op) 259 + static void loongson_nand_trigger_op(struct loongson_nand_host *host, struct loongson_nand_op *op) 264 260 { 265 261 struct nand_chip *chip = &host->chip; 266 262 struct mtd_info *mtd = nand_to_mtd(chip); ··· 284 280 else 285 281 op->len = op->orig_len; 286 282 287 - writel(op->len, host->reg_base + LS1X_NAND_OP_NUM); 283 + writel(op->len, host->reg_base + LOONGSON_NAND_OP_NUM); 288 284 289 285 /* set operation area and scope */ 290 286 col = op->addrs[1] << BITS_PER_BYTE | op->addrs[0]; ··· 292 288 unsigned int op_scope = 0; 293 289 294 290 if (col < mtd->writesize) { 295 - op->cmd_reg |= LS1X_NAND_CMD_OP_MAIN; 291 + op->cmd_reg |= LOONGSON_NAND_CMD_OP_MAIN; 296 292 op_scope = mtd->writesize; 297 293 } 298 294 299 - op->cmd_reg |= LS1X_NAND_CMD_OP_SPARE; 295 + op->cmd_reg |= LOONGSON_NAND_CMD_OP_SPARE; 300 296 op_scope += mtd->oobsize; 301 297 302 298 op_scope <<= __ffs(host->data->op_scope_field); 303 - regmap_update_bits(host->regmap, LS1X_NAND_PARAM, 299 + regmap_update_bits(host->regmap, LOONGSON_NAND_PARAM, 304 300 host->data->op_scope_field, op_scope); 305 301 } 306 302 307 303 /* set command */ 308 - writel(op->cmd_reg, host->reg_base + LS1X_NAND_CMD); 304 + writel(op->cmd_reg, host->reg_base + LOONGSON_NAND_CMD); 309 305 310 306 /* trigger operation */ 311 - regmap_write_bits(host->regmap, LS1X_NAND_CMD, LS1X_NAND_CMD_VALID, LS1X_NAND_CMD_VALID); 307 + regmap_write_bits(host->regmap, LOONGSON_NAND_CMD, LOONGSON_NAND_CMD_VALID, 308 + LOONGSON_NAND_CMD_VALID); 312 309 } 313 310 314 - static int ls1x_nand_wait_for_op_done(struct ls1x_nand_host *host, struct ls1x_nand_op *op) 311 + static int loongson_nand_wait_for_op_done(struct loongson_nand_host *host, 312 + struct loongson_nand_op *op) 315 313 { 316 314 unsigned int val; 317 315 int ret = 0; 318 316 319 317 if (op->rdy_timeout_ms) { 320 - ret = regmap_read_poll_timeout(host->regmap, LS1X_NAND_CMD, 321 - val, val & LS1X_NAND_CMD_OP_DONE, 318 + ret = regmap_read_poll_timeout(host->regmap, LOONGSON_NAND_CMD, 319 + val, val & LOONGSON_NAND_CMD_OP_DONE, 322 320 0, op->rdy_timeout_ms * MSEC_PER_SEC); 323 321 if (ret) 324 322 dev_err(host->dev, "operation failed\n"); ··· 329 323 return ret; 330 324 } 331 325 332 - static void ls1x_nand_dma_callback(void *data) 326 + static void loongson_nand_dma_callback(void *data) 333 327 { 334 - struct ls1x_nand_host *host = (struct ls1x_nand_host *)data; 328 + struct loongson_nand_host *host = (struct loongson_nand_host *)data; 335 329 struct dma_chan *chan = host->dma_chan; 336 330 struct device *dev = chan->device->dev; 337 331 enum dma_status status; ··· 345 339 } 346 340 } 347 341 348 - static int ls1x_nand_dma_transfer(struct ls1x_nand_host *host, struct ls1x_nand_op *op) 342 + static int loongson_nand_dma_transfer(struct loongson_nand_host *host, struct loongson_nand_op *op) 349 343 { 350 344 struct nand_chip *chip = &host->chip; 351 345 struct dma_chan *chan = host->dma_chan; ··· 380 374 ret = -ENOMEM; 381 375 goto err; 382 376 } 383 - desc->callback = ls1x_nand_dma_callback; 377 + desc->callback = loongson_nand_dma_callback; 384 378 desc->callback_param = host; 385 379 386 380 host->dma_cookie = dmaengine_submit(desc); ··· 411 405 return ret; 412 406 } 413 407 414 - static int ls1x_nand_data_type_exec(struct nand_chip *chip, const struct nand_subop *subop) 408 + static int loongson_nand_data_type_exec(struct nand_chip *chip, const struct nand_subop *subop) 415 409 { 416 - struct ls1x_nand_host *host = nand_get_controller_data(chip); 417 - struct ls1x_nand_op op = {}; 410 + struct loongson_nand_host *host = nand_get_controller_data(chip); 411 + struct loongson_nand_op op = {}; 418 412 int ret; 419 413 420 - ret = ls1x_nand_parse_instructions(chip, subop, &op); 414 + ret = loongson_nand_parse_instructions(chip, subop, &op); 421 415 if (ret) 422 416 return ret; 423 417 424 - ls1x_nand_trigger_op(host, &op); 418 + loongson_nand_trigger_op(host, &op); 425 419 426 - ret = ls1x_nand_dma_transfer(host, &op); 420 + ret = loongson_nand_dma_transfer(host, &op); 427 421 if (ret) 428 422 return ret; 429 423 430 - return ls1x_nand_wait_for_op_done(host, &op); 424 + return loongson_nand_wait_for_op_done(host, &op); 431 425 } 432 426 433 - static int ls1x_nand_misc_type_exec(struct nand_chip *chip, 434 - const struct nand_subop *subop, struct ls1x_nand_op *op) 427 + static int loongson_nand_misc_type_exec(struct nand_chip *chip, const struct nand_subop *subop, 428 + struct loongson_nand_op *op) 435 429 { 436 - struct ls1x_nand_host *host = nand_get_controller_data(chip); 430 + struct loongson_nand_host *host = nand_get_controller_data(chip); 437 431 int ret; 438 432 439 - ret = ls1x_nand_parse_instructions(chip, subop, op); 433 + ret = loongson_nand_parse_instructions(chip, subop, op); 440 434 if (ret) 441 435 return ret; 442 436 443 - ls1x_nand_trigger_op(host, op); 437 + loongson_nand_trigger_op(host, op); 444 438 445 - return ls1x_nand_wait_for_op_done(host, op); 439 + return loongson_nand_wait_for_op_done(host, op); 446 440 } 447 441 448 - static int ls1x_nand_zerolen_type_exec(struct nand_chip *chip, const struct nand_subop *subop) 442 + static int loongson_nand_zerolen_type_exec(struct nand_chip *chip, const struct nand_subop *subop) 449 443 { 450 - struct ls1x_nand_op op = {}; 444 + struct loongson_nand_op op = {}; 451 445 452 - return ls1x_nand_misc_type_exec(chip, subop, &op); 446 + return loongson_nand_misc_type_exec(chip, subop, &op); 453 447 } 454 448 455 - static int ls1x_nand_read_id_type_exec(struct nand_chip *chip, const struct nand_subop *subop) 449 + static int loongson_nand_read_id_type_exec(struct nand_chip *chip, const struct nand_subop *subop) 456 450 { 457 - struct ls1x_nand_host *host = nand_get_controller_data(chip); 458 - struct ls1x_nand_op op = {}; 451 + struct loongson_nand_host *host = nand_get_controller_data(chip); 452 + struct loongson_nand_op op = {}; 459 453 int i, ret; 460 454 union { 461 455 char ids[5]; ··· 465 459 }; 466 460 } nand_id; 467 461 468 - ret = ls1x_nand_misc_type_exec(chip, subop, &op); 462 + ret = loongson_nand_misc_type_exec(chip, subop, &op); 469 463 if (ret) 470 464 return ret; 471 465 472 - nand_id.idl = readl(host->reg_base + LS1X_NAND_IDL); 473 - nand_id.idh = readb(host->reg_base + LS1X_NAND_IDH_STATUS); 466 + nand_id.idl = readl(host->reg_base + LOONGSON_NAND_IDL); 467 + nand_id.idh = readb(host->reg_base + LOONGSON_NAND_IDH_STATUS); 474 468 475 469 for (i = 0; i < min(sizeof(nand_id.ids), op.orig_len); i++) 476 470 op.buf[i] = nand_id.ids[sizeof(nand_id.ids) - 1 - i]; ··· 478 472 return ret; 479 473 } 480 474 481 - static int ls1x_nand_read_status_type_exec(struct nand_chip *chip, const struct nand_subop *subop) 475 + static int loongson_nand_read_status_type_exec(struct nand_chip *chip, 476 + const struct nand_subop *subop) 482 477 { 483 - struct ls1x_nand_host *host = nand_get_controller_data(chip); 484 - struct ls1x_nand_op op = {}; 478 + struct loongson_nand_host *host = nand_get_controller_data(chip); 479 + struct loongson_nand_op op = {}; 485 480 int val, ret; 486 481 487 - ret = ls1x_nand_misc_type_exec(chip, subop, &op); 482 + ret = loongson_nand_misc_type_exec(chip, subop, &op); 488 483 if (ret) 489 484 return ret; 490 485 491 - val = readl(host->reg_base + LS1X_NAND_IDH_STATUS); 486 + val = readl(host->reg_base + LOONGSON_NAND_IDH_STATUS); 492 487 val &= ~host->data->status_field; 493 488 op.buf[0] = val << ffs(host->data->status_field); 494 489 495 490 return ret; 496 491 } 497 492 498 - static const struct nand_op_parser ls1x_nand_op_parser = NAND_OP_PARSER( 493 + static const struct nand_op_parser loongson_nand_op_parser = NAND_OP_PARSER( 499 494 NAND_OP_PARSER_PATTERN( 500 - ls1x_nand_read_id_type_exec, 495 + loongson_nand_read_id_type_exec, 501 496 NAND_OP_PARSER_PAT_CMD_ELEM(false), 502 - NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), 497 + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LOONGSON_NAND_MAX_ADDR_CYC), 503 498 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), 504 499 NAND_OP_PARSER_PATTERN( 505 - ls1x_nand_read_status_type_exec, 500 + loongson_nand_read_status_type_exec, 506 501 NAND_OP_PARSER_PAT_CMD_ELEM(false), 507 502 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), 508 503 NAND_OP_PARSER_PATTERN( 509 - ls1x_nand_zerolen_type_exec, 504 + loongson_nand_zerolen_type_exec, 510 505 NAND_OP_PARSER_PAT_CMD_ELEM(false), 511 506 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 512 507 NAND_OP_PARSER_PATTERN( 513 - ls1x_nand_zerolen_type_exec, 508 + loongson_nand_zerolen_type_exec, 514 509 NAND_OP_PARSER_PAT_CMD_ELEM(false), 515 - NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), 510 + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LOONGSON_NAND_MAX_ADDR_CYC), 516 511 NAND_OP_PARSER_PAT_CMD_ELEM(false), 517 512 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 518 513 NAND_OP_PARSER_PATTERN( 519 - ls1x_nand_data_type_exec, 514 + loongson_nand_data_type_exec, 520 515 NAND_OP_PARSER_PAT_CMD_ELEM(false), 521 - NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), 516 + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LOONGSON_NAND_MAX_ADDR_CYC), 522 517 NAND_OP_PARSER_PAT_CMD_ELEM(false), 523 518 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 524 519 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)), 525 520 NAND_OP_PARSER_PATTERN( 526 - ls1x_nand_data_type_exec, 521 + loongson_nand_data_type_exec, 527 522 NAND_OP_PARSER_PAT_CMD_ELEM(false), 528 - NAND_OP_PARSER_PAT_ADDR_ELEM(false, LS1X_NAND_MAX_ADDR_CYC), 523 + NAND_OP_PARSER_PAT_ADDR_ELEM(false, LOONGSON_NAND_MAX_ADDR_CYC), 529 524 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0), 530 525 NAND_OP_PARSER_PAT_CMD_ELEM(false), 531 526 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 532 527 ); 533 528 534 - static int ls1x_nand_is_valid_cmd(u8 opcode) 529 + static int loongson_nand_is_valid_cmd(u8 opcode) 535 530 { 536 531 if (opcode == NAND_CMD_STATUS || opcode == NAND_CMD_RESET || opcode == NAND_CMD_READID) 537 532 return 0; ··· 540 533 return -EOPNOTSUPP; 541 534 } 542 535 543 - static int ls1x_nand_is_valid_cmd_seq(u8 opcode1, u8 opcode2) 536 + static int loongson_nand_is_valid_cmd_seq(u8 opcode1, u8 opcode2) 544 537 { 545 538 if (opcode1 == NAND_CMD_RNDOUT && opcode2 == NAND_CMD_RNDOUTSTART) 546 539 return 0; ··· 557 550 return -EOPNOTSUPP; 558 551 } 559 552 560 - static int ls1x_nand_check_op(struct nand_chip *chip, const struct nand_operation *op) 553 + static int loongson_nand_check_op(struct nand_chip *chip, const struct nand_operation *op) 561 554 { 562 555 const struct nand_op_instr *instr1 = NULL, *instr2 = NULL; 563 556 int op_id; ··· 579 572 return -EOPNOTSUPP; 580 573 581 574 if (!instr2) 582 - return ls1x_nand_is_valid_cmd(instr1->ctx.cmd.opcode); 575 + return loongson_nand_is_valid_cmd(instr1->ctx.cmd.opcode); 583 576 584 - return ls1x_nand_is_valid_cmd_seq(instr1->ctx.cmd.opcode, instr2->ctx.cmd.opcode); 577 + return loongson_nand_is_valid_cmd_seq(instr1->ctx.cmd.opcode, instr2->ctx.cmd.opcode); 585 578 } 586 579 587 - static int ls1x_nand_exec_op(struct nand_chip *chip, 588 - const struct nand_operation *op, bool check_only) 580 + static int loongson_nand_exec_op(struct nand_chip *chip, const struct nand_operation *op, 581 + bool check_only) 589 582 { 590 583 if (check_only) 591 - return ls1x_nand_check_op(chip, op); 584 + return loongson_nand_check_op(chip, op); 592 585 593 - return nand_op_parser_exec_op(chip, &ls1x_nand_op_parser, op, check_only); 586 + return nand_op_parser_exec_op(chip, &loongson_nand_op_parser, op, check_only); 594 587 } 595 588 596 - static int ls1x_nand_attach_chip(struct nand_chip *chip) 589 + static int loongson_nand_attach_chip(struct nand_chip *chip) 597 590 { 598 - struct ls1x_nand_host *host = nand_get_controller_data(chip); 591 + struct loongson_nand_host *host = nand_get_controller_data(chip); 599 592 u64 chipsize = nanddev_target_size(&chip->base); 600 593 int cell_size = 0; 601 594 ··· 639 632 } 640 633 641 634 /* set cell size */ 642 - regmap_update_bits(host->regmap, LS1X_NAND_PARAM, LS1X_NAND_CELL_SIZE_MASK, 643 - FIELD_PREP(LS1X_NAND_CELL_SIZE_MASK, cell_size)); 635 + regmap_update_bits(host->regmap, LOONGSON_NAND_PARAM, LOONGSON_NAND_CELL_SIZE_MASK, 636 + FIELD_PREP(LOONGSON_NAND_CELL_SIZE_MASK, cell_size)); 644 637 645 - regmap_update_bits(host->regmap, LS1X_NAND_TIMING, LS1X_NAND_HOLD_CYCLE_MASK, 646 - FIELD_PREP(LS1X_NAND_HOLD_CYCLE_MASK, host->data->hold_cycle)); 638 + regmap_update_bits(host->regmap, LOONGSON_NAND_TIMING, LOONGSON_NAND_HOLD_CYCLE_MASK, 639 + FIELD_PREP(LOONGSON_NAND_HOLD_CYCLE_MASK, host->data->hold_cycle)); 647 640 648 - regmap_update_bits(host->regmap, LS1X_NAND_TIMING, LS1X_NAND_WAIT_CYCLE_MASK, 649 - FIELD_PREP(LS1X_NAND_WAIT_CYCLE_MASK, host->data->wait_cycle)); 641 + regmap_update_bits(host->regmap, LOONGSON_NAND_TIMING, LOONGSON_NAND_WAIT_CYCLE_MASK, 642 + FIELD_PREP(LOONGSON_NAND_WAIT_CYCLE_MASK, host->data->wait_cycle)); 650 643 651 644 chip->ecc.read_page_raw = nand_monolithic_read_page_raw; 652 645 chip->ecc.write_page_raw = nand_monolithic_write_page_raw; ··· 654 647 return 0; 655 648 } 656 649 657 - static const struct nand_controller_ops ls1x_nand_controller_ops = { 658 - .exec_op = ls1x_nand_exec_op, 659 - .attach_chip = ls1x_nand_attach_chip, 650 + static const struct nand_controller_ops loongson_nand_controller_ops = { 651 + .exec_op = loongson_nand_exec_op, 652 + .attach_chip = loongson_nand_attach_chip, 660 653 }; 661 654 662 - static void ls1x_nand_controller_cleanup(struct ls1x_nand_host *host) 655 + static void loongson_nand_controller_cleanup(struct loongson_nand_host *host) 663 656 { 664 657 if (host->dma_chan) 665 658 dma_release_channel(host->dma_chan); 666 659 } 667 660 668 - static int ls1x_nand_controller_init(struct ls1x_nand_host *host) 661 + static int loongson_nand_controller_init(struct loongson_nand_host *host) 669 662 { 670 663 struct device *dev = host->dev; 671 664 struct dma_chan *chan; 672 665 struct dma_slave_config cfg = {}; 673 666 int ret; 674 667 675 - host->regmap = devm_regmap_init_mmio(dev, host->reg_base, &ls1x_nand_regmap_config); 668 + host->regmap = devm_regmap_init_mmio(dev, host->reg_base, &loongson_nand_regmap_config); 676 669 if (IS_ERR(host->regmap)) 677 670 return dev_err_probe(dev, PTR_ERR(host->regmap), "failed to init regmap\n"); 678 671 ··· 694 687 return 0; 695 688 } 696 689 697 - static int ls1x_nand_chip_init(struct ls1x_nand_host *host) 690 + static int loongson_nand_chip_init(struct loongson_nand_host *host) 698 691 { 699 692 struct device *dev = host->dev; 700 693 int nchips = of_get_child_count(dev->of_node); ··· 735 728 return 0; 736 729 } 737 730 738 - static int ls1x_nand_probe(struct platform_device *pdev) 731 + static int loongson_nand_probe(struct platform_device *pdev) 739 732 { 740 733 struct device *dev = &pdev->dev; 741 - const struct ls1x_nand_data *data; 742 - struct ls1x_nand_host *host; 734 + const struct loongson_nand_data *data; 735 + struct loongson_nand_host *host; 743 736 struct resource *res; 744 737 int ret; 745 738 ··· 766 759 767 760 host->dev = dev; 768 761 host->data = data; 769 - host->controller.ops = &ls1x_nand_controller_ops; 762 + host->controller.ops = &loongson_nand_controller_ops; 770 763 771 764 nand_controller_init(&host->controller); 772 765 773 - ret = ls1x_nand_controller_init(host); 766 + ret = loongson_nand_controller_init(host); 774 767 if (ret) 775 768 goto err; 776 769 777 - ret = ls1x_nand_chip_init(host); 770 + ret = loongson_nand_chip_init(host); 778 771 if (ret) 779 772 goto err; 780 773 ··· 782 775 783 776 return 0; 784 777 err: 785 - ls1x_nand_controller_cleanup(host); 778 + loongson_nand_controller_cleanup(host); 786 779 787 780 return ret; 788 781 } 789 782 790 - static void ls1x_nand_remove(struct platform_device *pdev) 783 + static void loongson_nand_remove(struct platform_device *pdev) 791 784 { 792 - struct ls1x_nand_host *host = platform_get_drvdata(pdev); 785 + struct loongson_nand_host *host = platform_get_drvdata(pdev); 793 786 struct nand_chip *chip = &host->chip; 794 787 int ret; 795 788 796 789 ret = mtd_device_unregister(nand_to_mtd(chip)); 797 790 WARN_ON(ret); 798 791 nand_cleanup(chip); 799 - ls1x_nand_controller_cleanup(host); 792 + loongson_nand_controller_cleanup(host); 800 793 } 801 794 802 - static const struct ls1x_nand_data ls1b_nand_data = { 795 + static const struct loongson_nand_data ls1b_nand_data = { 803 796 .status_field = GENMASK(15, 8), 804 797 .hold_cycle = 0x2, 805 798 .wait_cycle = 0xc, 806 799 .set_addr = ls1b_nand_set_addr, 807 800 }; 808 801 809 - static const struct ls1x_nand_data ls1c_nand_data = { 802 + static const struct loongson_nand_data ls1c_nand_data = { 810 803 .status_field = GENMASK(23, 16), 811 804 .op_scope_field = GENMASK(29, 16), 812 805 .hold_cycle = 0x2, ··· 814 807 .set_addr = ls1c_nand_set_addr, 815 808 }; 816 809 817 - static const struct of_device_id ls1x_nand_match[] = { 810 + static const struct of_device_id loongson_nand_match[] = { 818 811 { 819 812 .compatible = "loongson,ls1b-nand-controller", 820 813 .data = &ls1b_nand_data, ··· 825 818 }, 826 819 { /* sentinel */ } 827 820 }; 828 - MODULE_DEVICE_TABLE(of, ls1x_nand_match); 821 + MODULE_DEVICE_TABLE(of, loongson_nand_match); 829 822 830 - static struct platform_driver ls1x_nand_driver = { 831 - .probe = ls1x_nand_probe, 832 - .remove = ls1x_nand_remove, 823 + static struct platform_driver loongson_nand_driver = { 824 + .probe = loongson_nand_probe, 825 + .remove = loongson_nand_remove, 833 826 .driver = { 834 827 .name = KBUILD_MODNAME, 835 - .of_match_table = ls1x_nand_match, 828 + .of_match_table = loongson_nand_match, 836 829 }, 837 830 }; 838 831 839 - module_platform_driver(ls1x_nand_driver); 832 + module_platform_driver(loongson_nand_driver); 840 833 841 834 MODULE_AUTHOR("Keguang Zhang <keguang.zhang@gmail.com>"); 842 - MODULE_DESCRIPTION("Loongson-1 NAND Controller Driver"); 835 + MODULE_DESCRIPTION("Loongson NAND Controller Driver"); 843 836 MODULE_LICENSE("GPL");