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drm/amdgpu: Add function to fill training region

Add a function to fill in memory training reservation region. Only if
the reservation for the region is successful, memory training context
will be initialized.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher
7b0af160 2c7b0e37

+34 -26
+34 -26
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 1724 1724 reserve_size, false); 1725 1725 } 1726 1726 1727 + static void amdgpu_ttm_init_mem_train_resv_region(struct amdgpu_device *adev) 1728 + { 1729 + uint64_t reserve_size; 1730 + uint64_t offset; 1731 + 1732 + if (!adev->discovery.reserve_tmr) 1733 + return; 1734 + 1735 + if (!adev->bios || amdgpu_sriov_vf(adev)) 1736 + return; 1737 + 1738 + if (!amdgpu_atomfirmware_mem_training_supported(adev)) 1739 + return; 1740 + 1741 + reserve_size = adev->mman.resv_region[AMDGPU_RESV_FW].size; 1742 + offset = ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1743 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_MEM_TRAIN, 1744 + offset, 1745 + GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES, 1746 + false); 1747 + } 1748 + 1727 1749 static void amdgpu_ttm_init_vram_resv_regions(struct amdgpu_device *adev) 1728 1750 { 1729 1751 /* Initialize memory reservations as required for VGA. ··· 1755 1733 */ 1756 1734 amdgpu_gmc_init_vga_resv_regions(adev); 1757 1735 amdgpu_ttm_init_fw_resv_region(adev); 1736 + amdgpu_ttm_init_mem_train_resv_region(adev); 1758 1737 } 1759 1738 1760 1739 int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev, ··· 1821 1798 return 0; 1822 1799 } 1823 1800 1824 - static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev, 1825 - uint32_t reserve_size) 1801 + static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1826 1802 { 1827 1803 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1804 + struct amdgpu_vram_resv *resv = 1805 + &adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN]; 1828 1806 1829 1807 memset(ctx, 0, sizeof(*ctx)); 1830 1808 1831 - ctx->c2p_train_data_offset = 1832 - ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1809 + ctx->c2p_train_data_offset = resv->offset; 1833 1810 ctx->p2c_train_data_offset = 1834 1811 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1835 - ctx->train_data_size = 1836 - GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1812 + ctx->train_data_size = resv->size; 1837 1813 1838 1814 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1839 1815 ctx->train_data_size, ··· 1847 1825 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1848 1826 { 1849 1827 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1850 - bool mem_train_support = false; 1851 - uint32_t reserve_size; 1852 1828 int ret; 1853 1829 1854 - reserve_size = adev->mman.resv_region[AMDGPU_RESV_FW].size; 1855 - 1856 - if (adev->bios && !amdgpu_sriov_vf(adev)) { 1857 - if (amdgpu_atomfirmware_mem_training_supported(adev)) 1858 - mem_train_support = true; 1859 - else 1860 - DRM_DEBUG("memory training does not support!\n"); 1830 + ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_MEM_TRAIN); 1831 + if (ret) { 1832 + dev_err(adev->dev, "memory training region reservation failed(%d)!\n", ret); 1833 + return ret; 1861 1834 } 1862 1835 1863 - if (mem_train_support) { 1864 - /* reserve vram for mem train according to TMR location */ 1865 - amdgpu_ttm_training_data_block_init(adev, reserve_size); 1866 - amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_MEM_TRAIN, 1867 - ctx->c2p_train_data_offset, 1868 - ctx->train_data_size, false); 1869 - ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_MEM_TRAIN); 1870 - if (ret) { 1871 - dev_err(adev->dev, "memory training region reservation failed(%d)!\n", ret); 1872 - return ret; 1873 - } 1836 + if (adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN].size) { 1837 + amdgpu_ttm_training_data_block_init(adev); 1874 1838 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1875 1839 } 1876 1840