tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'arm/fixes' into soc/late2

* arm/fixes:
arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT
reset: amlogic: t7: Fix null reset ops
arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-ultra-mach-sbc: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-sr-som: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-nitrogen-som: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-aristainetos3a-som-v1: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-edm-g: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-icore-mx8mp: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-debix-som-a: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-debix-model-a: Correct PAD settings for PMIC_nINT
dt-bindings: arm64: add Marvell 7k COMe boards

Arnd Bergmann 7b82df33 8242c709

+30 -18
+11
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
··· 21 21 - const: marvell,armada-ap806-dual 22 22 - const: marvell,armada-ap806 23 23 24 + - description: 25 + Falcon (DB-98CX85x0) Development board COM Express Carrier plus 26 + Armada 7020 SoC COM Express CPU module 27 + items: 28 + - const: marvell,armada7020-falcon-carrier 29 + - const: marvell,db-falcon-carrier 30 + - const: marvell,armada7020-cpu-module 31 + - const: marvell,armada7020 32 + - const: marvell,armada-ap806-dual 33 + - const: marvell,armada-ap806 34 + 24 35 - description: Armada 7040 SoC 25 36 items: 26 37 - enum:
+2 -2
arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi
··· 60 60 pinctrl-names = "default"; 61 61 pinctrl-0 = <&pinctrl_pmic>; 62 62 interrupt-parent = <&gpio1>; 63 - interrupts = <3 IRQ_TYPE_EDGE_RISING>; 63 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 64 64 65 65 regulators { 66 66 buck1: BUCK1 { ··· 194 194 195 195 pinctrl_pmic: emtop-pmic-grp { 196 196 fsl,pins = < 197 - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 197 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 198 198 >; 199 199 }; 200 200
+1 -1
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
··· 292 292 }; 293 293 294 294 pinctrl_pmic: pmicgrp { 295 - fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; 295 + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1d4>; 296 296 }; 297 297 298 298 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+1 -1
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
··· 283 283 }; 284 284 285 285 pinctrl_pmic: pmicgrp { 286 - fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>; 286 + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1c4>; 287 287 }; 288 288 289 289 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
··· 903 903 904 904 pinctrl_pmic: aristainetos3-pmic-grp { 905 905 fsl,pins = < 906 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 906 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 907 907 >; 908 908 }; 909 909
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
··· 1001 1001 pinctrl_pmic: pmic-grp { 1002 1002 fsl,pins = < 1003 1003 /* PMIC_nINT */ 1004 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 1004 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 1005 1005 >; 1006 1006 }; 1007 1007
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
··· 440 440 441 441 pinctrl_pmic: pmicirqgrp { 442 442 fsl,pins = < 443 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 443 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 444 444 >; 445 445 }; 446 446
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
··· 499 499 500 500 pinctrl_pmic: pmicgrp { 501 501 fsl,pins = < 502 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 502 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 503 503 >; 504 504 }; 505 505
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
··· 241 241 242 242 pinctrl_pmic: pmicgrp { 243 243 fsl,pins = < 244 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 244 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 245 245 >; 246 246 }; 247 247
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
··· 989 989 pinctrl_pmic: dhcom-pmic-grp { 990 990 fsl,pins = < 991 991 /* PMIC_nINT */ 992 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 992 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 993 993 >; 994 994 }; 995 995
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi
··· 563 563 564 564 pinctrl_pmic: pmicirqgrp { 565 565 fsl,pins = < 566 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 566 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 567 567 >; 568 568 }; 569 569
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
··· 132 132 133 133 pinctrl_pmic: pmicgrp { 134 134 fsl,pins = < 135 - MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 135 + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0 136 136 >; 137 137 }; 138 138
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
··· 356 356 357 357 pinctrl_pmic: pmicgrp { 358 358 fsl,pins = < 359 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 359 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 360 360 >; 361 361 }; 362 362
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
··· 296 296 297 297 pinctrl_pmic: pmicirqgrp { 298 298 fsl,pins = < 299 - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 299 + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x1c0 300 300 >; 301 301 }; 302 302
+2 -2
arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
··· 174 174 pinctrl-0 = <&pmic_pins>; 175 175 pinctrl-names = "default"; 176 176 interrupt-parent = <&gpio1>; 177 - interrupts = <3 GPIO_ACTIVE_LOW>; 177 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 178 178 nxp,i2c-lt-enable; 179 179 180 180 regulators { ··· 417 417 418 418 pmic_pins: pinctrl-pmic-grp { 419 419 fsl,pins = < 420 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 420 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 421 421 >; 422 422 }; 423 423
+2 -2
arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
··· 275 275 reg = <0x25>; 276 276 pinctrl-0 = <&pinctrl_pmic>; 277 277 interrupt-parent = <&gpio1>; 278 - interrupts = <3 GPIO_ACTIVE_LOW>; 278 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 279 279 280 280 /* 281 281 * i.MX 8M Plus Data Sheet for Consumer Products ··· 739 739 740 740 pinctrl_pmic: pmic-grp { 741 741 fsl,pins = < 742 - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */ 742 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 /* #PMIC_INT */ 743 743 >; 744 744 }; 745 745
+1
drivers/reset/amlogic/reset-meson.c
··· 42 42 }; 43 43 44 44 static const struct meson_reset_param t7_param = { 45 + .reset_ops = &meson_reset_ops, 45 46 .reset_num = 224, 46 47 .reset_offset = 0x0, 47 48 .level_offset = 0x40,