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drm/i915/vrr: Add function to check if DC Balance Possible

Add a function that checks if DC Balance enabling is possible on the
requested PIPE. Apart from the DISPLAY_VER check, account for current
firmware limitations, which only allow DC Balance on PIPE A and PIPE B.

v2: Rephrased commit message. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-9-mitulkumar.ajitkumar.golani@intel.com

authored by

Mitul Golani and committed by
Ankit Nautiyal 7bf11bc2 2873c8ea

+17 -2
+17 -2
drivers/gpu/drm/i915/display/intel_vrr.c
··· 351 351 return vmax; 352 352 } 353 353 354 + static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state) 355 + { 356 + struct intel_display *display = to_intel_display(crtc_state); 357 + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 358 + enum pipe pipe = crtc->pipe; 359 + 360 + /* 361 + * FIXME: Currently Firmware supports DC Balancing on PIPE A 362 + * and PIPE B. Account those limitation while computing DC 363 + * Balance parameters. 364 + */ 365 + return (HAS_VRR_DC_BALANCE(display) && 366 + ((pipe == PIPE_A) || (pipe == PIPE_B))); 367 + } 368 + 354 369 static void 355 370 intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state) 356 371 { 357 372 int guardband_usec, adjustment_usec; 358 373 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 359 374 360 - if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable) 375 + if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable) 361 376 return; 362 377 363 378 crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax; ··· 854 839 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 855 840 enum pipe pipe = crtc->pipe; 856 841 857 - if (!HAS_VRR_DC_BALANCE(display)) 842 + if (!intel_vrr_dc_balance_possible(crtc_state)) 858 843 return; 859 844 860 845 reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));