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drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.

Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined,
ensuring SoC-specific initialization is performed only when necessary.

This change prepares for RZ/V2H(P) SoC support while maintaining
compatibility with existing platforms.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-9-prabhakar.mahadev-lad.rj@bp.renesas.com

authored by

Lad Prabhakar and committed by
Biju Das 7c1e102c a56a6b81

+4
+4
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
··· 40 40 41 41 struct rzg2l_mipi_dsi_hw_info { 42 42 int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); 43 + void (*dphy_startup_late_init)(struct rzg2l_mipi_dsi *dsi); 43 44 void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); 44 45 u32 phy_reg_offset; 45 46 u32 link_reg_offset; ··· 331 330 /* Enable Data lanes and Clock lanes */ 332 331 txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; 333 332 rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); 333 + 334 + if (dsi->info->dphy_startup_late_init) 335 + dsi->info->dphy_startup_late_init(dsi); 334 336 335 337 hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); 336 338 /*