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drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.

Update the `mipi_dsi_host_attach()` function to check this flag before
allowing 16BPP formats. If the SoC does not support 16BPP, return an error
to prevent incorrect format selection.

This change enables finer-grained format support control for different
SoC variants.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-8-prabhakar.mahadev-lad.rj@bp.renesas.com

authored by

Lad Prabhakar and committed by
Biju Das a56a6b81 7c3fecdd

+11
+11
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
··· 34 34 35 35 #define RZG2L_DCS_BUF_SIZE 128 /* Maximum DCS buffer size in external memory. */ 36 36 37 + #define RZ_MIPI_DSI_FEATURE_16BPP BIT(0) 38 + 37 39 struct rzg2l_mipi_dsi; 38 40 39 41 struct rzg2l_mipi_dsi_hw_info { ··· 45 43 u32 link_reg_offset; 46 44 unsigned long min_dclk; 47 45 unsigned long max_dclk; 46 + u8 features; 48 47 }; 49 48 50 49 struct rzg2l_mipi_dsi { ··· 675 672 676 673 switch (mipi_dsi_pixel_format_to_bpp(device->format)) { 677 674 case 24: 675 + break; 678 676 case 18: 677 + break; 678 + case 16: 679 + if (!(dsi->info->features & RZ_MIPI_DSI_FEATURE_16BPP)) { 680 + dev_err(dsi->dev, "Unsupported format 0x%04x\n", 681 + device->format); 682 + return -EINVAL; 683 + } 679 684 break; 680 685 default: 681 686 dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);