Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iommu-fixes-v4.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU fixes from Joerg Roedel:
"The fixes include:
- Two patches to revert the use of default domains in the ARM SMMU
driver. Enabling this caused regressions which need more thorough
fixing. So the regressions are fixed for now by disabling the use
of default domains.
- A fix for a v4.4 regression in the AMD IOMMU driver which broke
devices behind invisible PCIe-to-PCI bridges with IOMMU enabled"
* tag 'iommu-fixes-v4.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/arm-smmu: Don't allocate resources for bypass domains
iommu/arm-smmu: Fix stream-match conflict with IOMMU_DOMAIN_DMA
iommu/amd: Fix checking of pci dma aliases
+92
-19
+76
-11
drivers/iommu/amd_iommu.c
+76
-11
drivers/iommu/amd_iommu.c
···
92
92
struct list_head dev_data_list; /* For global dev_data_list */
93
93
struct protection_domain *domain; /* Domain the device is bound to */
94
94
u16 devid; /* PCI Device ID */
95
+
u16 alias; /* Alias Device ID */
95
96
bool iommu_v2; /* Device can make use of IOMMUv2 */
96
97
bool passthrough; /* Device is identity mapped */
97
98
struct {
···
167
166
return container_of(dom, struct protection_domain, domain);
168
167
}
169
168
169
+
static inline u16 get_device_id(struct device *dev)
170
+
{
171
+
struct pci_dev *pdev = to_pci_dev(dev);
172
+
173
+
return PCI_DEVID(pdev->bus->number, pdev->devfn);
174
+
}
175
+
170
176
static struct iommu_dev_data *alloc_dev_data(u16 devid)
171
177
{
172
178
struct iommu_dev_data *dev_data;
···
211
203
return dev_data;
212
204
}
213
205
206
+
static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
207
+
{
208
+
*(u16 *)data = alias;
209
+
return 0;
210
+
}
211
+
212
+
static u16 get_alias(struct device *dev)
213
+
{
214
+
struct pci_dev *pdev = to_pci_dev(dev);
215
+
u16 devid, ivrs_alias, pci_alias;
216
+
217
+
devid = get_device_id(dev);
218
+
ivrs_alias = amd_iommu_alias_table[devid];
219
+
pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
220
+
221
+
if (ivrs_alias == pci_alias)
222
+
return ivrs_alias;
223
+
224
+
/*
225
+
* DMA alias showdown
226
+
*
227
+
* The IVRS is fairly reliable in telling us about aliases, but it
228
+
* can't know about every screwy device. If we don't have an IVRS
229
+
* reported alias, use the PCI reported alias. In that case we may
230
+
* still need to initialize the rlookup and dev_table entries if the
231
+
* alias is to a non-existent device.
232
+
*/
233
+
if (ivrs_alias == devid) {
234
+
if (!amd_iommu_rlookup_table[pci_alias]) {
235
+
amd_iommu_rlookup_table[pci_alias] =
236
+
amd_iommu_rlookup_table[devid];
237
+
memcpy(amd_iommu_dev_table[pci_alias].data,
238
+
amd_iommu_dev_table[devid].data,
239
+
sizeof(amd_iommu_dev_table[pci_alias].data));
240
+
}
241
+
242
+
return pci_alias;
243
+
}
244
+
245
+
pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
246
+
"for device %s[%04x:%04x], kernel reported alias "
247
+
"%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
248
+
PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
249
+
PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
250
+
PCI_FUNC(pci_alias));
251
+
252
+
/*
253
+
* If we don't have a PCI DMA alias and the IVRS alias is on the same
254
+
* bus, then the IVRS table may know about a quirk that we don't.
255
+
*/
256
+
if (pci_alias == devid &&
257
+
PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
258
+
pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
259
+
pdev->dma_alias_devfn = ivrs_alias & 0xff;
260
+
pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
261
+
PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
262
+
dev_name(dev));
263
+
}
264
+
265
+
return ivrs_alias;
266
+
}
267
+
214
268
static struct iommu_dev_data *find_dev_data(u16 devid)
215
269
{
216
270
struct iommu_dev_data *dev_data;
···
283
213
dev_data = alloc_dev_data(devid);
284
214
285
215
return dev_data;
286
-
}
287
-
288
-
static inline u16 get_device_id(struct device *dev)
289
-
{
290
-
struct pci_dev *pdev = to_pci_dev(dev);
291
-
292
-
return PCI_DEVID(pdev->bus->number, pdev->devfn);
293
216
}
294
217
295
218
static struct iommu_dev_data *get_dev_data(struct device *dev)
···
412
349
if (!dev_data)
413
350
return -ENOMEM;
414
351
352
+
dev_data->alias = get_alias(dev);
353
+
415
354
if (pci_iommuv2_capable(pdev)) {
416
355
struct amd_iommu *iommu;
417
356
···
434
369
u16 devid, alias;
435
370
436
371
devid = get_device_id(dev);
437
-
alias = amd_iommu_alias_table[devid];
372
+
alias = get_alias(dev);
438
373
439
374
memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
440
375
memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
···
1126
1061
int ret;
1127
1062
1128
1063
iommu = amd_iommu_rlookup_table[dev_data->devid];
1129
-
alias = amd_iommu_alias_table[dev_data->devid];
1064
+
alias = dev_data->alias;
1130
1065
1131
1066
ret = iommu_flush_dte(iommu, dev_data->devid);
1132
1067
if (!ret && alias != dev_data->devid)
···
2104
2039
bool ats;
2105
2040
2106
2041
iommu = amd_iommu_rlookup_table[dev_data->devid];
2107
-
alias = amd_iommu_alias_table[dev_data->devid];
2042
+
alias = dev_data->alias;
2108
2043
ats = dev_data->ats.enabled;
2109
2044
2110
2045
/* Update data structures */
···
2138
2073
return;
2139
2074
2140
2075
iommu = amd_iommu_rlookup_table[dev_data->devid];
2141
-
alias = amd_iommu_alias_table[dev_data->devid];
2076
+
alias = dev_data->alias;
2142
2077
2143
2078
/* decrease reference counters */
2144
2079
dev_data->domain->dev_iommu[iommu->index] -= 1;
+16
-8
drivers/iommu/arm-smmu.c
+16
-8
drivers/iommu/arm-smmu.c
···
826
826
if (smmu_domain->smmu)
827
827
goto out_unlock;
828
828
829
+
/* We're bypassing these SIDs, so don't allocate an actual context */
830
+
if (domain->type == IOMMU_DOMAIN_DMA) {
831
+
smmu_domain->smmu = smmu;
832
+
goto out_unlock;
833
+
}
834
+
829
835
/*
830
836
* Mapping the requested stage onto what we support is surprisingly
831
837
* complicated, mainly because the spec allows S1+S2 SMMUs without
···
954
948
void __iomem *cb_base;
955
949
int irq;
956
950
957
-
if (!smmu)
951
+
if (!smmu || domain->type == IOMMU_DOMAIN_DMA)
958
952
return;
959
953
960
954
/*
···
1095
1089
struct arm_smmu_device *smmu = smmu_domain->smmu;
1096
1090
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1097
1091
1092
+
/*
1093
+
* FIXME: This won't be needed once we have IOMMU-backed DMA ops
1094
+
* for all devices behind the SMMU. Note that we need to take
1095
+
* care configuring SMRs for devices both a platform_device and
1096
+
* and a PCI device (i.e. a PCI host controller)
1097
+
*/
1098
+
if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA)
1099
+
return 0;
1100
+
1098
1101
/* Devices in an IOMMU group may already be configured */
1099
1102
ret = arm_smmu_master_configure_smrs(smmu, cfg);
1100
1103
if (ret)
1101
1104
return ret == -EEXIST ? 0 : ret;
1102
-
1103
-
/*
1104
-
* FIXME: This won't be needed once we have IOMMU-backed DMA ops
1105
-
* for all devices behind the SMMU.
1106
-
*/
1107
-
if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA)
1108
-
return 0;
1109
1105
1110
1106
for (i = 0; i < cfg->num_streamids; ++i) {
1111
1107
u32 idx, s2cr;