clk: qcom: lpass: Add support for resets & external mclk for SC7280

The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks.

Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after
disable as this clock signal is used by hardware to turn ON memories in
LPASS. Also add the external mclk to interface external MI2S.

Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-6-git-send-email-quic_c_skakit@quicinc.com

authored by

Taniya Das and committed by

Bjorn Andersson 3 years ago 7c6a6641 0cbcfbe5

+55 -2

2 changed files

expand all

drivers

clk

qcom

lpassaudiocc-sc7280.c

lpasscorecc-sc7280.c

+22 -2

drivers/clk/qcom/lpassaudiocc-sc7280.c

··· 23 23 #include "clk-regmap-mux.h" 24 24 #include "common.h" 25 25 #include "gdsc.h" 26 + #include "reset.h" 26 27 27 28 enum { 28 29 P_BI_TCXO, ··· 249 248 .parent_data = lpass_aon_cc_parent_data_0, 250 249 .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0), 251 250 .flags = CLK_OPS_PARENT_ENABLE, 252 - .ops = &clk_rcg2_ops, 251 + .ops = &clk_rcg2_shared_ops, 253 252 }, 254 253 }; 255 254 ··· 704 703 .num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks), 705 704 }; 706 705 706 + static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = { 707 + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 }, 708 + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 }, 709 + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, 710 + }; 711 + 712 + static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = { 713 + .config = &lpass_audio_cc_sc7280_regmap_config, 714 + .resets = lpass_audio_cc_sc7280_resets, 715 + .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets), 716 + }; 717 + 707 718 static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = { 708 719 { .compatible = "qcom,sc7280-lpassaudiocc" }, 709 720 { } ··· 785 772 regmap_write(regmap, 0x4, 0x3b); 786 773 regmap_write(regmap, 0x8, 0xff05); 787 774 788 - ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap); 775 + ret = qcom_cc_probe_by_index(pdev, 0, &lpass_audio_cc_sc7280_desc); 789 776 if (ret) { 790 777 dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n"); 778 + pm_runtime_disable(&pdev->dev); 779 + return ret; 780 + } 781 + 782 + ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc); 783 + if (ret) { 784 + dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n"); 791 785 pm_runtime_disable(&pdev->dev); 792 786 return ret; 793 787 }

+33

drivers/clk/qcom/lpasscorecc-sc7280.c

··· 190 190 }, 191 191 }; 192 192 193 + static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = { 194 + .cmd_rcgr = 0x20000, 195 + .mnd_width = 8, 196 + .hid_width = 5, 197 + .parent_map = lpass_core_cc_parent_map_0, 198 + .freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src, 199 + .clkr.hw.init = &(const struct clk_init_data){ 200 + .name = "lpass_core_cc_ext_mclk0_clk_src", 201 + .parent_data = lpass_core_cc_parent_data_0, 202 + .num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0), 203 + .ops = &clk_rcg2_ops, 204 + }, 205 + }; 193 206 194 207 static struct clk_branch lpass_core_cc_core_clk = { 195 208 .halt_reg = 0x1f000, ··· 296 283 }, 297 284 }; 298 285 286 + static struct clk_branch lpass_core_cc_ext_mclk0_clk = { 287 + .halt_reg = 0x20014, 288 + .halt_check = BRANCH_HALT, 289 + .clkr = { 290 + .enable_reg = 0x20014, 291 + .enable_mask = BIT(0), 292 + .hw.init = &(const struct clk_init_data){ 293 + .name = "lpass_core_cc_ext_mclk0_clk", 294 + .parent_hws = (const struct clk_hw*[]){ 295 + &lpass_core_cc_ext_mclk0_clk_src.clkr.hw, 296 + }, 297 + .num_parents = 1, 298 + .flags = CLK_SET_RATE_PARENT, 299 + .ops = &clk_branch2_ops, 300 + }, 301 + }, 302 + }; 303 + 299 304 static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = { 300 305 .halt_reg = 0x23000, 301 306 .halt_check = BRANCH_HALT_VOTED, ··· 357 326 [LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr, 358 327 [LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr, 359 328 [LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr, 329 + [LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr, 330 + [LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr, 360 331 }; 361 332 362 333 static struct regmap_config lpass_core_cc_sc7280_regmap_config = {

Configure Feed

Configure Feed