Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: rt722-sdca: Add RT722 SDCA driver
This is the initial codec driver for rt722-sdca.
Signed-off-by: Jack Yu <jack.yu@realtek.com
Link: https://lore.kernel.org/r/20230421030116.26245-1-jack.yu@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org
authored by
Jack Yu
and committed by
Mark Brown
7f5d6036
5782f019
+2436
+7
sound/soc/codecs/Kconfig
+7
sound/soc/codecs/Kconfig
···
207
207
imply SND_SOC_RT712_SDCA_DMIC_SDW
208
208
imply SND_SOC_RT715_SDW
209
209
imply SND_SOC_RT715_SDCA_SDW
210
+
imply SND_SOC_RT722_SDCA_SDW
210
211
imply SND_SOC_RT1308_SDW
211
212
imply SND_SOC_RT1316_SDW
212
213
imply SND_SOC_RT1318_SDW
···
1536
1535
1537
1536
config SND_SOC_RT712_SDCA_DMIC_SDW
1538
1537
tristate "Realtek RT712 SDCA DMIC Codec - SDW"
1538
+
depends on SOUNDWIRE
1539
+
select REGMAP_SOUNDWIRE
1540
+
select REGMAP_SOUNDWIRE_MBQ
1541
+
1542
+
config SND_SOC_RT722_SDCA_SDW
1543
+
tristate "Realtek RT722 SDCA Codec - SDW"
1539
1544
depends on SOUNDWIRE
1540
1545
select REGMAP_SOUNDWIRE
1541
1546
select REGMAP_SOUNDWIRE_MBQ
+2
sound/soc/codecs/Makefile
+2
sound/soc/codecs/Makefile
···
237
237
snd-soc-rt712-sdca-dmic-objs := rt712-sdca-dmic.o
238
238
snd-soc-rt715-objs := rt715.o rt715-sdw.o
239
239
snd-soc-rt715-sdca-objs := rt715-sdca.o rt715-sdca-sdw.o
240
+
snd-soc-rt722-sdca-objs := rt722-sdca.o rt722-sdca-sdw.o
240
241
snd-soc-rt9120-objs := rt9120.o
241
242
snd-soc-sdw-mockup-objs := sdw-mockup.o
242
243
snd-soc-sgtl5000-objs := sgtl5000.o
···
608
607
obj-$(CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW) += snd-soc-rt712-sdca-dmic.o
609
608
obj-$(CONFIG_SND_SOC_RT715) += snd-soc-rt715.o
610
609
obj-$(CONFIG_SND_SOC_RT715_SDCA_SDW) += snd-soc-rt715-sdca.o
610
+
obj-$(CONFIG_SND_SOC_RT722_SDCA_SDW) += snd-soc-rt722-sdca.o
611
611
obj-$(CONFIG_SND_SOC_RT9120) += snd-soc-rt9120.o
612
612
obj-$(CONFIG_SND_SOC_SDW_MOCKUP) += snd-soc-sdw-mockup.o
613
613
obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
+510
sound/soc/codecs/rt722-sdca-sdw.c
+510
sound/soc/codecs/rt722-sdca-sdw.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
//
3
+
// rt722-sdca-sdw.c -- rt722 SDCA ALSA SoC audio driver
4
+
//
5
+
// Copyright(c) 2023 Realtek Semiconductor Corp.
6
+
//
7
+
//
8
+
9
+
#include <linux/delay.h>
10
+
#include <linux/device.h>
11
+
#include <linux/module.h>
12
+
#include <linux/mod_devicetable.h>
13
+
#include <linux/pm_runtime.h>
14
+
#include <linux/soundwire/sdw_registers.h>
15
+
16
+
#include "rt722-sdca.h"
17
+
#include "rt722-sdca-sdw.h"
18
+
19
+
static bool rt722_sdca_readable_register(struct device *dev, unsigned int reg)
20
+
{
21
+
switch (reg) {
22
+
case 0x2f01 ... 0x2f0a:
23
+
case 0x2f35 ... 0x2f36:
24
+
case 0x2f50:
25
+
case 0x2f54:
26
+
case 0x2f58 ... 0x2f5d:
27
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_SELECTED_MODE,
28
+
0):
29
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
30
+
0):
31
+
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
32
+
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
33
+
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
34
+
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
35
+
return true;
36
+
default:
37
+
return false;
38
+
}
39
+
}
40
+
41
+
static bool rt722_sdca_volatile_register(struct device *dev, unsigned int reg)
42
+
{
43
+
switch (reg) {
44
+
case 0x2f01:
45
+
case 0x2f54:
46
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
47
+
0):
48
+
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
49
+
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
50
+
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
51
+
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
52
+
return true;
53
+
default:
54
+
return false;
55
+
}
56
+
}
57
+
58
+
static bool rt722_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
59
+
{
60
+
switch (reg) {
61
+
case 0x2000000 ... 0x2000024:
62
+
case 0x2000029 ... 0x200004a:
63
+
case 0x2000051 ... 0x2000052:
64
+
case 0x200005a ... 0x200005b:
65
+
case 0x2000061 ... 0x2000069:
66
+
case 0x200006b:
67
+
case 0x2000070:
68
+
case 0x200007f:
69
+
case 0x2000082 ... 0x200008e:
70
+
case 0x2000090 ... 0x2000094:
71
+
case 0x5300000 ... 0x5300002:
72
+
case 0x5400002:
73
+
case 0x5600000 ... 0x5600007:
74
+
case 0x5700000 ... 0x5700004:
75
+
case 0x5800000 ... 0x5800004:
76
+
case 0x5b00003:
77
+
case 0x5c00011:
78
+
case 0x5d00006:
79
+
case 0x5f00000 ... 0x5f0000d:
80
+
case 0x5f00030:
81
+
case 0x6100000 ... 0x6100051:
82
+
case 0x6100055 ... 0x6100057:
83
+
case 0x6100062:
84
+
case 0x6100064 ... 0x6100065:
85
+
case 0x6100067:
86
+
case 0x6100070 ... 0x610007c:
87
+
case 0x6100080:
88
+
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
89
+
CH_01):
90
+
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
91
+
CH_02):
92
+
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
93
+
CH_03):
94
+
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
95
+
CH_04):
96
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L):
97
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R):
98
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
99
+
CH_L):
100
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
101
+
CH_R):
102
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
103
+
CH_L):
104
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
105
+
CH_R):
106
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
107
+
RT722_SDCA_CTL_FU_CH_GAIN, CH_L):
108
+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
109
+
RT722_SDCA_CTL_FU_CH_GAIN, CH_R):
110
+
return true;
111
+
default:
112
+
return false;
113
+
}
114
+
}
115
+
116
+
static bool rt722_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
117
+
{
118
+
switch (reg) {
119
+
case 0x2000000:
120
+
case 0x200000d:
121
+
case 0x2000019:
122
+
case 0x2000020:
123
+
case 0x2000030:
124
+
case 0x2000046:
125
+
case 0x2000067:
126
+
case 0x2000084:
127
+
case 0x2000086:
128
+
return true;
129
+
default:
130
+
return false;
131
+
}
132
+
}
133
+
134
+
static const struct regmap_config rt722_sdca_regmap = {
135
+
.reg_bits = 32,
136
+
.val_bits = 8,
137
+
.readable_reg = rt722_sdca_readable_register,
138
+
.volatile_reg = rt722_sdca_volatile_register,
139
+
.max_register = 0x44ffffff,
140
+
.reg_defaults = rt722_sdca_reg_defaults,
141
+
.num_reg_defaults = ARRAY_SIZE(rt722_sdca_reg_defaults),
142
+
.cache_type = REGCACHE_RBTREE,
143
+
.use_single_read = true,
144
+
.use_single_write = true,
145
+
};
146
+
147
+
static const struct regmap_config rt722_sdca_mbq_regmap = {
148
+
.name = "sdw-mbq",
149
+
.reg_bits = 32,
150
+
.val_bits = 16,
151
+
.readable_reg = rt722_sdca_mbq_readable_register,
152
+
.volatile_reg = rt722_sdca_mbq_volatile_register,
153
+
.max_register = 0x41000312,
154
+
.reg_defaults = rt722_sdca_mbq_defaults,
155
+
.num_reg_defaults = ARRAY_SIZE(rt722_sdca_mbq_defaults),
156
+
.cache_type = REGCACHE_RBTREE,
157
+
.use_single_read = true,
158
+
.use_single_write = true,
159
+
};
160
+
161
+
static int rt722_sdca_update_status(struct sdw_slave *slave,
162
+
enum sdw_slave_status status)
163
+
{
164
+
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
165
+
166
+
/* Update the status */
167
+
rt722->status = status;
168
+
169
+
if (status == SDW_SLAVE_UNATTACHED)
170
+
rt722->hw_init = false;
171
+
172
+
if (status == SDW_SLAVE_ATTACHED) {
173
+
if (rt722->hs_jack) {
174
+
/*
175
+
* Due to the SCP_SDCA_INTMASK will be cleared by any reset, and then
176
+
* if the device attached again, we will need to set the setting back.
177
+
* It could avoid losing the jack detection interrupt.
178
+
* This also could sync with the cache value as the rt722_sdca_jack_init set.
179
+
*/
180
+
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
181
+
SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6);
182
+
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
183
+
SDW_SCP_SDCA_INTMASK_SDCA_8);
184
+
}
185
+
}
186
+
187
+
/*
188
+
* Perform initialization only if slave status is present and
189
+
* hw_init flag is false
190
+
*/
191
+
if (rt722->hw_init || rt722->status != SDW_SLAVE_ATTACHED)
192
+
return 0;
193
+
194
+
/* perform I/O transfers required for Slave initialization */
195
+
return rt722_sdca_io_init(&slave->dev, slave);
196
+
}
197
+
198
+
static int rt722_sdca_read_prop(struct sdw_slave *slave)
199
+
{
200
+
struct sdw_slave_prop *prop = &slave->prop;
201
+
int nval;
202
+
int i, j;
203
+
u32 bit;
204
+
unsigned long addr;
205
+
struct sdw_dpn_prop *dpn;
206
+
207
+
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
208
+
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
209
+
210
+
prop->paging_support = true;
211
+
212
+
/*
213
+
* port = 1 for headphone playback
214
+
* port = 2 for headset-mic capture
215
+
* port = 3 for speaker playback
216
+
* port = 6 for digital-mic capture
217
+
*/
218
+
prop->source_ports = BIT(6) | BIT(2); /* BITMAP: 01000100 */
219
+
prop->sink_ports = BIT(3) | BIT(1); /* BITMAP: 00001010 */
220
+
221
+
nval = hweight32(prop->source_ports);
222
+
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
223
+
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
224
+
if (!prop->src_dpn_prop)
225
+
return -ENOMEM;
226
+
227
+
i = 0;
228
+
dpn = prop->src_dpn_prop;
229
+
addr = prop->source_ports;
230
+
for_each_set_bit(bit, &addr, 32) {
231
+
dpn[i].num = bit;
232
+
dpn[i].type = SDW_DPN_FULL;
233
+
dpn[i].simple_ch_prep_sm = true;
234
+
dpn[i].ch_prep_timeout = 10;
235
+
i++;
236
+
}
237
+
238
+
/* do this again for sink now */
239
+
nval = hweight32(prop->sink_ports);
240
+
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
241
+
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
242
+
if (!prop->sink_dpn_prop)
243
+
return -ENOMEM;
244
+
245
+
j = 0;
246
+
dpn = prop->sink_dpn_prop;
247
+
addr = prop->sink_ports;
248
+
for_each_set_bit(bit, &addr, 32) {
249
+
dpn[j].num = bit;
250
+
dpn[j].type = SDW_DPN_FULL;
251
+
dpn[j].simple_ch_prep_sm = true;
252
+
dpn[j].ch_prep_timeout = 10;
253
+
j++;
254
+
}
255
+
256
+
/* set the timeout values */
257
+
prop->clk_stop_timeout = 200;
258
+
259
+
/* wake-up event */
260
+
prop->wake_capable = 1;
261
+
262
+
return 0;
263
+
}
264
+
265
+
static int rt722_sdca_interrupt_callback(struct sdw_slave *slave,
266
+
struct sdw_slave_intr_status *status)
267
+
{
268
+
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
269
+
int ret, stat;
270
+
int count = 0, retry = 3;
271
+
unsigned int sdca_cascade, scp_sdca_stat1, scp_sdca_stat2 = 0;
272
+
273
+
if (cancel_delayed_work_sync(&rt722->jack_detect_work)) {
274
+
dev_warn(&slave->dev, "%s the pending delayed_work was cancelled", __func__);
275
+
/* avoid the HID owner doesn't change to device */
276
+
if (rt722->scp_sdca_stat2)
277
+
scp_sdca_stat2 = rt722->scp_sdca_stat2;
278
+
}
279
+
280
+
/*
281
+
* The critical section below intentionally protects a rather large piece of code.
282
+
* We don't want to allow the system suspend to disable an interrupt while we are
283
+
* processing it, which could be problematic given the quirky SoundWire interrupt
284
+
* scheme. We do want however to prevent new workqueues from being scheduled if
285
+
* the disable_irq flag was set during system suspend.
286
+
*/
287
+
mutex_lock(&rt722->disable_irq_lock);
288
+
289
+
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
290
+
if (ret < 0)
291
+
goto io_error;
292
+
rt722->scp_sdca_stat1 = ret;
293
+
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
294
+
if (ret < 0)
295
+
goto io_error;
296
+
rt722->scp_sdca_stat2 = ret;
297
+
if (scp_sdca_stat2)
298
+
rt722->scp_sdca_stat2 |= scp_sdca_stat2;
299
+
do {
300
+
/* clear flag */
301
+
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
302
+
if (ret < 0)
303
+
goto io_error;
304
+
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_0) {
305
+
ret = sdw_update_no_pm(rt722->slave, SDW_SCP_SDCA_INT1,
306
+
SDW_SCP_SDCA_INT_SDCA_0, SDW_SCP_SDCA_INT_SDCA_0);
307
+
if (ret < 0)
308
+
goto io_error;
309
+
} else if (ret & SDW_SCP_SDCA_INTMASK_SDCA_6) {
310
+
ret = sdw_update_no_pm(rt722->slave, SDW_SCP_SDCA_INT1,
311
+
SDW_SCP_SDCA_INT_SDCA_6, SDW_SCP_SDCA_INT_SDCA_6);
312
+
if (ret < 0)
313
+
goto io_error;
314
+
}
315
+
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
316
+
if (ret < 0)
317
+
goto io_error;
318
+
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_8) {
319
+
ret = sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INT2,
320
+
SDW_SCP_SDCA_INTMASK_SDCA_8);
321
+
if (ret < 0)
322
+
goto io_error;
323
+
}
324
+
325
+
/* check if flag clear or not */
326
+
ret = sdw_read_no_pm(rt722->slave, SDW_DP0_INT);
327
+
if (ret < 0)
328
+
goto io_error;
329
+
sdca_cascade = ret & SDW_DP0_SDCA_CASCADE;
330
+
331
+
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
332
+
if (ret < 0)
333
+
goto io_error;
334
+
scp_sdca_stat1 = ret & SDW_SCP_SDCA_INTMASK_SDCA_0;
335
+
336
+
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
337
+
if (ret < 0)
338
+
goto io_error;
339
+
scp_sdca_stat2 = ret & SDW_SCP_SDCA_INTMASK_SDCA_8;
340
+
341
+
stat = scp_sdca_stat1 || scp_sdca_stat2 || sdca_cascade;
342
+
343
+
count++;
344
+
} while (stat != 0 && count < retry);
345
+
346
+
if (stat)
347
+
dev_warn(&slave->dev,
348
+
"%s scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
349
+
rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
350
+
351
+
if (status->sdca_cascade && !rt722->disable_irq)
352
+
mod_delayed_work(system_power_efficient_wq,
353
+
&rt722->jack_detect_work, msecs_to_jiffies(30));
354
+
355
+
mutex_unlock(&rt722->disable_irq_lock);
356
+
357
+
return 0;
358
+
359
+
io_error:
360
+
mutex_unlock(&rt722->disable_irq_lock);
361
+
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
362
+
return ret;
363
+
}
364
+
365
+
static struct sdw_slave_ops rt722_sdca_slave_ops = {
366
+
.read_prop = rt722_sdca_read_prop,
367
+
.interrupt_callback = rt722_sdca_interrupt_callback,
368
+
.update_status = rt722_sdca_update_status,
369
+
};
370
+
371
+
static int rt722_sdca_sdw_probe(struct sdw_slave *slave,
372
+
const struct sdw_device_id *id)
373
+
{
374
+
struct regmap *regmap, *mbq_regmap;
375
+
376
+
/* Regmap Initialization */
377
+
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt722_sdca_mbq_regmap);
378
+
if (IS_ERR(mbq_regmap))
379
+
return PTR_ERR(mbq_regmap);
380
+
381
+
regmap = devm_regmap_init_sdw(slave, &rt722_sdca_regmap);
382
+
if (IS_ERR(regmap))
383
+
return PTR_ERR(regmap);
384
+
385
+
return rt722_sdca_init(&slave->dev, regmap, mbq_regmap, slave);
386
+
}
387
+
388
+
static int rt722_sdca_sdw_remove(struct sdw_slave *slave)
389
+
{
390
+
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
391
+
392
+
if (rt722->hw_init) {
393
+
cancel_delayed_work_sync(&rt722->jack_detect_work);
394
+
cancel_delayed_work_sync(&rt722->jack_btn_check_work);
395
+
}
396
+
397
+
if (rt722->first_hw_init)
398
+
pm_runtime_disable(&slave->dev);
399
+
400
+
mutex_destroy(&rt722->calibrate_mutex);
401
+
mutex_destroy(&rt722->disable_irq_lock);
402
+
403
+
return 0;
404
+
}
405
+
406
+
static const struct sdw_device_id rt722_sdca_id[] = {
407
+
SDW_SLAVE_ENTRY_EXT(0x025d, 0x722, 0x3, 0x1, 0),
408
+
{},
409
+
};
410
+
MODULE_DEVICE_TABLE(sdw, rt722_sdca_id);
411
+
412
+
static int __maybe_unused rt722_sdca_dev_suspend(struct device *dev)
413
+
{
414
+
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
415
+
416
+
if (!rt722->hw_init)
417
+
return 0;
418
+
419
+
cancel_delayed_work_sync(&rt722->jack_detect_work);
420
+
cancel_delayed_work_sync(&rt722->jack_btn_check_work);
421
+
422
+
regcache_cache_only(rt722->regmap, true);
423
+
regcache_cache_only(rt722->mbq_regmap, true);
424
+
425
+
return 0;
426
+
}
427
+
428
+
static int __maybe_unused rt722_sdca_dev_system_suspend(struct device *dev)
429
+
{
430
+
struct rt722_sdca_priv *rt722_sdca = dev_get_drvdata(dev);
431
+
struct sdw_slave *slave = dev_to_sdw_dev(dev);
432
+
int ret1, ret2;
433
+
434
+
if (!rt722_sdca->hw_init)
435
+
return 0;
436
+
437
+
/*
438
+
* prevent new interrupts from being handled after the
439
+
* deferred work completes and before the parent disables
440
+
* interrupts on the link
441
+
*/
442
+
mutex_lock(&rt722_sdca->disable_irq_lock);
443
+
rt722_sdca->disable_irq = true;
444
+
ret1 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK1,
445
+
SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6, 0);
446
+
ret2 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK2,
447
+
SDW_SCP_SDCA_INTMASK_SDCA_8, 0);
448
+
mutex_unlock(&rt722_sdca->disable_irq_lock);
449
+
450
+
if (ret1 < 0 || ret2 < 0) {
451
+
/* log but don't prevent suspend from happening */
452
+
dev_dbg(&slave->dev, "%s: could not disable SDCA interrupts\n:", __func__);
453
+
}
454
+
455
+
return rt722_sdca_dev_suspend(dev);
456
+
}
457
+
458
+
#define RT722_PROBE_TIMEOUT 5000
459
+
460
+
static int __maybe_unused rt722_sdca_dev_resume(struct device *dev)
461
+
{
462
+
struct sdw_slave *slave = dev_to_sdw_dev(dev);
463
+
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
464
+
unsigned long time;
465
+
466
+
if (!rt722->first_hw_init)
467
+
return 0;
468
+
469
+
if (!slave->unattach_request)
470
+
goto regmap_sync;
471
+
472
+
time = wait_for_completion_timeout(&slave->initialization_complete,
473
+
msecs_to_jiffies(RT722_PROBE_TIMEOUT));
474
+
if (!time) {
475
+
dev_err(&slave->dev, "Initialization not complete, timed out\n");
476
+
sdw_show_ping_status(slave->bus, true);
477
+
478
+
return -ETIMEDOUT;
479
+
}
480
+
481
+
regmap_sync:
482
+
slave->unattach_request = 0;
483
+
regcache_cache_only(rt722->regmap, false);
484
+
regcache_sync(rt722->regmap);
485
+
regcache_cache_only(rt722->mbq_regmap, false);
486
+
regcache_sync(rt722->mbq_regmap);
487
+
return 0;
488
+
}
489
+
490
+
static const struct dev_pm_ops rt722_sdca_pm = {
491
+
SET_SYSTEM_SLEEP_PM_OPS(rt722_sdca_dev_system_suspend, rt722_sdca_dev_resume)
492
+
SET_RUNTIME_PM_OPS(rt722_sdca_dev_suspend, rt722_sdca_dev_resume, NULL)
493
+
};
494
+
495
+
static struct sdw_driver rt722_sdca_sdw_driver = {
496
+
.driver = {
497
+
.name = "rt722-sdca",
498
+
.owner = THIS_MODULE,
499
+
.pm = &rt722_sdca_pm,
500
+
},
501
+
.probe = rt722_sdca_sdw_probe,
502
+
.remove = rt722_sdca_sdw_remove,
503
+
.ops = &rt722_sdca_slave_ops,
504
+
.id_table = rt722_sdca_id,
505
+
};
506
+
module_sdw_driver(rt722_sdca_sdw_driver);
507
+
508
+
MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
509
+
MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
510
+
MODULE_LICENSE("GPL");
+124
sound/soc/codecs/rt722-sdca-sdw.h
+124
sound/soc/codecs/rt722-sdca-sdw.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* rt722-sdca-sdw.h -- RT722 SDCA ALSA SoC audio driver header
4
+
*
5
+
* Copyright(c) 2023 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
#ifndef __RT722_SDW_H__
9
+
#define __RT722_SDW_H__
10
+
11
+
#include <linux/regmap.h>
12
+
#include <linux/soundwire/sdw_registers.h>
13
+
14
+
static const struct reg_default rt722_sdca_reg_defaults[] = {
15
+
{ 0x202d, 0x00 },
16
+
{ 0x2f01, 0x00 },
17
+
{ 0x2f02, 0x09 },
18
+
{ 0x2f03, 0x00 },
19
+
{ 0x2f04, 0x00 },
20
+
{ 0x2f05, 0x0b },
21
+
{ 0x2f06, 0x01 },
22
+
{ 0x2f08, 0x00 },
23
+
{ 0x2f09, 0x00 },
24
+
{ 0x2f0a, 0x00 },
25
+
{ 0x2f35, 0x00 },
26
+
{ 0x2f36, 0x00 },
27
+
{ 0x2f50, 0xf0 },
28
+
{ 0x2f58, 0x07 },
29
+
{ 0x2f59, 0x07 },
30
+
{ 0x2f5a, 0x07 },
31
+
{ 0x2f5b, 0x07 },
32
+
{ 0x2f5c, 0x27 },
33
+
{ 0x2f5d, 0x07 },
34
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
35
+
0), 0x09 },
36
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
37
+
0), 0x09 },
38
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_REQ_POWER_STATE,
39
+
0), 0x03 },
40
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_REQ_POWER_STATE,
41
+
0), 0x03 },
42
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_L),
43
+
0x01 },
44
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_R),
45
+
0x01 },
46
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_L),
47
+
0x01 },
48
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_R),
49
+
0x01 },
50
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
51
+
0), 0x09 },
52
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_01),
53
+
0x01 },
54
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_02),
55
+
0x01 },
56
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_03),
57
+
0x01 },
58
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_04),
59
+
0x01 },
60
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
61
+
0x03 },
62
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, RT722_SDCA_CTL_VENDOR_DEF, 0),
63
+
0x00 },
64
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
65
+
0x09 },
66
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_L),
67
+
0x01 },
68
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_R),
69
+
0x01 },
70
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
71
+
0x03 },
72
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, RT722_SDCA_CTL_VENDOR_DEF, 0), 0x00 },
73
+
};
74
+
75
+
static const struct reg_default rt722_sdca_mbq_defaults[] = {
76
+
{ 0x200003c, 0xc214 },
77
+
{ 0x2000046, 0x8004 },
78
+
{ 0x6100006, 0x0005 },
79
+
{ 0x6100010, 0x2630 },
80
+
{ 0x6100011, 0x152f },
81
+
{ 0x6100013, 0x0102 },
82
+
{ 0x6100015, 0x2200 },
83
+
{ 0x6100017, 0x0102 },
84
+
{ 0x6100025, 0x2a29 },
85
+
{ 0x6100026, 0x2a00 },
86
+
{ 0x6100028, 0x2a2a },
87
+
{ 0x6100029, 0x4141 },
88
+
{ 0x6100055, 0x0000 },
89
+
{ 0x5810000, 0x702d },
90
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
91
+
CH_L), 0x0000 },
92
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
93
+
CH_R), 0x0000 },
94
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
95
+
CH_L), 0x0000 },
96
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
97
+
CH_R), 0x0000 },
98
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
99
+
CH_L), 0x0000 },
100
+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
101
+
CH_R), 0x0000 },
102
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
103
+
CH_01), 0x0000 },
104
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
105
+
CH_02), 0x0000 },
106
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
107
+
CH_03), 0x0000 },
108
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
109
+
CH_04), 0x0000 },
110
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
111
+
0x0000 },
112
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_02),
113
+
0x0000 },
114
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_03),
115
+
0x0000 },
116
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_04),
117
+
0x0000 },
118
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L),
119
+
0x0000 },
120
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R),
121
+
0x0000 },
122
+
};
123
+
124
+
#endif /* __RT722_SDW_H__ */
+1555
sound/soc/codecs/rt722-sdca.c
+1555
sound/soc/codecs/rt722-sdca.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
//
3
+
// rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver
4
+
//
5
+
// Copyright(c) 2023 Realtek Semiconductor Corp.
6
+
//
7
+
//
8
+
9
+
#include <linux/bitops.h>
10
+
#include <sound/core.h>
11
+
#include <linux/delay.h>
12
+
#include <linux/init.h>
13
+
#include <sound/initval.h>
14
+
#include <sound/jack.h>
15
+
#include <linux/kernel.h>
16
+
#include <linux/module.h>
17
+
#include <linux/moduleparam.h>
18
+
#include <sound/pcm.h>
19
+
#include <linux/pm_runtime.h>
20
+
#include <sound/pcm_params.h>
21
+
#include <linux/soundwire/sdw_registers.h>
22
+
#include <linux/slab.h>
23
+
#include <sound/soc-dapm.h>
24
+
#include <sound/tlv.h>
25
+
26
+
#include "rt722-sdca.h"
27
+
28
+
int rt722_sdca_index_write(struct rt722_sdca_priv *rt722,
29
+
unsigned int nid, unsigned int reg, unsigned int value)
30
+
{
31
+
struct regmap *regmap = rt722->mbq_regmap;
32
+
unsigned int addr = (nid << 20) | reg;
33
+
int ret;
34
+
35
+
ret = regmap_write(regmap, addr, value);
36
+
if (ret < 0)
37
+
dev_err(&rt722->slave->dev,
38
+
"Failed to set private value: %06x <= %04x ret=%d\n",
39
+
addr, value, ret);
40
+
41
+
return ret;
42
+
}
43
+
44
+
int rt722_sdca_index_read(struct rt722_sdca_priv *rt722,
45
+
unsigned int nid, unsigned int reg, unsigned int *value)
46
+
{
47
+
int ret;
48
+
struct regmap *regmap = rt722->mbq_regmap;
49
+
unsigned int addr = (nid << 20) | reg;
50
+
51
+
ret = regmap_read(regmap, addr, value);
52
+
if (ret < 0)
53
+
dev_err(&rt722->slave->dev,
54
+
"Failed to get private value: %06x => %04x ret=%d\n",
55
+
addr, *value, ret);
56
+
57
+
return ret;
58
+
}
59
+
60
+
static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722,
61
+
unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
62
+
{
63
+
unsigned int tmp;
64
+
int ret;
65
+
66
+
ret = rt722_sdca_index_read(rt722, nid, reg, &tmp);
67
+
if (ret < 0)
68
+
return ret;
69
+
70
+
set_mask_bits(&tmp, mask, val);
71
+
return rt722_sdca_index_write(rt722, nid, reg, tmp);
72
+
}
73
+
74
+
static int rt722_sdca_btn_type(unsigned char *buffer)
75
+
{
76
+
if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) ||
77
+
(*(buffer + 1) == 0x10))
78
+
return SND_JACK_BTN_2;
79
+
else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) ||
80
+
(*(buffer + 1) == 0x20))
81
+
return SND_JACK_BTN_3;
82
+
else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) ||
83
+
(*(buffer + 1) == 0x40))
84
+
return SND_JACK_BTN_0;
85
+
else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) ||
86
+
(*(buffer + 1) == 0x80))
87
+
return SND_JACK_BTN_1;
88
+
89
+
return 0;
90
+
}
91
+
92
+
static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722)
93
+
{
94
+
unsigned int btn_type = 0, offset, idx, val, owner;
95
+
int ret;
96
+
unsigned char buf[3];
97
+
98
+
/* get current UMP message owner */
99
+
ret = regmap_read(rt722->regmap,
100
+
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
101
+
RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner);
102
+
if (ret < 0)
103
+
return 0;
104
+
105
+
/* if owner is device then there is no button event from device */
106
+
if (owner == 1)
107
+
return 0;
108
+
109
+
/* read UMP message offset */
110
+
ret = regmap_read(rt722->regmap,
111
+
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
112
+
RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
113
+
if (ret < 0)
114
+
goto _end_btn_det_;
115
+
116
+
for (idx = 0; idx < sizeof(buf); idx++) {
117
+
ret = regmap_read(rt722->regmap,
118
+
RT722_BUF_ADDR_HID1 + offset + idx, &val);
119
+
if (ret < 0)
120
+
goto _end_btn_det_;
121
+
buf[idx] = val & 0xff;
122
+
}
123
+
124
+
if (buf[0] == 0x11)
125
+
btn_type = rt722_sdca_btn_type(&buf[1]);
126
+
127
+
_end_btn_det_:
128
+
/* Host is owner, so set back to device */
129
+
if (owner == 0)
130
+
/* set owner to device */
131
+
regmap_write(rt722->regmap,
132
+
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
133
+
RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01);
134
+
135
+
return btn_type;
136
+
}
137
+
138
+
static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722)
139
+
{
140
+
unsigned int det_mode;
141
+
int ret;
142
+
143
+
/* get detected_mode */
144
+
ret = regmap_read(rt722->regmap,
145
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
146
+
RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
147
+
if (ret < 0)
148
+
goto io_error;
149
+
150
+
switch (det_mode) {
151
+
case 0x00:
152
+
rt722->jack_type = 0;
153
+
break;
154
+
case 0x03:
155
+
rt722->jack_type = SND_JACK_HEADPHONE;
156
+
break;
157
+
case 0x05:
158
+
rt722->jack_type = SND_JACK_HEADSET;
159
+
break;
160
+
}
161
+
162
+
/* write selected_mode */
163
+
if (det_mode) {
164
+
ret = regmap_write(rt722->regmap,
165
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
166
+
RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode);
167
+
if (ret < 0)
168
+
goto io_error;
169
+
}
170
+
171
+
dev_dbg(&rt722->slave->dev,
172
+
"%s, detected_mode=0x%x\n", __func__, det_mode);
173
+
174
+
return 0;
175
+
176
+
io_error:
177
+
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
178
+
return ret;
179
+
}
180
+
181
+
static void rt722_sdca_jack_detect_handler(struct work_struct *work)
182
+
{
183
+
struct rt722_sdca_priv *rt722 =
184
+
container_of(work, struct rt722_sdca_priv, jack_detect_work.work);
185
+
int btn_type = 0, ret;
186
+
187
+
if (!rt722->hs_jack)
188
+
return;
189
+
190
+
if (!rt722->component->card || !rt722->component->card->instantiated)
191
+
return;
192
+
193
+
/* SDW_SCP_SDCA_INT_SDCA_6 is used for jack detection */
194
+
if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_6 ||
195
+
rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) {
196
+
ret = rt722_sdca_headset_detect(rt722);
197
+
if (ret < 0)
198
+
return;
199
+
}
200
+
201
+
/* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */
202
+
if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8)
203
+
btn_type = rt722_sdca_button_detect(rt722);
204
+
205
+
if (rt722->jack_type == 0)
206
+
btn_type = 0;
207
+
208
+
dev_dbg(&rt722->slave->dev,
209
+
"in %s, jack_type=%d\n", __func__, rt722->jack_type);
210
+
dev_dbg(&rt722->slave->dev,
211
+
"in %s, btn_type=0x%x\n", __func__, btn_type);
212
+
dev_dbg(&rt722->slave->dev,
213
+
"in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
214
+
rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
215
+
216
+
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
217
+
SND_JACK_HEADSET |
218
+
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
219
+
SND_JACK_BTN_2 | SND_JACK_BTN_3);
220
+
221
+
if (btn_type) {
222
+
/* button released */
223
+
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
224
+
SND_JACK_HEADSET |
225
+
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
226
+
SND_JACK_BTN_2 | SND_JACK_BTN_3);
227
+
228
+
mod_delayed_work(system_power_efficient_wq,
229
+
&rt722->jack_btn_check_work, msecs_to_jiffies(200));
230
+
}
231
+
}
232
+
233
+
static void rt722_sdca_btn_check_handler(struct work_struct *work)
234
+
{
235
+
struct rt722_sdca_priv *rt722 =
236
+
container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work);
237
+
int btn_type = 0, ret, idx;
238
+
unsigned int det_mode, offset, val;
239
+
unsigned char buf[3];
240
+
241
+
ret = regmap_read(rt722->regmap,
242
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
243
+
RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
244
+
if (ret < 0)
245
+
goto io_error;
246
+
247
+
/* pin attached */
248
+
if (det_mode) {
249
+
/* read UMP message offset */
250
+
ret = regmap_read(rt722->regmap,
251
+
SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
252
+
RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
253
+
if (ret < 0)
254
+
goto io_error;
255
+
256
+
for (idx = 0; idx < sizeof(buf); idx++) {
257
+
ret = regmap_read(rt722->regmap,
258
+
RT722_BUF_ADDR_HID1 + offset + idx, &val);
259
+
if (ret < 0)
260
+
goto io_error;
261
+
buf[idx] = val & 0xff;
262
+
}
263
+
264
+
if (buf[0] == 0x11)
265
+
btn_type = rt722_sdca_btn_type(&buf[1]);
266
+
} else
267
+
rt722->jack_type = 0;
268
+
269
+
dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type);
270
+
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
271
+
SND_JACK_HEADSET |
272
+
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
273
+
SND_JACK_BTN_2 | SND_JACK_BTN_3);
274
+
275
+
if (btn_type) {
276
+
/* button released */
277
+
snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
278
+
SND_JACK_HEADSET |
279
+
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
280
+
SND_JACK_BTN_2 | SND_JACK_BTN_3);
281
+
282
+
mod_delayed_work(system_power_efficient_wq,
283
+
&rt722->jack_btn_check_work, msecs_to_jiffies(200));
284
+
}
285
+
286
+
return;
287
+
288
+
io_error:
289
+
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
290
+
}
291
+
292
+
static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722)
293
+
{
294
+
mutex_lock(&rt722->calibrate_mutex);
295
+
if (rt722->hs_jack) {
296
+
/* set SCP_SDCA_IntMask1[0]=1 */
297
+
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
298
+
SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6);
299
+
/* set SCP_SDCA_IntMask2[0]=1 */
300
+
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
301
+
SDW_SCP_SDCA_INTMASK_SDCA_8);
302
+
dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__);
303
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
304
+
RT722_HDA_LEGACY_UNSOL_CTL, 0x016E);
305
+
/* set XU(et03h) & XU(et0Dh) to Not bypassed */
306
+
regmap_write(rt722->regmap,
307
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03,
308
+
RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
309
+
regmap_write(rt722->regmap,
310
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D,
311
+
RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
312
+
/* trigger GE interrupt */
313
+
rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
314
+
RT722_GE_RELATED_CTL2, 0x4000, 0x4000);
315
+
}
316
+
mutex_unlock(&rt722->calibrate_mutex);
317
+
}
318
+
319
+
static int rt722_sdca_set_jack_detect(struct snd_soc_component *component,
320
+
struct snd_soc_jack *hs_jack, void *data)
321
+
{
322
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
323
+
int ret;
324
+
325
+
rt722->hs_jack = hs_jack;
326
+
327
+
ret = pm_runtime_resume_and_get(component->dev);
328
+
if (ret < 0) {
329
+
if (ret != -EACCES) {
330
+
dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
331
+
return ret;
332
+
}
333
+
/* pm_runtime not enabled yet */
334
+
dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
335
+
return 0;
336
+
}
337
+
338
+
rt722_sdca_jack_init(rt722);
339
+
340
+
pm_runtime_mark_last_busy(component->dev);
341
+
pm_runtime_put_autosuspend(component->dev);
342
+
343
+
return 0;
344
+
}
345
+
346
+
/* For SDCA control DAC/ADC Gain */
347
+
static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol,
348
+
struct snd_ctl_elem_value *ucontrol)
349
+
{
350
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
351
+
struct soc_mixer_control *mc =
352
+
(struct soc_mixer_control *)kcontrol->private_value;
353
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
354
+
unsigned int read_l, read_r, gain_l_val, gain_r_val;
355
+
unsigned int adc_vol_flag = 0, changed = 0;
356
+
unsigned int lvalue, rvalue;
357
+
const unsigned int interval_offset = 0xc0;
358
+
const unsigned int tendB = 0xa00;
359
+
360
+
if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
361
+
strstr(ucontrol->id.name, "FU0F Capture Volume"))
362
+
adc_vol_flag = 1;
363
+
364
+
regmap_read(rt722->mbq_regmap, mc->reg, &lvalue);
365
+
regmap_read(rt722->mbq_regmap, mc->rreg, &rvalue);
366
+
367
+
/* L Channel */
368
+
gain_l_val = ucontrol->value.integer.value[0];
369
+
if (gain_l_val > mc->max)
370
+
gain_l_val = mc->max;
371
+
372
+
if (mc->shift == 8) /* boost gain */
373
+
gain_l_val = gain_l_val * tendB;
374
+
else {
375
+
/* ADC/DAC gain */
376
+
if (adc_vol_flag)
377
+
gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset);
378
+
else
379
+
gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
380
+
gain_l_val &= 0xffff;
381
+
}
382
+
383
+
/* R Channel */
384
+
gain_r_val = ucontrol->value.integer.value[1];
385
+
if (gain_r_val > mc->max)
386
+
gain_r_val = mc->max;
387
+
388
+
if (mc->shift == 8) /* boost gain */
389
+
gain_r_val = gain_r_val * tendB;
390
+
else {
391
+
/* ADC/DAC gain */
392
+
if (adc_vol_flag)
393
+
gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset);
394
+
else
395
+
gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
396
+
gain_r_val &= 0xffff;
397
+
}
398
+
399
+
if (lvalue != gain_l_val || rvalue != gain_r_val)
400
+
changed = 1;
401
+
else
402
+
return 0;
403
+
404
+
/* Lch*/
405
+
regmap_write(rt722->mbq_regmap, mc->reg, gain_l_val);
406
+
407
+
/* Rch */
408
+
regmap_write(rt722->mbq_regmap, mc->rreg, gain_r_val);
409
+
410
+
regmap_read(rt722->mbq_regmap, mc->reg, &read_l);
411
+
regmap_read(rt722->mbq_regmap, mc->rreg, &read_r);
412
+
if (read_r == gain_r_val && read_l == gain_l_val)
413
+
return changed;
414
+
415
+
return -EIO;
416
+
}
417
+
418
+
static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol,
419
+
struct snd_ctl_elem_value *ucontrol)
420
+
{
421
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
422
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
423
+
struct soc_mixer_control *mc =
424
+
(struct soc_mixer_control *)kcontrol->private_value;
425
+
unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
426
+
unsigned int adc_vol_flag = 0;
427
+
const unsigned int interval_offset = 0xc0;
428
+
const unsigned int tendB = 0xa00;
429
+
430
+
if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
431
+
strstr(ucontrol->id.name, "FU0F Capture Volume"))
432
+
adc_vol_flag = 1;
433
+
434
+
regmap_read(rt722->mbq_regmap, mc->reg, &read_l);
435
+
regmap_read(rt722->mbq_regmap, mc->rreg, &read_r);
436
+
437
+
if (mc->shift == 8) /* boost gain */
438
+
ctl_l = read_l / tendB;
439
+
else {
440
+
if (adc_vol_flag)
441
+
ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset);
442
+
else
443
+
ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
444
+
}
445
+
446
+
if (read_l != read_r) {
447
+
if (mc->shift == 8) /* boost gain */
448
+
ctl_r = read_r / tendB;
449
+
else { /* ADC/DAC gain */
450
+
if (adc_vol_flag)
451
+
ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset);
452
+
else
453
+
ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
454
+
}
455
+
} else {
456
+
ctl_r = ctl_l;
457
+
}
458
+
459
+
ucontrol->value.integer.value[0] = ctl_l;
460
+
ucontrol->value.integer.value[1] = ctl_r;
461
+
462
+
return 0;
463
+
}
464
+
465
+
static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722)
466
+
{
467
+
int err, i;
468
+
unsigned int ch_mute;
469
+
470
+
for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) {
471
+
ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i];
472
+
err = regmap_write(rt722->regmap,
473
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
474
+
RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
475
+
if (err < 0)
476
+
return err;
477
+
}
478
+
479
+
return 0;
480
+
}
481
+
482
+
static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol,
483
+
struct snd_ctl_elem_value *ucontrol)
484
+
{
485
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
486
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
487
+
struct rt722_sdca_dmic_kctrl_priv *p =
488
+
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
489
+
unsigned int i;
490
+
491
+
for (i = 0; i < p->count; i++)
492
+
ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i];
493
+
494
+
return 0;
495
+
}
496
+
497
+
static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol,
498
+
struct snd_ctl_elem_value *ucontrol)
499
+
{
500
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
501
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
502
+
struct rt722_sdca_dmic_kctrl_priv *p =
503
+
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
504
+
int err, changed = 0, i;
505
+
506
+
for (i = 0; i < p->count; i++) {
507
+
if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i])
508
+
changed = 1;
509
+
rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i];
510
+
}
511
+
512
+
err = rt722_sdca_set_fu1e_capture_ctl(rt722);
513
+
if (err < 0)
514
+
return err;
515
+
516
+
return changed;
517
+
}
518
+
519
+
static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722)
520
+
{
521
+
int err;
522
+
unsigned int ch_l, ch_r;
523
+
524
+
ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00;
525
+
ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00;
526
+
527
+
err = regmap_write(rt722->regmap,
528
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
529
+
RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l);
530
+
if (err < 0)
531
+
return err;
532
+
533
+
err = regmap_write(rt722->regmap,
534
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
535
+
RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r);
536
+
if (err < 0)
537
+
return err;
538
+
539
+
return 0;
540
+
}
541
+
542
+
static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol,
543
+
struct snd_ctl_elem_value *ucontrol)
544
+
{
545
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
546
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
547
+
548
+
ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute;
549
+
ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute;
550
+
return 0;
551
+
}
552
+
553
+
static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol,
554
+
struct snd_ctl_elem_value *ucontrol)
555
+
{
556
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
557
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
558
+
int err, changed = 0;
559
+
560
+
if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] ||
561
+
rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1])
562
+
changed = 1;
563
+
564
+
rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0];
565
+
rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1];
566
+
err = rt722_sdca_set_fu0f_capture_ctl(rt722);
567
+
if (err < 0)
568
+
return err;
569
+
570
+
return changed;
571
+
}
572
+
573
+
static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol,
574
+
struct snd_ctl_elem_info *uinfo)
575
+
{
576
+
struct rt722_sdca_dmic_kctrl_priv *p =
577
+
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
578
+
579
+
if (p->max == 1)
580
+
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
581
+
else
582
+
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
583
+
uinfo->count = p->count;
584
+
uinfo->value.integer.min = 0;
585
+
uinfo->value.integer.max = p->max;
586
+
return 0;
587
+
}
588
+
589
+
static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol,
590
+
struct snd_ctl_elem_value *ucontrol)
591
+
{
592
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
593
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
594
+
struct rt722_sdca_dmic_kctrl_priv *p =
595
+
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
596
+
unsigned int boost_step = 0x0a00;
597
+
unsigned int vol_max = 0x1e00;
598
+
unsigned int regvalue, ctl, i;
599
+
unsigned int adc_vol_flag = 0;
600
+
const unsigned int interval_offset = 0xc0;
601
+
602
+
if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
603
+
adc_vol_flag = 1;
604
+
605
+
/* check all channels */
606
+
for (i = 0; i < p->count; i++) {
607
+
regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value);
608
+
609
+
if (!adc_vol_flag) /* boost gain */
610
+
ctl = regvalue / boost_step;
611
+
else { /* ADC gain */
612
+
if (adc_vol_flag)
613
+
ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset);
614
+
else
615
+
ctl = p->max - (((0 - regvalue) & 0xffff) / interval_offset);
616
+
}
617
+
618
+
ucontrol->value.integer.value[i] = ctl;
619
+
}
620
+
621
+
return 0;
622
+
}
623
+
624
+
static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol,
625
+
struct snd_ctl_elem_value *ucontrol)
626
+
{
627
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
628
+
struct rt722_sdca_dmic_kctrl_priv *p =
629
+
(struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
630
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
631
+
unsigned int boost_step = 0x0a00;
632
+
unsigned int vol_max = 0x1e00;
633
+
unsigned int gain_val[4];
634
+
unsigned int i, adc_vol_flag = 0, changed = 0;
635
+
unsigned int regvalue[4];
636
+
const unsigned int interval_offset = 0xc0;
637
+
int err;
638
+
639
+
if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
640
+
adc_vol_flag = 1;
641
+
642
+
/* check all channels */
643
+
for (i = 0; i < p->count; i++) {
644
+
regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value[i]);
645
+
646
+
gain_val[i] = ucontrol->value.integer.value[i];
647
+
if (gain_val[i] > p->max)
648
+
gain_val[i] = p->max;
649
+
650
+
if (!adc_vol_flag) /* boost gain */
651
+
gain_val[i] = gain_val[i] * boost_step;
652
+
else { /* ADC gain */
653
+
gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset);
654
+
gain_val[i] &= 0xffff;
655
+
}
656
+
657
+
if (regvalue[i] != gain_val[i])
658
+
changed = 1;
659
+
}
660
+
661
+
if (!changed)
662
+
return 0;
663
+
664
+
for (i = 0; i < p->count; i++) {
665
+
err = regmap_write(rt722->mbq_regmap, p->reg_base + i, gain_val[i]);
666
+
if (err < 0)
667
+
dev_err(&rt722->slave->dev, "%#08x can't be set\n", p->reg_base + i);
668
+
}
669
+
670
+
return changed;
671
+
}
672
+
673
+
#define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \
674
+
((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \
675
+
{.reg_base = xreg_base, .count = xcount, .max = xmax, \
676
+
.invert = xinvert})
677
+
678
+
#define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
679
+
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
680
+
.info = rt722_sdca_fu_info, \
681
+
.get = rt722_sdca_fu1e_capture_get, \
682
+
.put = rt722_sdca_fu1e_capture_put, \
683
+
.private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
684
+
685
+
#define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
686
+
xhandler_put, xcount, xmax, tlv_array) \
687
+
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
688
+
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
689
+
SNDRV_CTL_ELEM_ACCESS_READWRITE, \
690
+
.tlv.p = (tlv_array), \
691
+
.info = rt722_sdca_fu_info, \
692
+
.get = xhandler_get, .put = xhandler_put, \
693
+
.private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
694
+
695
+
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
696
+
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0);
697
+
static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0);
698
+
699
+
static const struct snd_kcontrol_new rt722_sdca_controls[] = {
700
+
/* Headphone playback settings */
701
+
SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume",
702
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
703
+
RT722_SDCA_CTL_FU_VOLUME, CH_L),
704
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
705
+
RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
706
+
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
707
+
/* Headset mic capture settings */
708
+
SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
709
+
rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put),
710
+
SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume",
711
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
712
+
RT722_SDCA_CTL_FU_VOLUME, CH_L),
713
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
714
+
RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0,
715
+
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv),
716
+
SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume",
717
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
718
+
RT722_SDCA_CTL_FU_CH_GAIN, CH_L),
719
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
720
+
RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0,
721
+
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv),
722
+
/* AMP playback settings */
723
+
SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume",
724
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
725
+
RT722_SDCA_CTL_FU_VOLUME, CH_L),
726
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
727
+
RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
728
+
rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
729
+
/* DMIC capture settings */
730
+
RT722_SDCA_FU_CTRL("FU1E Capture Switch",
731
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
732
+
RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4),
733
+
RT722_SDCA_EXT_TLV("FU1E Capture Volume",
734
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
735
+
RT722_SDCA_CTL_FU_VOLUME, CH_01),
736
+
rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
737
+
4, 0x3f, mic_vol_tlv),
738
+
RT722_SDCA_EXT_TLV("FU15 Boost Volume",
739
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15,
740
+
RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
741
+
rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
742
+
4, 3, boost_vol_tlv),
743
+
};
744
+
745
+
static int rt722_sdca_adc_mux_get(struct snd_kcontrol *kcontrol,
746
+
struct snd_ctl_elem_value *ucontrol)
747
+
{
748
+
struct snd_soc_component *component =
749
+
snd_soc_dapm_kcontrol_component(kcontrol);
750
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
751
+
unsigned int val = 0, mask_sft;
752
+
753
+
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
754
+
mask_sft = 12;
755
+
else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
756
+
mask_sft = 4;
757
+
else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
758
+
mask_sft = 0;
759
+
else
760
+
return -EINVAL;
761
+
762
+
rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL,
763
+
RT722_HDA_LEGACY_MUX_CTL0, &val);
764
+
765
+
ucontrol->value.enumerated.item[0] = (val >> mask_sft) & 0x7;
766
+
767
+
return 0;
768
+
}
769
+
770
+
static int rt722_sdca_adc_mux_put(struct snd_kcontrol *kcontrol,
771
+
struct snd_ctl_elem_value *ucontrol)
772
+
{
773
+
struct snd_soc_component *component =
774
+
snd_soc_dapm_kcontrol_component(kcontrol);
775
+
struct snd_soc_dapm_context *dapm =
776
+
snd_soc_dapm_kcontrol_dapm(kcontrol);
777
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
778
+
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
779
+
unsigned int *item = ucontrol->value.enumerated.item;
780
+
unsigned int val, val2 = 0, change, mask_sft;
781
+
782
+
if (item[0] >= e->items)
783
+
return -EINVAL;
784
+
785
+
if (strstr(ucontrol->id.name, "ADC 22 Mux"))
786
+
mask_sft = 12;
787
+
else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
788
+
mask_sft = 4;
789
+
else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
790
+
mask_sft = 0;
791
+
else
792
+
return -EINVAL;
793
+
794
+
val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
795
+
796
+
rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL,
797
+
RT722_HDA_LEGACY_MUX_CTL0, &val2);
798
+
val2 = (0x7 << mask_sft) & val2;
799
+
800
+
if (val == val2)
801
+
change = 0;
802
+
else
803
+
change = 1;
804
+
805
+
if (change)
806
+
rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
807
+
RT722_HDA_LEGACY_MUX_CTL0, 0x7 << mask_sft,
808
+
val << mask_sft);
809
+
810
+
snd_soc_dapm_mux_update_power(dapm, kcontrol,
811
+
item[0], e, NULL);
812
+
813
+
return change;
814
+
}
815
+
816
+
static const char * const adc22_mux_text[] = {
817
+
"MIC2",
818
+
"LINE1",
819
+
"LINE2",
820
+
};
821
+
822
+
static const char * const adc07_10_mux_text[] = {
823
+
"DMIC1",
824
+
"DMIC2",
825
+
};
826
+
827
+
static SOC_ENUM_SINGLE_DECL(
828
+
rt722_adc22_enum, SND_SOC_NOPM, 0, adc22_mux_text);
829
+
830
+
static SOC_ENUM_SINGLE_DECL(
831
+
rt722_adc24_enum, SND_SOC_NOPM, 0, adc07_10_mux_text);
832
+
833
+
static SOC_ENUM_SINGLE_DECL(
834
+
rt722_adc25_enum, SND_SOC_NOPM, 0, adc07_10_mux_text);
835
+
836
+
static const struct snd_kcontrol_new rt722_sdca_adc22_mux =
837
+
SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt722_adc22_enum,
838
+
rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
839
+
840
+
static const struct snd_kcontrol_new rt722_sdca_adc24_mux =
841
+
SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt722_adc24_enum,
842
+
rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
843
+
844
+
static const struct snd_kcontrol_new rt722_sdca_adc25_mux =
845
+
SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt722_adc25_enum,
846
+
rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
847
+
848
+
static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w,
849
+
struct snd_kcontrol *kcontrol, int event)
850
+
{
851
+
struct snd_soc_component *component =
852
+
snd_soc_dapm_to_component(w->dapm);
853
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
854
+
unsigned char unmute = 0x0, mute = 0x1;
855
+
856
+
switch (event) {
857
+
case SND_SOC_DAPM_POST_PMU:
858
+
regmap_write(rt722->regmap,
859
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
860
+
RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
861
+
regmap_write(rt722->regmap,
862
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
863
+
RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
864
+
break;
865
+
case SND_SOC_DAPM_PRE_PMD:
866
+
regmap_write(rt722->regmap,
867
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
868
+
RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
869
+
regmap_write(rt722->regmap,
870
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
871
+
RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
872
+
break;
873
+
}
874
+
return 0;
875
+
}
876
+
877
+
static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w,
878
+
struct snd_kcontrol *kcontrol, int event)
879
+
{
880
+
struct snd_soc_component *component =
881
+
snd_soc_dapm_to_component(w->dapm);
882
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
883
+
unsigned char unmute = 0x0, mute = 0x1;
884
+
885
+
switch (event) {
886
+
case SND_SOC_DAPM_POST_PMU:
887
+
regmap_write(rt722->regmap,
888
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
889
+
RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
890
+
regmap_write(rt722->regmap,
891
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
892
+
RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
893
+
break;
894
+
case SND_SOC_DAPM_PRE_PMD:
895
+
regmap_write(rt722->regmap,
896
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
897
+
RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
898
+
regmap_write(rt722->regmap,
899
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
900
+
RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
901
+
break;
902
+
}
903
+
return 0;
904
+
}
905
+
906
+
static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w,
907
+
struct snd_kcontrol *kcontrol, int event)
908
+
{
909
+
struct snd_soc_component *component =
910
+
snd_soc_dapm_to_component(w->dapm);
911
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
912
+
913
+
switch (event) {
914
+
case SND_SOC_DAPM_POST_PMU:
915
+
rt722->fu1e_dapm_mute = false;
916
+
rt722_sdca_set_fu1e_capture_ctl(rt722);
917
+
break;
918
+
case SND_SOC_DAPM_PRE_PMD:
919
+
rt722->fu1e_dapm_mute = true;
920
+
rt722_sdca_set_fu1e_capture_ctl(rt722);
921
+
break;
922
+
}
923
+
return 0;
924
+
}
925
+
926
+
static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w,
927
+
struct snd_kcontrol *kcontrol, int event)
928
+
{
929
+
struct snd_soc_component *component =
930
+
snd_soc_dapm_to_component(w->dapm);
931
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
932
+
933
+
switch (event) {
934
+
case SND_SOC_DAPM_POST_PMU:
935
+
rt722->fu0f_dapm_mute = false;
936
+
rt722_sdca_set_fu0f_capture_ctl(rt722);
937
+
break;
938
+
case SND_SOC_DAPM_PRE_PMD:
939
+
rt722->fu0f_dapm_mute = true;
940
+
rt722_sdca_set_fu0f_capture_ctl(rt722);
941
+
break;
942
+
}
943
+
return 0;
944
+
}
945
+
946
+
static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w,
947
+
struct snd_kcontrol *kcontrol, int event)
948
+
{
949
+
struct snd_soc_component *component =
950
+
snd_soc_dapm_to_component(w->dapm);
951
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
952
+
unsigned char ps0 = 0x0, ps3 = 0x3;
953
+
954
+
switch (event) {
955
+
case SND_SOC_DAPM_POST_PMU:
956
+
regmap_write(rt722->regmap,
957
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
958
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
959
+
break;
960
+
case SND_SOC_DAPM_PRE_PMD:
961
+
regmap_write(rt722->regmap,
962
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
963
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
964
+
break;
965
+
}
966
+
return 0;
967
+
}
968
+
969
+
static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w,
970
+
struct snd_kcontrol *kcontrol, int event)
971
+
{
972
+
struct snd_soc_component *component =
973
+
snd_soc_dapm_to_component(w->dapm);
974
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
975
+
unsigned char ps0 = 0x0, ps3 = 0x3;
976
+
977
+
switch (event) {
978
+
case SND_SOC_DAPM_POST_PMU:
979
+
regmap_write(rt722->regmap,
980
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
981
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
982
+
break;
983
+
case SND_SOC_DAPM_PRE_PMD:
984
+
regmap_write(rt722->regmap,
985
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
986
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
987
+
break;
988
+
}
989
+
return 0;
990
+
}
991
+
992
+
static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w,
993
+
struct snd_kcontrol *kcontrol, int event)
994
+
{
995
+
struct snd_soc_component *component =
996
+
snd_soc_dapm_to_component(w->dapm);
997
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
998
+
unsigned char ps0 = 0x0, ps3 = 0x3;
999
+
1000
+
switch (event) {
1001
+
case SND_SOC_DAPM_POST_PMU:
1002
+
regmap_write(rt722->regmap,
1003
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
1004
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1005
+
break;
1006
+
case SND_SOC_DAPM_PRE_PMD:
1007
+
regmap_write(rt722->regmap,
1008
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
1009
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1010
+
break;
1011
+
}
1012
+
return 0;
1013
+
}
1014
+
1015
+
static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w,
1016
+
struct snd_kcontrol *kcontrol, int event)
1017
+
{
1018
+
struct snd_soc_component *component =
1019
+
snd_soc_dapm_to_component(w->dapm);
1020
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1021
+
unsigned char ps0 = 0x0, ps3 = 0x3;
1022
+
1023
+
switch (event) {
1024
+
case SND_SOC_DAPM_POST_PMU:
1025
+
regmap_write(rt722->regmap,
1026
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
1027
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1028
+
break;
1029
+
case SND_SOC_DAPM_PRE_PMD:
1030
+
regmap_write(rt722->regmap,
1031
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
1032
+
RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1033
+
break;
1034
+
}
1035
+
return 0;
1036
+
}
1037
+
1038
+
static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = {
1039
+
SND_SOC_DAPM_OUTPUT("HP"),
1040
+
SND_SOC_DAPM_OUTPUT("SPK"),
1041
+
SND_SOC_DAPM_INPUT("MIC2"),
1042
+
SND_SOC_DAPM_INPUT("LINE1"),
1043
+
SND_SOC_DAPM_INPUT("LINE2"),
1044
+
SND_SOC_DAPM_INPUT("DMIC1_2"),
1045
+
SND_SOC_DAPM_INPUT("DMIC3_4"),
1046
+
1047
+
SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1048
+
rt722_sdca_pde23_event,
1049
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1050
+
SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0,
1051
+
rt722_sdca_pde47_event,
1052
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1053
+
SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
1054
+
rt722_sdca_pde11_event,
1055
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1056
+
SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0,
1057
+
rt722_sdca_pde12_event,
1058
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1059
+
1060
+
SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0,
1061
+
rt722_sdca_fu21_event,
1062
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1063
+
SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0,
1064
+
rt722_sdca_fu42_event,
1065
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1066
+
SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0,
1067
+
rt722_sdca_fu36_event,
1068
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1069
+
SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0,
1070
+
rt722_sdca_fu113_event,
1071
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1072
+
SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
1073
+
&rt722_sdca_adc22_mux),
1074
+
SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
1075
+
&rt722_sdca_adc24_mux),
1076
+
SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
1077
+
&rt722_sdca_adc25_mux),
1078
+
1079
+
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0),
1080
+
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0),
1081
+
SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0),
1082
+
SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0),
1083
+
};
1084
+
1085
+
static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = {
1086
+
{"FU 42", NULL, "DP1RX"},
1087
+
{"FU 21", NULL, "DP3RX"},
1088
+
1089
+
{"ADC 22 Mux", "MIC2", "MIC2"},
1090
+
{"ADC 22 Mux", "LINE1", "LINE1"},
1091
+
{"ADC 22 Mux", "LINE2", "LINE2"},
1092
+
{"ADC 24 Mux", "DMIC1", "DMIC1_2"},
1093
+
{"ADC 24 Mux", "DMIC2", "DMIC3_4"},
1094
+
{"ADC 25 Mux", "DMIC1", "DMIC1_2"},
1095
+
{"ADC 25 Mux", "DMIC2", "DMIC3_4"},
1096
+
{"FU 36", NULL, "PDE 12"},
1097
+
{"FU 36", NULL, "ADC 22 Mux"},
1098
+
{"FU 113", NULL, "PDE 11"},
1099
+
{"FU 113", NULL, "ADC 24 Mux"},
1100
+
{"FU 113", NULL, "ADC 25 Mux"},
1101
+
{"DP2TX", NULL, "FU 36"},
1102
+
{"DP6TX", NULL, "FU 113"},
1103
+
1104
+
{"HP", NULL, "PDE 47"},
1105
+
{"HP", NULL, "FU 42"},
1106
+
{"SPK", NULL, "PDE 23"},
1107
+
{"SPK", NULL, "FU 21"},
1108
+
};
1109
+
1110
+
static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev)
1111
+
{
1112
+
device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src);
1113
+
1114
+
return 0;
1115
+
}
1116
+
1117
+
static int rt722_sdca_probe(struct snd_soc_component *component)
1118
+
{
1119
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1120
+
int ret;
1121
+
1122
+
rt722_sdca_parse_dt(rt722, &rt722->slave->dev);
1123
+
rt722->component = component;
1124
+
1125
+
ret = pm_runtime_resume(component->dev);
1126
+
if (ret < 0 && ret != -EACCES)
1127
+
return ret;
1128
+
1129
+
return 0;
1130
+
}
1131
+
1132
+
static const struct snd_soc_component_driver soc_sdca_dev_rt722 = {
1133
+
.probe = rt722_sdca_probe,
1134
+
.controls = rt722_sdca_controls,
1135
+
.num_controls = ARRAY_SIZE(rt722_sdca_controls),
1136
+
.dapm_widgets = rt722_sdca_dapm_widgets,
1137
+
.num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets),
1138
+
.dapm_routes = rt722_sdca_audio_map,
1139
+
.num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map),
1140
+
.set_jack = rt722_sdca_set_jack_detect,
1141
+
.endianness = 1,
1142
+
};
1143
+
1144
+
static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
1145
+
int direction)
1146
+
{
1147
+
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
1148
+
1149
+
return 0;
1150
+
}
1151
+
1152
+
static void rt722_sdca_shutdown(struct snd_pcm_substream *substream,
1153
+
struct snd_soc_dai *dai)
1154
+
{
1155
+
snd_soc_dai_set_dma_data(dai, substream, NULL);
1156
+
}
1157
+
1158
+
static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
1159
+
struct snd_pcm_hw_params *params,
1160
+
struct snd_soc_dai *dai)
1161
+
{
1162
+
struct snd_soc_component *component = dai->component;
1163
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1164
+
struct sdw_stream_config stream_config;
1165
+
struct sdw_port_config port_config;
1166
+
enum sdw_data_direction direction;
1167
+
struct sdw_stream_runtime *sdw_stream;
1168
+
int retval, port, num_channels;
1169
+
unsigned int sampling_rate;
1170
+
1171
+
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
1172
+
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
1173
+
1174
+
if (!sdw_stream)
1175
+
return -EINVAL;
1176
+
1177
+
if (!rt722->slave)
1178
+
return -EINVAL;
1179
+
1180
+
/*
1181
+
* RT722_AIF1 with port = 1 for headphone playback
1182
+
* RT722_AIF1 with port = 2 for headset-mic capture
1183
+
* RT722_AIF2 with port = 3 for speaker playback
1184
+
* RT722_AIF3 with port = 6 for digital-mic capture
1185
+
*/
1186
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1187
+
direction = SDW_DATA_DIR_RX;
1188
+
if (dai->id == RT722_AIF1)
1189
+
port = 1;
1190
+
else if (dai->id == RT722_AIF2)
1191
+
port = 3;
1192
+
else
1193
+
return -EINVAL;
1194
+
} else {
1195
+
direction = SDW_DATA_DIR_TX;
1196
+
if (dai->id == RT722_AIF1)
1197
+
port = 2;
1198
+
else if (dai->id == RT722_AIF3)
1199
+
port = 6;
1200
+
else
1201
+
return -EINVAL;
1202
+
}
1203
+
stream_config.frame_rate = params_rate(params);
1204
+
stream_config.ch_count = params_channels(params);
1205
+
stream_config.bps = snd_pcm_format_width(params_format(params));
1206
+
stream_config.direction = direction;
1207
+
1208
+
num_channels = params_channels(params);
1209
+
port_config.ch_mask = GENMASK(num_channels - 1, 0);
1210
+
port_config.num = port;
1211
+
1212
+
retval = sdw_stream_add_slave(rt722->slave, &stream_config,
1213
+
&port_config, 1, sdw_stream);
1214
+
if (retval) {
1215
+
dev_err(dai->dev, "Unable to configure port\n");
1216
+
return retval;
1217
+
}
1218
+
1219
+
if (params_channels(params) > 16) {
1220
+
dev_err(component->dev, "Unsupported channels %d\n",
1221
+
params_channels(params));
1222
+
return -EINVAL;
1223
+
}
1224
+
1225
+
/* sampling rate configuration */
1226
+
switch (params_rate(params)) {
1227
+
case 44100:
1228
+
sampling_rate = RT722_SDCA_RATE_44100HZ;
1229
+
break;
1230
+
case 48000:
1231
+
sampling_rate = RT722_SDCA_RATE_48000HZ;
1232
+
break;
1233
+
case 96000:
1234
+
sampling_rate = RT722_SDCA_RATE_96000HZ;
1235
+
break;
1236
+
case 192000:
1237
+
sampling_rate = RT722_SDCA_RATE_192000HZ;
1238
+
break;
1239
+
default:
1240
+
dev_err(component->dev, "Rate %d is not supported\n",
1241
+
params_rate(params));
1242
+
return -EINVAL;
1243
+
}
1244
+
1245
+
/* set sampling frequency */
1246
+
if (dai->id == RT722_AIF1) {
1247
+
regmap_write(rt722->regmap,
1248
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01,
1249
+
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1250
+
regmap_write(rt722->regmap,
1251
+
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11,
1252
+
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1253
+
}
1254
+
1255
+
if (dai->id == RT722_AIF2)
1256
+
regmap_write(rt722->regmap,
1257
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31,
1258
+
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1259
+
1260
+
if (dai->id == RT722_AIF3)
1261
+
regmap_write(rt722->regmap,
1262
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F,
1263
+
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1264
+
1265
+
return 0;
1266
+
}
1267
+
1268
+
static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
1269
+
struct snd_soc_dai *dai)
1270
+
{
1271
+
struct snd_soc_component *component = dai->component;
1272
+
struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1273
+
struct sdw_stream_runtime *sdw_stream =
1274
+
snd_soc_dai_get_dma_data(dai, substream);
1275
+
1276
+
if (!rt722->slave)
1277
+
return -EINVAL;
1278
+
1279
+
sdw_stream_remove_slave(rt722->slave, sdw_stream);
1280
+
return 0;
1281
+
}
1282
+
1283
+
#define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
1284
+
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
1285
+
#define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1286
+
SNDRV_PCM_FMTBIT_S24_LE)
1287
+
1288
+
static const struct snd_soc_dai_ops rt722_sdca_ops = {
1289
+
.hw_params = rt722_sdca_pcm_hw_params,
1290
+
.hw_free = rt722_sdca_pcm_hw_free,
1291
+
.set_stream = rt722_sdca_set_sdw_stream,
1292
+
.shutdown = rt722_sdca_shutdown,
1293
+
};
1294
+
1295
+
static struct snd_soc_dai_driver rt722_sdca_dai[] = {
1296
+
{
1297
+
.name = "rt722-sdca-aif1",
1298
+
.id = RT722_AIF1,
1299
+
.playback = {
1300
+
.stream_name = "DP1 Headphone Playback",
1301
+
.channels_min = 1,
1302
+
.channels_max = 2,
1303
+
.rates = RT722_STEREO_RATES,
1304
+
.formats = RT722_FORMATS,
1305
+
},
1306
+
.capture = {
1307
+
.stream_name = "DP2 Headset Capture",
1308
+
.channels_min = 1,
1309
+
.channels_max = 2,
1310
+
.rates = RT722_STEREO_RATES,
1311
+
.formats = RT722_FORMATS,
1312
+
},
1313
+
.ops = &rt722_sdca_ops,
1314
+
},
1315
+
{
1316
+
.name = "rt722-sdca-aif2",
1317
+
.id = RT722_AIF2,
1318
+
.playback = {
1319
+
.stream_name = "DP3 Speaker Playback",
1320
+
.channels_min = 1,
1321
+
.channels_max = 2,
1322
+
.rates = RT722_STEREO_RATES,
1323
+
.formats = RT722_FORMATS,
1324
+
},
1325
+
.ops = &rt722_sdca_ops,
1326
+
},
1327
+
{
1328
+
.name = "rt722-sdca-aif3",
1329
+
.id = RT722_AIF3,
1330
+
.capture = {
1331
+
.stream_name = "DP6 DMic Capture",
1332
+
.channels_min = 1,
1333
+
.channels_max = 2,
1334
+
.rates = RT722_STEREO_RATES,
1335
+
.formats = RT722_FORMATS,
1336
+
},
1337
+
.ops = &rt722_sdca_ops,
1338
+
}
1339
+
};
1340
+
1341
+
int rt722_sdca_init(struct device *dev, struct regmap *regmap,
1342
+
struct regmap *mbq_regmap, struct sdw_slave *slave)
1343
+
{
1344
+
struct rt722_sdca_priv *rt722;
1345
+
1346
+
rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL);
1347
+
if (!rt722)
1348
+
return -ENOMEM;
1349
+
1350
+
dev_set_drvdata(dev, rt722);
1351
+
rt722->slave = slave;
1352
+
rt722->regmap = regmap;
1353
+
rt722->mbq_regmap = mbq_regmap;
1354
+
1355
+
mutex_init(&rt722->calibrate_mutex);
1356
+
mutex_init(&rt722->disable_irq_lock);
1357
+
1358
+
INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler);
1359
+
INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler);
1360
+
1361
+
/*
1362
+
* Mark hw_init to false
1363
+
* HW init will be performed when device reports present
1364
+
*/
1365
+
rt722->hw_init = false;
1366
+
rt722->first_hw_init = false;
1367
+
rt722->fu1e_dapm_mute = true;
1368
+
rt722->fu0f_dapm_mute = true;
1369
+
rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true;
1370
+
rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] =
1371
+
rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true;
1372
+
1373
+
return devm_snd_soc_register_component(dev,
1374
+
&soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai));
1375
+
}
1376
+
1377
+
static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722)
1378
+
{
1379
+
/* Set AD07 power entity floating control */
1380
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1381
+
RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29);
1382
+
/* Set AD10 power entity floating control */
1383
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1384
+
RT722_ADC10_PDE_FLOAT_CTL, 0x2a00);
1385
+
/* Set DMIC1/DMIC2 power entity floating control */
1386
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1387
+
RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a);
1388
+
/* Set DMIC2 IT entity floating control */
1389
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1390
+
RT722_DMIC_ENT_FLOAT_CTL, 0x2626);
1391
+
/* Set AD10 FU entity floating control */
1392
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1393
+
RT722_ADC_ENT_FLOAT_CTL, 0x1e00);
1394
+
/* Set DMIC2 FU entity floating control */
1395
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1396
+
RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515);
1397
+
/* Set AD10 FU channel floating control */
1398
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1399
+
RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304);
1400
+
/* Set DMIC2 FU channel floating control */
1401
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1402
+
RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304);
1403
+
/* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */
1404
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1405
+
RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000);
1406
+
/* Enable vf707_r12_05/vf707_r13_05 */
1407
+
regmap_write(rt722->regmap,
1408
+
SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26,
1409
+
RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01);
1410
+
/* Fine tune PDE2A latency */
1411
+
regmap_write(rt722->regmap, 0x2f5c, 0x25);
1412
+
}
1413
+
1414
+
static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722)
1415
+
{
1416
+
/* Set DVQ=01 */
1417
+
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1418
+
0xc215);
1419
+
/* Reset dc_cal_top */
1420
+
rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1421
+
0x702c);
1422
+
/* W1C Trigger Calibration */
1423
+
rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1424
+
0xf02d);
1425
+
/* Set DAC02/ClassD power entity floating control */
1426
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL,
1427
+
0x2323);
1428
+
/* Set EAPD high */
1429
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL,
1430
+
0x0002);
1431
+
/* Enable vf707_r14 */
1432
+
regmap_write(rt722->regmap,
1433
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23,
1434
+
RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04);
1435
+
}
1436
+
1437
+
static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722)
1438
+
{
1439
+
int loop_check, chk_cnt = 100, ret;
1440
+
unsigned int calib_status = 0;
1441
+
1442
+
/* Read eFuse */
1443
+
rt722_sdca_index_write(rt722, RT722_VENDOR_SPK_EFUSE, RT722_DC_CALIB_CTRL,
1444
+
0x4808);
1445
+
/* Button A, B, C, D bypass mode */
1446
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4,
1447
+
0xcf00);
1448
+
/* HID1 slot enable */
1449
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5,
1450
+
0x000f);
1451
+
/* Report ID for HID1 */
1452
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0,
1453
+
0x1100);
1454
+
/* OSC/OOC for slot 2, 3 */
1455
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7,
1456
+
0x0c12);
1457
+
/* Set JD de-bounce clock control */
1458
+
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1,
1459
+
0x7002);
1460
+
/* Set DVQ=01 */
1461
+
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1462
+
0xc215);
1463
+
/* FSM switch to calibration manual mode */
1464
+
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL,
1465
+
0x4100);
1466
+
/* W1C Trigger DC calibration (HP) */
1467
+
rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3,
1468
+
0x008d);
1469
+
/* check HP calibration FSM status */
1470
+
for (loop_check = 0; loop_check < chk_cnt; loop_check++) {
1471
+
ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI,
1472
+
RT722_DAC_DC_CALI_CTL3, &calib_status);
1473
+
if (ret < 0 || loop_check == chk_cnt)
1474
+
dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret);
1475
+
if ((calib_status & 0x0040) == 0x0)
1476
+
break;
1477
+
}
1478
+
/* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */
1479
+
rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4,
1480
+
0x0010);
1481
+
/* Set ADC09 power entity floating control */
1482
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL,
1483
+
0x2a12);
1484
+
/* Set MIC2 and LINE1 power entity floating control */
1485
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL,
1486
+
0x3429);
1487
+
/* Set ET41h and LINE2 power entity floating control */
1488
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL,
1489
+
0x4112);
1490
+
/* Set DAC03 and HP power entity floating control */
1491
+
rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL,
1492
+
0x4040);
1493
+
/* Fine tune PDE40 latency */
1494
+
regmap_write(rt722->regmap, 0x2f58, 0x07);
1495
+
}
1496
+
1497
+
int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave)
1498
+
{
1499
+
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
1500
+
1501
+
rt722->disable_irq = false;
1502
+
1503
+
if (rt722->hw_init)
1504
+
return 0;
1505
+
1506
+
if (rt722->first_hw_init) {
1507
+
regcache_cache_only(rt722->regmap, false);
1508
+
regcache_cache_bypass(rt722->regmap, true);
1509
+
regcache_cache_only(rt722->mbq_regmap, false);
1510
+
regcache_cache_bypass(rt722->mbq_regmap, true);
1511
+
} else {
1512
+
/*
1513
+
* PM runtime is only enabled when a Slave reports as Attached
1514
+
*/
1515
+
1516
+
/* set autosuspend parameters */
1517
+
pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
1518
+
pm_runtime_use_autosuspend(&slave->dev);
1519
+
1520
+
/* update count of parent 'active' children */
1521
+
pm_runtime_set_active(&slave->dev);
1522
+
1523
+
/* make sure the device does not suspend immediately */
1524
+
pm_runtime_mark_last_busy(&slave->dev);
1525
+
1526
+
pm_runtime_enable(&slave->dev);
1527
+
}
1528
+
1529
+
pm_runtime_get_noresume(&slave->dev);
1530
+
1531
+
rt722_sdca_dmic_preset(rt722);
1532
+
rt722_sdca_amp_preset(rt722);
1533
+
rt722_sdca_jack_preset(rt722);
1534
+
1535
+
if (rt722->first_hw_init) {
1536
+
regcache_cache_bypass(rt722->regmap, false);
1537
+
regcache_mark_dirty(rt722->regmap);
1538
+
regcache_cache_bypass(rt722->mbq_regmap, false);
1539
+
regcache_mark_dirty(rt722->mbq_regmap);
1540
+
} else
1541
+
rt722->first_hw_init = true;
1542
+
1543
+
/* Mark Slave initialization complete */
1544
+
rt722->hw_init = true;
1545
+
1546
+
pm_runtime_mark_last_busy(&slave->dev);
1547
+
pm_runtime_put_autosuspend(&slave->dev);
1548
+
1549
+
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
1550
+
return 0;
1551
+
}
1552
+
1553
+
MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
1554
+
MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1555
+
MODULE_LICENSE("GPL");
+238
sound/soc/codecs/rt722-sdca.h
+238
sound/soc/codecs/rt722-sdca.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* rt722-sdca.h -- RT722 SDCA ALSA SoC audio driver header
4
+
*
5
+
* Copyright(c) 2023 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
#ifndef __RT722_H__
9
+
#define __RT722_H__
10
+
11
+
#include <linux/pm.h>
12
+
#include <linux/regmap.h>
13
+
#include <linux/soundwire/sdw.h>
14
+
#include <linux/soundwire/sdw_type.h>
15
+
#include <sound/soc.h>
16
+
#include <linux/workqueue.h>
17
+
18
+
struct rt722_sdca_priv {
19
+
struct regmap *regmap;
20
+
struct regmap *mbq_regmap;
21
+
struct snd_soc_component *component;
22
+
struct sdw_slave *slave;
23
+
enum sdw_slave_status status;
24
+
struct sdw_bus_params params;
25
+
bool hw_init;
26
+
bool first_hw_init;
27
+
struct mutex calibrate_mutex;
28
+
struct mutex disable_irq_lock;
29
+
bool disable_irq;
30
+
/* For Headset jack & Headphone */
31
+
unsigned int scp_sdca_stat1;
32
+
unsigned int scp_sdca_stat2;
33
+
struct snd_soc_jack *hs_jack;
34
+
struct delayed_work jack_detect_work;
35
+
struct delayed_work jack_btn_check_work;
36
+
int jack_type;
37
+
int jd_src;
38
+
bool fu0f_dapm_mute;
39
+
bool fu0f_mixer_l_mute;
40
+
bool fu0f_mixer_r_mute;
41
+
/* For DMIC */
42
+
bool fu1e_dapm_mute;
43
+
bool fu1e_mixer_mute[4];
44
+
};
45
+
46
+
struct rt722_sdca_dmic_kctrl_priv {
47
+
unsigned int reg_base;
48
+
unsigned int count;
49
+
unsigned int max;
50
+
unsigned int invert;
51
+
};
52
+
53
+
/* NID */
54
+
#define RT722_VENDOR_REG 0x20
55
+
#define RT722_VENDOR_CALI 0x58
56
+
#define RT722_VENDOR_SPK_EFUSE 0x5c
57
+
#define RT722_VENDOR_IMS_DRE 0x5b
58
+
#define RT722_VENDOR_ANALOG_CTL 0x5f
59
+
#define RT722_VENDOR_HDA_CTL 0x61
60
+
61
+
/* Index (NID:20h) */
62
+
#define RT722_JD_PRODUCT_NUM 0x00
63
+
#define RT722_ANALOG_BIAS_CTL3 0x04
64
+
#define RT722_JD_CTRL1 0x09
65
+
#define RT722_LDO2_3_CTL1 0x0e
66
+
#define RT722_LDO1_CTL 0x1a
67
+
#define RT722_HP_JD_CTRL 0x24
68
+
#define RT722_CLSD_CTRL6 0x3c
69
+
#define RT722_COMBO_JACK_AUTO_CTL1 0x45
70
+
#define RT722_COMBO_JACK_AUTO_CTL2 0x46
71
+
#define RT722_COMBO_JACK_AUTO_CTL3 0x47
72
+
#define RT722_DIGITAL_MISC_CTRL4 0x4a
73
+
#define RT722_FSM_CTL 0x67
74
+
#define RT722_SDCA_INTR_REC 0x82
75
+
#define RT722_SW_CONFIG1 0x8a
76
+
#define RT722_SW_CONFIG2 0x8b
77
+
78
+
/* Index (NID:58h) */
79
+
#define RT722_DAC_DC_CALI_CTL0 0x00
80
+
#define RT722_DAC_DC_CALI_CTL1 0x01
81
+
#define RT722_DAC_DC_CALI_CTL2 0x02
82
+
#define RT722_DAC_DC_CALI_CTL3 0x03
83
+
84
+
/* Index (NID:59h) */
85
+
#define RT722_ULTRA_SOUND_DETECTOR6 0x1e
86
+
87
+
/* Index (NID:5bh) */
88
+
#define RT722_IMS_DIGITAL_CTL1 0x00
89
+
#define RT722_IMS_DIGITAL_CTL5 0x05
90
+
#define RT722_HP_DETECT_RLDET_CTL1 0x29
91
+
#define RT722_HP_DETECT_RLDET_CTL2 0x2a
92
+
93
+
/* Index (NID:5fh) */
94
+
#define RT722_MISC_POWER_CTL0 0x00
95
+
#define RT722_MISC_POWER_CTL7 0x08
96
+
97
+
/* Index (NID:61h) */
98
+
#define RT722_HDA_LEGACY_MUX_CTL0 0x00
99
+
#define RT722_HDA_LEGACY_UNSOL_CTL 0x03
100
+
#define RT722_HDA_LEGACY_CONFIG_CTL0 0x06
101
+
#define RT722_HDA_LEGACY_RESET_CTL 0x08
102
+
#define RT722_HDA_LEGACY_GPIO_WAKE_EN_CTL 0x0e
103
+
#define RT722_DMIC_ENT_FLOAT_CTL 0x10
104
+
#define RT722_DMIC_GAIN_ENT_FLOAT_CTL0 0x11
105
+
#define RT722_DMIC_GAIN_ENT_FLOAT_CTL2 0x13
106
+
#define RT722_ADC_ENT_FLOAT_CTL 0x15
107
+
#define RT722_ADC_VOL_CH_FLOAT_CTL 0x17
108
+
#define RT722_ADC_SAMPLE_RATE_FLOAT 0x18
109
+
#define RT722_DAC03_HP_PDE_FLOAT_CTL 0x22
110
+
#define RT722_MIC2_LINE2_PDE_FLOAT_CTL 0x23
111
+
#define RT722_ET41_LINE2_PDE_FLOAT_CTL 0x24
112
+
#define RT722_ADC0A_08_PDE_FLOAT_CTL 0x25
113
+
#define RT722_ADC10_PDE_FLOAT_CTL 0x26
114
+
#define RT722_DMIC1_2_PDE_FLOAT_CTL 0x28
115
+
#define RT722_AMP_PDE_FLOAT_CTL 0x29
116
+
#define RT722_I2S_IN_OUT_PDE_FLOAT_CTL 0x2f
117
+
#define RT722_GE_RELATED_CTL1 0x45
118
+
#define RT722_GE_RELATED_CTL2 0x46
119
+
#define RT722_MIXER_CTL0 0x52
120
+
#define RT722_MIXER_CTL1 0x53
121
+
#define RT722_EAPD_CTL 0x55
122
+
#define RT722_UMP_HID_CTL0 0x60
123
+
#define RT722_UMP_HID_CTL1 0x61
124
+
#define RT722_UMP_HID_CTL2 0x62
125
+
#define RT722_UMP_HID_CTL3 0x63
126
+
#define RT722_UMP_HID_CTL4 0x64
127
+
#define RT722_UMP_HID_CTL5 0x65
128
+
#define RT722_UMP_HID_CTL6 0x66
129
+
#define RT722_UMP_HID_CTL7 0x67
130
+
#define RT722_UMP_HID_CTL8 0x68
131
+
132
+
/* Parameter & Verb control 01 (0x1a)(NID:20h) */
133
+
#define RT722_HIDDEN_REG_SW_RESET (0x1 << 14)
134
+
135
+
/* combo jack auto switch control 2 (0x46)(NID:20h) */
136
+
#define RT722_COMBOJACK_AUTO_DET_STATUS (0x1 << 11)
137
+
#define RT722_COMBOJACK_AUTO_DET_TRS (0x1 << 10)
138
+
#define RT722_COMBOJACK_AUTO_DET_CTIA (0x1 << 9)
139
+
#define RT722_COMBOJACK_AUTO_DET_OMTP (0x1 << 8)
140
+
141
+
/* DAC calibration control (0x00)(NID:58h) */
142
+
#define RT722_DC_CALIB_CTRL (0x1 << 16)
143
+
/* DAC DC offset calibration control-1 (0x01)(NID:58h) */
144
+
#define RT722_PDM_DC_CALIB_STATUS (0x1 << 15)
145
+
146
+
#define RT722_EAPD_HIGH 0x2
147
+
#define RT722_EAPD_LOW 0x0
148
+
149
+
/* Buffer address for HID */
150
+
#define RT722_BUF_ADDR_HID1 0x44030000
151
+
#define RT722_BUF_ADDR_HID2 0x44030020
152
+
153
+
/* RT722 SDCA Control - function number */
154
+
#define FUNC_NUM_JACK_CODEC 0x01
155
+
#define FUNC_NUM_MIC_ARRAY 0x02
156
+
#define FUNC_NUM_HID 0x03
157
+
#define FUNC_NUM_AMP 0x04
158
+
159
+
/* RT722 SDCA entity */
160
+
#define RT722_SDCA_ENT_HID01 0x01
161
+
#define RT722_SDCA_ENT_GE49 0x49
162
+
#define RT722_SDCA_ENT_USER_FU05 0x05
163
+
#define RT722_SDCA_ENT_USER_FU06 0x06
164
+
#define RT722_SDCA_ENT_USER_FU0F 0x0f
165
+
#define RT722_SDCA_ENT_USER_FU10 0x19
166
+
#define RT722_SDCA_ENT_USER_FU1E 0x1e
167
+
#define RT722_SDCA_ENT_FU15 0x15
168
+
#define RT722_SDCA_ENT_PDE23 0x23
169
+
#define RT722_SDCA_ENT_PDE40 0x40
170
+
#define RT722_SDCA_ENT_PDE11 0x11
171
+
#define RT722_SDCA_ENT_PDE12 0x12
172
+
#define RT722_SDCA_ENT_PDE2A 0x2a
173
+
#define RT722_SDCA_ENT_CS01 0x01
174
+
#define RT722_SDCA_ENT_CS11 0x11
175
+
#define RT722_SDCA_ENT_CS1F 0x1f
176
+
#define RT722_SDCA_ENT_CS1C 0x1c
177
+
#define RT722_SDCA_ENT_CS31 0x31
178
+
#define RT722_SDCA_ENT_OT23 0x42
179
+
#define RT722_SDCA_ENT_IT26 0x26
180
+
#define RT722_SDCA_ENT_IT09 0x09
181
+
#define RT722_SDCA_ENT_PLATFORM_FU15 0x15
182
+
#define RT722_SDCA_ENT_PLATFORM_FU44 0x44
183
+
#define RT722_SDCA_ENT_XU03 0x03
184
+
#define RT722_SDCA_ENT_XU0D 0x0d
185
+
186
+
/* RT722 SDCA control */
187
+
#define RT722_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10
188
+
#define RT722_SDCA_CTL_FU_MUTE 0x01
189
+
#define RT722_SDCA_CTL_FU_VOLUME 0x02
190
+
#define RT722_SDCA_CTL_HIDTX_CURRENT_OWNER 0x10
191
+
#define RT722_SDCA_CTL_HIDTX_SET_OWNER_TO_DEVICE 0x11
192
+
#define RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET 0x12
193
+
#define RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH 0x13
194
+
#define RT722_SDCA_CTL_SELECTED_MODE 0x01
195
+
#define RT722_SDCA_CTL_DETECTED_MODE 0x02
196
+
#define RT722_SDCA_CTL_REQ_POWER_STATE 0x01
197
+
#define RT722_SDCA_CTL_VENDOR_DEF 0x30
198
+
#define RT722_SDCA_CTL_FU_CH_GAIN 0x0b
199
+
200
+
/* RT722 SDCA channel */
201
+
#define CH_L 0x01
202
+
#define CH_R 0x02
203
+
#define CH_01 0x01
204
+
#define CH_02 0x02
205
+
#define CH_03 0x03
206
+
#define CH_04 0x04
207
+
#define CH_08 0x08
208
+
209
+
/* sample frequency index */
210
+
#define RT722_SDCA_RATE_16000HZ 0x04
211
+
#define RT722_SDCA_RATE_32000HZ 0x07
212
+
#define RT722_SDCA_RATE_44100HZ 0x08
213
+
#define RT722_SDCA_RATE_48000HZ 0x09
214
+
#define RT722_SDCA_RATE_96000HZ 0x0b
215
+
#define RT722_SDCA_RATE_192000HZ 0x0d
216
+
217
+
enum {
218
+
RT722_AIF1, /* For headset mic and headphone */
219
+
RT722_AIF2, /* For speaker */
220
+
RT722_AIF3, /* For dmic */
221
+
RT722_AIFS,
222
+
};
223
+
224
+
enum rt722_sdca_jd_src {
225
+
RT722_JD_NULL,
226
+
RT722_JD1,
227
+
};
228
+
229
+
int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave);
230
+
int rt722_sdca_init(struct device *dev, struct regmap *regmap,
231
+
struct regmap *mbq_regmap, struct sdw_slave *slave);
232
+
int rt722_sdca_index_write(struct rt722_sdca_priv *rt722,
233
+
unsigned int nid, unsigned int reg, unsigned int value);
234
+
int rt722_sdca_index_read(struct rt722_sdca_priv *rt722,
235
+
unsigned int nid, unsigned int reg, unsigned int *value);
236
+
237
+
int rt722_sdca_jack_detect(struct rt722_sdca_priv *rt722, bool *hp, bool *mic);
238
+
#endif /* __RT722_H__ */