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drm/amd/display: Fix MST recognizes connected displays as one

[What]
MST now recognizes both connected displays

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Muhammad Ahmed and committed by
Alex Deucher 7f7925e2 a6db1993

+20 -20
+17 -13
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
··· 1178 1178 dto_params.otg_inst = tg->inst; 1179 1179 dto_params.timing = &pipe_ctx->stream->timing; 1180 1180 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 1181 - dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1182 - dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 1183 - dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); 1184 - } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se) 1181 + if (dccg) { 1182 + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1183 + dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 1184 + dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); 1185 + } 1186 + } else if (dccg && dccg->funcs->disable_symclk_se) { 1185 1187 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, 1186 1188 link_enc->transmitter - TRANSMITTER_UNIPHY_A); 1189 + } 1187 1190 1188 1191 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1189 1192 /* TODO: This looks like a bug to me as we are disabling HPO IO when ··· 2658 2655 struct clk_mgr *dccg = dc->clk_mgr; 2659 2656 2660 2657 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2661 - 2662 - dccg->funcs->update_clocks( 2663 - dccg, 2664 - context, 2665 - false); 2658 + if (dccg) 2659 + dccg->funcs->update_clocks( 2660 + dccg, 2661 + context, 2662 + false); 2666 2663 } 2667 2664 2668 2665 void dce110_optimize_bandwidth( ··· 2673 2670 2674 2671 dce110_set_displaymarks(dc, context); 2675 2672 2676 - dccg->funcs->update_clocks( 2677 - dccg, 2678 - context, 2679 - true); 2673 + if (dccg) 2674 + dccg->funcs->update_clocks( 2675 + dccg, 2676 + context, 2677 + true); 2680 2678 } 2681 2679 2682 2680 static void dce110_program_front_end_for_pipe(
+2 -6
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
··· 2710 2710 struct dce_hwseq *hws = dc->hwseq; 2711 2711 unsigned int k1_div = PIXEL_RATE_DIV_NA; 2712 2712 unsigned int k2_div = PIXEL_RATE_DIV_NA; 2713 - struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 2714 - struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2715 2713 2716 2714 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2717 2715 if (dc->hwseq->funcs.setup_hpo_hw_control) ··· 2729 2731 dto_params.timing = &pipe_ctx->stream->timing; 2730 2732 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2731 2733 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2732 - } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se) 2733 - dccg->funcs->enable_symclk_se(dccg, 2734 - stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); 2735 - 2734 + } else { 2735 + } 2736 2736 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 2737 2737 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 2738 2738
+1 -1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
··· 75 75 if (power_on) { 76 76 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0); 77 77 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5); 78 - } else { 78 + } else if (!mpc->ctx->dc->debug.disable_mem_low_power) { 79 79 ASSERT(false); 80 80 /* TODO: change to mpc 81 81 * dpp_base->ctx->dc->optimized_required = true;