Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: fix some non-initialized register mask and setting
[why]
fix some non-initialized register mask and update golden setting
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Charlene Liu
and committed by
Alex Deucher
a6db1993
c06ef68a
+65
-18
+42
-14
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+42
-14
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
···
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#define mmCLK1_CLK3_DFS_CNTL 0x16E72
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#define mmCLK1_CLK4_DFS_CNTL 0x16E75
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+
#define mmCLK1_CLK0_CURRENT_CNT 0x16EE7
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#define mmCLK1_CLK1_CURRENT_CNT 0x16EE8
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#define mmCLK1_CLK2_CURRENT_CNT 0x16EE9
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#define mmCLK1_CLK3_CURRENT_CNT 0x16EEA
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#define mmCLK1_CLK4_CURRENT_CNT 0x16EEB
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+
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#define mmCLK4_CLK0_CURRENT_CNT 0x1B0C9
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+
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#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
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#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
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#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
···
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static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct clk_mgr_internal *clk_mgr)
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{
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unsigned int dispclk_khz_reg = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK
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unsigned int dppclk_khz_reg = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK
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unsigned int dprefclk_khz_reg = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK
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unsigned int dcfclk_khz_reg = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK
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unsigned int dtbclk_khz_reg = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK
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unsigned int fclk_khz_reg = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK
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+
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// Overrides for these clocks in case there is no p_state change support
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int dramclk_khz_override = new_clocks->dramclk_khz;
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int fclk_khz_override = new_clocks->fclk_khz;
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+
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int num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
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+
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if (!new_clocks->p_state_change_support) {
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dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
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+
}
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if (!new_clocks->fclk_p_state_change_support) {
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fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
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}
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+
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////////////////////////////////////////////////////////////////////////////
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// IMPORTANT: When adding more clocks to these logs, do NOT put a newline
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// anywhere other than at the very end of the string.
···
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new_clocks->dcfclk_khz > 0 &&
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new_clocks->dppclk_khz > 0) {
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-
if (new_clocks->p_state_change_support) {
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DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:%d - fclk_khz:%d - "
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"dcfclk_khz:%d - dppclk_khz:%d\n",
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new_clocks->dramclk_khz,
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new_clocks->fclk_khz,
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-
new_clocks->dcfclk_khz,
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-
new_clocks->dppclk_khz);
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-
} else {
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DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:1249000 - fclk_khz:%d - "
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"dcfclk_khz:%d - dppclk_khz:%d\n",
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new_clocks->fclk_khz,
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new_clocks->dcfclk_khz,
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new_clocks->dppclk_khz);
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-
}
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DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
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"dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
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"dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
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"dtbclk_hw:%d - fclk_hw:%d\n",
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dramclk_khz_override,
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fclk_khz_override,
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new_clocks->dcfclk_khz,
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new_clocks->dppclk_khz,
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dispclk_khz_reg,
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dppclk_khz_reg,
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dprefclk_khz_reg,
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dcfclk_khz_reg,
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dtbclk_khz_reg,
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fclk_khz_reg);
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}
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}
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+4
-1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+4
-1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
···
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type DIG_FIFO_READ_START_LEVEL;\
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type DIG_FIFO_ENABLE;\
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type DIG_FIFO_RESET;\
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-
type DIG_FIFO_RESET_DONE
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type DIG_FIFO_RESET_DONE;\
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type PIXEL_ENCODING_TYPE;\
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type UNCOMPRESSED_PIXEL_FORMAT;\
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type UNCOMPRESSED_COMPONENT_DEPTH
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#define SE_REG_FIELD_LIST_DCN3_5_COMMON(type) \
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type DIG_FE_CLK_EN;\
+4
-2
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+4
-2
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
···
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struct dcn3_clk_internal {
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int dummy;
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-
/*TODO:
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// TODO:
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uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
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uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
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uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
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uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
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uint32_t CLK1_CLK4_CURRENT_CNT;
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uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
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uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
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···
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uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
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uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
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uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
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-
*/
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+
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uint32_t CLK4_CLK0_CURRENT_CNT; //fclk
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};
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struct dcn301_clk_internal {
+15
-1
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+15
-1
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
···
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CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
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CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
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CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
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-
CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
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CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL), \
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CLK_SR_DCN32(CLK1_CLK0_CURRENT_CNT), \
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CLK_SR_DCN32(CLK1_CLK1_CURRENT_CNT), \
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CLK_SR_DCN32(CLK1_CLK2_CURRENT_CNT), \
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CLK_SR_DCN32(CLK1_CLK3_CURRENT_CNT), \
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CLK_SR_DCN32(CLK1_CLK4_CURRENT_CNT), \
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CLK_SR_DCN32(CLK4_CLK0_CURRENT_CNT)
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#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
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CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
···
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uint32_t CLK4_CLK2_CURRENT_CNT;
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uint32_t CLK4_CLK_PLL_REQ;
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+
uint32_t CLK4_CLK0_CURRENT_CNT;
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+
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uint32_t CLK3_CLK2_DFS_CNTL;
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uint32_t CLK3_CLK_PLL_REQ;
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···
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uint32_t CLK1_CLK2_DFS_CNTL;
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uint32_t CLK1_CLK3_DFS_CNTL;
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uint32_t CLK1_CLK4_DFS_CNTL;
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+
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uint32_t CLK1_CLK0_CURRENT_CNT;
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uint32_t CLK1_CLK1_CURRENT_CNT;
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+
uint32_t CLK1_CLK2_CURRENT_CNT;
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+
uint32_t CLK1_CLK3_CURRENT_CNT;
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uint32_t CLK1_CLK4_CURRENT_CNT;
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uint32_t CLK0_CLK0_DFS_CNTL;
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uint32_t CLK0_CLK1_DFS_CNTL;