Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Yoshihiro Shimoda
and committed by
Geert Uytterhoeven
7f906eaa
5d33481f
+24
-16
+6
-6
drivers/clk/renesas/r8a779a0-cpg-mssr.c
+6
-6
drivers/clk/renesas/r8a779a0-cpg-mssr.c
···
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/*
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* MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
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* 14 13 (MHz) 21 31
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-
* --------------------------------------------------------
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+
* ----------------------------------------------------------------
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* 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
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* 0 1 20 x 1 x106 x180 x106 x120 x160 /19
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* 1 0 Prohibited setting
···
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
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(((md) & BIT(13)) >> 13))
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static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
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/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
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{ 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, },
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{ 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
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{ 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, },
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/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
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{ 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
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{ 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
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{ 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
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};
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+10
-10
drivers/clk/renesas/r8a779f0-cpg-mssr.c
+10
-10
drivers/clk/renesas/r8a779f0-cpg-mssr.c
···
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC
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* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
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* 14 13 (MHz)
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-
* ----------------------------------------------------------------
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* 0 0 16 / 1 x200 x150 x200 x200 x134 /15
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* 0 1 20 / 1 x160 x120 x160 x160 x106 /19
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* ------------------------------------------------------------------------
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* 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15
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* 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19
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* 1 0 Prohibited setting
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* 1 1 40 / 2 x160 x120 x160 x160 x106 /38
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* 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
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(((md) & BIT(13)) >> 13))
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static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
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/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
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{ 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, },
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{ 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
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{ 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, },
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/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
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{ 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, },
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{ 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
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{ 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, },
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};
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static int __init r8a779f0_cpg_mssr_init(struct device *dev)
+5
drivers/clk/renesas/rcar-gen4-cpg.c
+5
drivers/clk/renesas/rcar-gen4-cpg.c
···
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div = cpg_pll_config->pll3_div;
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break;
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+
case CLK_TYPE_GEN4_PLL4:
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mult = cpg_pll_config->pll4_mult;
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div = cpg_pll_config->pll4_div;
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break;
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+
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case CLK_TYPE_GEN4_PLL5:
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mult = cpg_pll_config->pll5_mult;
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div = cpg_pll_config->pll5_div;
+3
drivers/clk/renesas/rcar-gen4-cpg.h
+3
drivers/clk/renesas/rcar-gen4-cpg.h
···
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CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
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CLK_TYPE_GEN4_PLL3,
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CLK_TYPE_GEN4_PLL5,
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CLK_TYPE_GEN4_PLL4,
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CLK_TYPE_GEN4_PLL6,
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CLK_TYPE_GEN4_SDSRC,
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CLK_TYPE_GEN4_SDH,
···
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u8 pll2_div;
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u8 pll3_mult;
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u8 pll3_div;
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u8 pll4_mult;
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u8 pll4_div;
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u8 pll5_mult;
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u8 pll5_div;
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u8 pll6_mult;