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sparc: move the XOR code to lib/raid/

Move the optimized XOR into lib/raid and include it it in xor.ko instead
of always building it into the main kernel image.

The code should probably be split into separate files for the two
implementations, but for now this just does the trivial move.

Link: https://lkml.kernel.org/r/20260327061704.3707577-18-hch@lst.de
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Eric Biggers <ebiggers@kernel.org>
Tested-by: Eric Biggers <ebiggers@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Gordeev <agordeev@linux.ibm.com>
Cc: Alexandre Ghiti <alex@ghiti.fr>
Cc: Andreas Larsson <andreas@gaisler.com>
Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Borislav Petkov (AMD)" <bp@alien8.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Mason <clm@fb.com>
Cc: Christian Borntraeger <borntraeger@linux.ibm.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: David Sterba <dsterba@suse.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Huacai Chen <chenhuacai@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jason A. Donenfeld <jason@zx2c4.com>
Cc: Johannes Berg <johannes@sipsolutions.net>
Cc: Li Nan <linan122@huawei.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Magnus Lindholm <linmag7@gmail.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Richard Weinberger <richard@nod.at>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Song Liu <song@kernel.org>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Ted Ts'o <tytso@mit.edu>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Cc: WANG Xuerui <kernel@xen0n.name>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>

authored by

Christoph Hellwig and committed by
Andrew Morton 7f963623 5265d55b

+52 -57
-1
arch/sparc/include/asm/asm-prototypes.h
··· 14 14 #include <asm/oplib.h> 15 15 #include <asm/pgtable.h> 16 16 #include <asm/trap_block.h> 17 - #include <asm/xor.h> 18 17 19 18 void *__memscan_zero(void *, size_t); 20 19 void *__memscan_generic(void *, int, size_t);
+40 -5
arch/sparc/include/asm/xor.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz) 4 + * Copyright (C) 2006 David S. Miller <davem@davemloft.net> 5 + */ 2 6 #ifndef ___ASM_SPARC_XOR_H 3 7 #define ___ASM_SPARC_XOR_H 8 + 4 9 #if defined(__sparc__) && defined(__arch64__) 5 - #include <asm/xor_64.h> 6 - #else 7 - #include <asm/xor_32.h> 8 - #endif 9 - #endif 10 + #include <asm/spitfire.h> 11 + 12 + extern struct xor_block_template xor_block_VIS; 13 + extern struct xor_block_template xor_block_niagara; 14 + 15 + #define arch_xor_init arch_xor_init 16 + static __always_inline void __init arch_xor_init(void) 17 + { 18 + /* Force VIS for everything except Niagara. */ 19 + if (tlb_type == hypervisor && 20 + (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || 21 + sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 22 + sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 23 + sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 24 + sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) 25 + xor_force(&xor_block_niagara); 26 + else 27 + xor_force(&xor_block_VIS); 28 + } 29 + #else /* sparc64 */ 30 + 31 + /* For grins, also test the generic routines. */ 32 + #include <asm-generic/xor.h> 33 + 34 + extern struct xor_block_template xor_block_SPARC; 35 + 36 + #define arch_xor_init arch_xor_init 37 + static __always_inline void __init arch_xor_init(void) 38 + { 39 + xor_register(&xor_block_8regs); 40 + xor_register(&xor_block_32regs); 41 + xor_register(&xor_block_SPARC); 42 + } 43 + #endif /* !sparc64 */ 44 + #endif /* ___ASM_SPARC_XOR_H */
+4 -19
arch/sparc/include/asm/xor_32.h lib/raid/xor/sparc/xor-sparc32.c
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * include/asm/xor.h 4 - * 5 - * Optimized RAID-5 checksumming functions for 32-bit Sparc. 6 - */ 7 - 1 + // SPDX-License-Identifier: GPL-2.0-or-later 8 2 /* 9 3 * High speed xor_block operation for RAID4/5 utilizing the 10 4 * ldd/std SPARC instructions. 11 5 * 12 6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 13 7 */ 8 + #include <linux/raid/xor_impl.h> 9 + #include <asm/xor.h> 14 10 15 11 static void 16 12 sparc_2(unsigned long bytes, unsigned long * __restrict p1, ··· 244 248 } while (--lines > 0); 245 249 } 246 250 247 - static struct xor_block_template xor_block_SPARC = { 251 + struct xor_block_template xor_block_SPARC = { 248 252 .name = "SPARC", 249 253 .do_2 = sparc_2, 250 254 .do_3 = sparc_3, 251 255 .do_4 = sparc_4, 252 256 .do_5 = sparc_5, 253 257 }; 254 - 255 - /* For grins, also test the generic routines. */ 256 - #include <asm-generic/xor.h> 257 - 258 - #define arch_xor_init arch_xor_init 259 - static __always_inline void __init arch_xor_init(void) 260 - { 261 - xor_register(&xor_block_8regs); 262 - xor_register(&xor_block_32regs); 263 - xor_register(&xor_block_SPARC); 264 - }
+5 -21
arch/sparc/include/asm/xor_64.h lib/raid/xor/sparc/xor-sparc64-glue.c
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 2 /* 3 - * include/asm/xor.h 4 - * 5 3 * High speed xor_block operation for RAID4/5 utilizing the 6 4 * UltraSparc Visual Instruction Set and Niagara block-init 7 5 * twin-load instructions. ··· 8 10 * Copyright (C) 2006 David S. Miller <davem@davemloft.net> 9 11 */ 10 12 11 - #include <asm/spitfire.h> 13 + #include <linux/raid/xor_impl.h> 14 + #include <asm/xor.h> 12 15 13 16 void xor_vis_2(unsigned long bytes, unsigned long * __restrict p1, 14 17 const unsigned long * __restrict p2); ··· 28 29 29 30 /* XXX Ugh, write cheetah versions... -DaveM */ 30 31 31 - static struct xor_block_template xor_block_VIS = { 32 + struct xor_block_template xor_block_VIS = { 32 33 .name = "VIS", 33 34 .do_2 = xor_vis_2, 34 35 .do_3 = xor_vis_3, ··· 51 52 const unsigned long * __restrict p4, 52 53 const unsigned long * __restrict p5); 53 54 54 - static struct xor_block_template xor_block_niagara = { 55 + struct xor_block_template xor_block_niagara = { 55 56 .name = "Niagara", 56 57 .do_2 = xor_niagara_2, 57 58 .do_3 = xor_niagara_3, 58 59 .do_4 = xor_niagara_4, 59 60 .do_5 = xor_niagara_5, 60 61 }; 61 - 62 - #define arch_xor_init arch_xor_init 63 - static __always_inline void __init arch_xor_init(void) 64 - { 65 - /* Force VIS for everything except Niagara. */ 66 - if (tlb_type == hypervisor && 67 - (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || 68 - sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 69 - sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 70 - sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 71 - sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) 72 - xor_force(&xor_block_niagara); 73 - else 74 - xor_force(&xor_block_VIS); 75 - }
+1 -1
arch/sparc/lib/Makefile
··· 48 48 lib-$(CONFIG_SPARC64) += GENpatch.o GENpage.o GENbzero.o 49 49 50 50 lib-$(CONFIG_SPARC64) += copy_in_user.o memmove.o 51 - lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o hweight.o ffs.o 51 + lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o hweight.o ffs.o 52 52 53 53 obj-$(CONFIG_SPARC64) += iomap.o 54 54 obj-$(CONFIG_SPARC32) += atomic32.o
-10
arch/sparc/lib/xor.S lib/raid/xor/sparc/xor-sparc64.S
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 2 /* 3 - * arch/sparc64/lib/xor.S 4 - * 5 3 * High speed xor_block operation for RAID4/5 utilizing the 6 4 * UltraSparc Visual Instruction Set and Niagara store-init/twin-load. 7 5 * ··· 90 92 retl 91 93 wr %g0, 0, %fprs 92 94 ENDPROC(xor_vis_2) 93 - EXPORT_SYMBOL(xor_vis_2) 94 95 95 96 ENTRY(xor_vis_3) 96 97 rd %fprs, %o5 ··· 156 159 retl 157 160 wr %g0, 0, %fprs 158 161 ENDPROC(xor_vis_3) 159 - EXPORT_SYMBOL(xor_vis_3) 160 162 161 163 ENTRY(xor_vis_4) 162 164 rd %fprs, %o5 ··· 241 245 retl 242 246 wr %g0, 0, %fprs 243 247 ENDPROC(xor_vis_4) 244 - EXPORT_SYMBOL(xor_vis_4) 245 248 246 249 ENTRY(xor_vis_5) 247 250 save %sp, -192, %sp ··· 347 352 ret 348 353 restore 349 354 ENDPROC(xor_vis_5) 350 - EXPORT_SYMBOL(xor_vis_5) 351 355 352 356 /* Niagara versions. */ 353 357 ENTRY(xor_niagara_2) /* %o0=bytes, %o1=dest, %o2=src */ ··· 393 399 ret 394 400 restore 395 401 ENDPROC(xor_niagara_2) 396 - EXPORT_SYMBOL(xor_niagara_2) 397 402 398 403 ENTRY(xor_niagara_3) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2 */ 399 404 save %sp, -192, %sp ··· 454 461 ret 455 462 restore 456 463 ENDPROC(xor_niagara_3) 457 - EXPORT_SYMBOL(xor_niagara_3) 458 464 459 465 ENTRY(xor_niagara_4) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3 */ 460 466 save %sp, -192, %sp ··· 536 544 ret 537 545 restore 538 546 ENDPROC(xor_niagara_4) 539 - EXPORT_SYMBOL(xor_niagara_4) 540 547 541 548 ENTRY(xor_niagara_5) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3, %o5=src4 */ 542 549 save %sp, -192, %sp ··· 634 643 ret 635 644 restore 636 645 ENDPROC(xor_niagara_5) 637 - EXPORT_SYMBOL(xor_niagara_5)
+2
lib/raid/xor/Makefile
··· 18 18 xor-$(CONFIG_CPU_HAS_LSX) += loongarch/xor_simd_glue.o 19 19 xor-$(CONFIG_ALTIVEC) += powerpc/xor_vmx.o powerpc/xor_vmx_glue.o 20 20 xor-$(CONFIG_RISCV_ISA_V) += riscv/xor.o riscv/xor-glue.o 21 + xor-$(CONFIG_SPARC32) += sparc/xor-sparc32.o 22 + xor-$(CONFIG_SPARC64) += sparc/xor-sparc64.o sparc/xor-sparc64-glue.o 21 23 22 24 23 25 CFLAGS_arm/xor-neon.o += $(CC_FLAGS_FPU)