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mfd: tps65219: Add support for TI TPS65215 PMIC

Use chip ID and chip_data struct to differentiate between devices in
probe(). Add TPS65215 resource information. Update descriptions and
copyright information to reflect the driver supports 2 PMIC devices.

Signed-off-by: Shree Ramamoorthy <s-ramamoorthy@ti.com>
Link: https://lore.kernel.org/r/20250206173725.386720-5-s-ramamoorthy@ti.com
Signed-off-by: Lee Jones <lee@kernel.org>

authored by

Shree Ramamoorthy and committed by
Lee Jones 7f9ed27e 76b58d51

+209 -12
+144 -6
drivers/mfd/tps65219.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 // 3 - // Driver for TPS65219 Integrated Power Management Integrated Chips (PMIC) 3 + // Driver for TPS65215/TPS65219 Power Management Integrated Chips (PMIC) 4 4 // 5 5 // Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ 6 + // Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 6 7 7 8 #include <linux/i2c.h> 8 9 #include <linux/reboot.h> ··· 60 59 DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"), 61 60 }; 62 61 62 + static const struct resource tps65215_regulator_resources[] = { 63 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_SCG, "LDO1_SCG"), 64 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_OC, "LDO1_OC"), 65 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_UV, "LDO1_UV"), 66 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_SCG, "LDO2_SCG"), 67 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_OC, "LDO2_OC"), 68 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_UV, "LDO2_UV"), 69 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"), 70 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"), 71 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"), 72 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"), 73 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"), 74 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"), 75 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"), 76 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"), 77 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"), 78 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"), 79 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"), 80 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"), 81 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"), 82 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"), 83 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"), 84 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"), 85 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_RV, "LDO2_RV"), 86 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"), 87 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"), 88 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"), 89 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV_SD, "LDO1_RV_SD"), 90 + DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_RV_SD, "LDO2_RV_SD"), 91 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"), 92 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_WARM, "SENSOR_3_WARM"), 93 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"), 94 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"), 95 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"), 96 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_HOT, "SENSOR_3_HOT"), 97 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"), 98 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"), 99 + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"), 100 + }; 101 + 63 102 static const struct resource tps65219_regulator_resources[] = { 64 103 DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_SCG, "LDO3_SCG"), 65 104 DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_OC, "LDO3_OC"), ··· 150 109 DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"), 151 110 }; 152 111 112 + static const struct mfd_cell tps65215_cells[] = { 113 + MFD_CELL_RES("tps65215-regulator", tps65215_regulator_resources), 114 + MFD_CELL_NAME("tps65215-gpio"), 115 + }; 116 + 153 117 static const struct mfd_cell tps65219_cells[] = { 154 118 MFD_CELL_RES("tps65219-regulator", tps65219_regulator_resources), 155 119 MFD_CELL_NAME("tps65219-gpio"), ··· 182 136 static unsigned int bit4_offsets[] = { TPS65219_REG_INT_BUCK_3_POS }; /* Buck 3 */ 183 137 static unsigned int bit5_offsets[] = { TPS65219_REG_INT_LDO_1_2_POS }; /* LDO 1-2 */ 184 138 static unsigned int bit6_offsets[] = { TPS65219_REG_INT_LDO_3_4_POS }; /* LDO 3-4 */ 139 + static unsigned int tps65215_bit5_offsets[] = { TPS65215_REG_INT_LDO_1_POS }; 140 + static unsigned int tps65215_bit6_offsets[] = { TPS65215_REG_INT_LDO_2_POS }; 185 141 static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS }; /* Power Button */ 186 142 187 143 static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = { ··· 197 149 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 198 150 }; 199 151 152 + static struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = { 153 + REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 154 + REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 155 + REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 156 + REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 157 + REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 158 + REGMAP_IRQ_MAIN_REG_OFFSET(tps65215_bit5_offsets), 159 + REGMAP_IRQ_MAIN_REG_OFFSET(tps65215_bit6_offsets), 160 + REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 161 + }; 162 + 200 163 #define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \ 201 164 REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK) 165 + 166 + static const struct regmap_irq tps65215_irqs[] = { 167 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_SCG, TPS65215_REG_INT_LDO_1_POS), 168 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_OC, TPS65215_REG_INT_LDO_1_POS), 169 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_UV, TPS65215_REG_INT_LDO_1_POS), 170 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_SCG, TPS65215_REG_INT_LDO_2_POS), 171 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_OC, TPS65215_REG_INT_LDO_2_POS), 172 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_UV, TPS65215_REG_INT_LDO_2_POS), 173 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65219_REG_INT_BUCK_3_POS), 174 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65219_REG_INT_BUCK_3_POS), 175 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65219_REG_INT_BUCK_3_POS), 176 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65219_REG_INT_BUCK_3_POS), 177 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65219_REG_INT_BUCK_1_2_POS), 178 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65219_REG_INT_BUCK_1_2_POS), 179 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS), 180 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65219_REG_INT_BUCK_1_2_POS), 181 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65219_REG_INT_BUCK_1_2_POS), 182 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65219_REG_INT_BUCK_1_2_POS), 183 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS), 184 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65219_REG_INT_BUCK_1_2_POS), 185 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_WARM, TPS65219_REG_INT_SYS_POS), 186 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65219_REG_INT_SYS_POS), 187 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65219_REG_INT_SYS_POS), 188 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65219_REG_INT_SYS_POS), 189 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_HOT, TPS65219_REG_INT_SYS_POS), 190 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65219_REG_INT_SYS_POS), 191 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65219_REG_INT_SYS_POS), 192 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65219_REG_INT_SYS_POS), 193 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65219_REG_INT_RV_POS), 194 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65219_REG_INT_RV_POS), 195 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65219_REG_INT_RV_POS), 196 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65219_REG_INT_RV_POS), 197 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_RV, TPS65219_REG_INT_RV_POS), 198 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65219_REG_INT_TO_RV_POS), 199 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65219_REG_INT_TO_RV_POS), 200 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65219_REG_INT_TO_RV_POS), 201 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV_SD, TPS65219_REG_INT_TO_RV_POS), 202 + TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_RV_SD, TPS65219_REG_INT_TO_RV_POS), 203 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65219_REG_INT_TO_RV_POS), 204 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65219_REG_INT_PB_POS), 205 + TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS), 206 + }; 202 207 203 208 static const struct regmap_irq tps65219_irqs[] = { 204 209 TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_SCG, TPS65219_REG_INT_LDO_3_4_POS), ··· 305 204 TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS), 306 205 }; 307 206 207 + static const struct regmap_irq_chip tps65215_irq_chip = { 208 + .name = "tps65215_irq", 209 + .main_status = TPS65219_REG_INT_SOURCE, 210 + .num_main_regs = 1, 211 + .num_main_status_bits = 8, 212 + .irqs = tps65215_irqs, 213 + .num_irqs = ARRAY_SIZE(tps65215_irqs), 214 + .status_base = TPS65215_REG_INT_LDO_2, 215 + .ack_base = TPS65215_REG_INT_LDO_2, 216 + .clear_ack = 1, 217 + .num_regs = 8, 218 + .sub_reg_offsets = tps65215_sub_irq_offsets, 219 + }; 220 + 308 221 static const struct regmap_irq_chip tps65219_irq_chip = { 309 222 .name = "tps65219_irq", 310 223 .main_status = TPS65219_REG_INT_SOURCE, ··· 333 218 .sub_reg_offsets = tps65219_sub_irq_offsets, 334 219 }; 335 220 221 + struct tps65219_chip_data { 222 + const struct regmap_irq_chip *irq_chip; 223 + const struct mfd_cell *cells; 224 + int n_cells; 225 + }; 226 + 227 + static struct tps65219_chip_data chip_info_table[] = { 228 + [TPS65215] = { 229 + .irq_chip = &tps65215_irq_chip, 230 + .cells = tps65215_cells, 231 + .n_cells = ARRAY_SIZE(tps65215_cells), 232 + }, 233 + [TPS65219] = { 234 + .irq_chip = &tps65219_irq_chip, 235 + .cells = tps65219_cells, 236 + .n_cells = ARRAY_SIZE(tps65219_cells), 237 + }, 238 + }; 239 + 336 240 static int tps65219_probe(struct i2c_client *client) 337 241 { 338 242 struct tps65219 *tps; 243 + struct tps65219_chip_data *pmic; 339 244 bool pwr_button; 340 245 int ret; 341 246 ··· 366 231 i2c_set_clientdata(client, tps); 367 232 368 233 tps->dev = &client->dev; 234 + tps->chip_id = (uintptr_t)i2c_get_match_data(client); 235 + pmic = &chip_info_table[tps->chip_id]; 369 236 370 237 tps->regmap = devm_regmap_init_i2c(client, &tps65219_regmap_config); 371 238 if (IS_ERR(tps->regmap)) { ··· 376 239 return ret; 377 240 } 378 241 379 - ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, client->irq, 380 - IRQF_ONESHOT, 0, &tps65219_irq_chip, 242 + ret = devm_regmap_add_irq_chip(tps->dev, tps->regmap, client->irq, 243 + IRQF_ONESHOT, 0, pmic->irq_chip, 381 244 &tps->irq_data); 382 245 if (ret) 383 246 return ret; 384 247 385 248 ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, 386 - tps65219_cells, ARRAY_SIZE(tps65219_cells), 249 + pmic->cells, pmic->n_cells, 387 250 NULL, 0, regmap_irq_get_domain(tps->irq_data)); 388 251 if (ret) { 389 252 dev_err(tps->dev, "Failed to add child devices: %d\n", ret); ··· 421 284 } 422 285 423 286 static const struct of_device_id of_tps65219_match_table[] = { 424 - { .compatible = "ti,tps65219", }, 287 + { .compatible = "ti,tps65215", .data = (void *)TPS65215, }, 288 + { .compatible = "ti,tps65219", .data = (void *)TPS65219, }, 425 289 {} 426 290 }; 427 291 MODULE_DEVICE_TABLE(of, of_tps65219_match_table); ··· 437 299 module_i2c_driver(tps65219_driver); 438 300 439 301 MODULE_AUTHOR("Jerome Neanne <jneanne@baylibre.com>"); 440 - MODULE_DESCRIPTION("TPS65219 power management IC driver"); 302 + MODULE_DESCRIPTION("TPS65215/TPS65219 PMIC driver"); 441 303 MODULE_LICENSE("GPL");
+65 -6
include/linux/mfd/tps65219.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 2 /* 3 - * Functions to access TPS65219 Power Management IC. 3 + * Functions to access TPS65215/TPS65219 Power Management Integrated Chips 4 4 * 5 5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ 6 + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 6 7 */ 7 8 8 9 #ifndef MFD_TPS65219_H ··· 14 13 #include <linux/regmap.h> 15 14 #include <linux/regulator/driver.h> 16 15 17 - /* TPS chip id list */ 18 - #define TPS65219 0xF0 16 + /* Chip id list*/ 17 + enum pmic_id { 18 + TPS65215, 19 + TPS65219, 20 + }; 19 21 20 22 /* I2C ID for TPS65219 part */ 21 23 #define TPS65219_I2C_ID 0x24 ··· 30 26 #define TPS65219_REG_BUCKS_CONFIG 0x03 31 27 #define TPS65219_REG_LDO4_VOUT 0x04 32 28 #define TPS65219_REG_LDO3_VOUT 0x05 29 + #define TPS65215_REG_LDO2_VOUT 0x05 33 30 #define TPS65219_REG_LDO2_VOUT 0x06 34 31 #define TPS65219_REG_LDO1_VOUT 0x07 35 32 #define TPS65219_REG_BUCK3_VOUT 0x8 ··· 38 33 #define TPS65219_REG_BUCK1_VOUT 0xA 39 34 #define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB 40 35 #define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC 36 + #define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC 41 37 #define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD 42 38 #define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE 43 39 #define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF ··· 73 67 #define TPS65219_REG_DISCHARGE_CONFIG 0x2A 74 68 /* main irq registers */ 75 69 #define TPS65219_REG_INT_SOURCE 0x2B 76 - /* 'sub irq' registers */ 70 + 71 + /* TPS65219 'sub irq' registers */ 77 72 #define TPS65219_REG_INT_LDO_3_4 0x2C 78 73 #define TPS65219_REG_INT_LDO_1_2 0x2D 74 + 75 + /* TPS65215 specific 'sub irq' registers */ 76 + #define TPS65215_REG_INT_LDO_2 0x2C 77 + #define TPS65215_REG_INT_LDO_1 0x2D 78 + 79 + /* Common TPS65215 & TPS65219 'sub irq' registers */ 79 80 #define TPS65219_REG_INT_BUCK_3 0x2E 80 81 #define TPS65219_REG_INT_BUCK_1_2 0x2F 81 82 #define TPS65219_REG_INT_SYSTEM 0x30 ··· 98 85 #define TPS65219_REG_INT_RV_POS 5 99 86 #define TPS65219_REG_INT_TO_RV_POS 6 100 87 #define TPS65219_REG_INT_PB_POS 7 88 + 89 + #define TPS65215_REG_INT_LDO_2_POS 0 90 + #define TPS65215_REG_INT_LDO_1_POS 1 101 91 102 92 #define TPS65219_REG_USER_NVM_CMD 0x34 103 93 #define TPS65219_REG_POWER_UP_STATUS 0x35 ··· 123 107 #define TPS65219_ENABLE_LDO1_EN_MASK BIT(3) 124 108 #define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) 125 109 #define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) 110 + #define TPS65215_ENABLE_LDO2_EN_MASK BIT(5) 126 111 #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) 127 112 /* power ON-OFF sequence slot */ 128 113 #define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) ··· 189 172 #define TPS65219_INT_LDO2_SCG_MASK BIT(3) 190 173 #define TPS65219_INT_LDO2_OC_MASK BIT(4) 191 174 #define TPS65219_INT_LDO2_UV_MASK BIT(5) 175 + /* TPS65215 LDO1-2*/ 176 + #define TPS65215_INT_LDO1_SCG_MASK BIT(0) 177 + #define TPS65215_INT_LDO1_OC_MASK BIT(1) 178 + #define TPS65215_INT_LDO1_UV_MASK BIT(2) 179 + #define TPS65215_INT_LDO2_SCG_MASK BIT(0) 180 + #define TPS65215_INT_LDO2_OC_MASK BIT(1) 181 + #define TPS65215_INT_LDO2_UV_MASK BIT(2) 192 182 /* BUCK3 */ 193 183 #define TPS65219_INT_BUCK3_SCG_MASK BIT(0) 194 184 #define TPS65219_INT_BUCK3_OC_MASK BIT(1) ··· 226 202 #define TPS65219_INT_LDO1_RV_MASK BIT(3) 227 203 #define TPS65219_INT_LDO2_RV_MASK BIT(4) 228 204 #define TPS65219_INT_LDO3_RV_MASK BIT(5) 205 + #define TPS65215_INT_LDO2_RV_MASK BIT(5) 229 206 #define TPS65219_INT_LDO4_RV_MASK BIT(6) 230 207 /* Residual Voltage ShutDown */ 231 208 #define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) ··· 235 210 #define TPS65219_INT_LDO1_RV_SD_MASK BIT(3) 236 211 #define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) 237 212 #define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) 213 + #define TPS65215_INT_LDO2_RV_SD_MASK BIT(5) 238 214 #define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) 239 215 #define TPS65219_INT_TIMEOUT_MASK BIT(7) 240 216 /* Power Button */ ··· 261 235 TPS65219_INT_LDO4_SCG, 262 236 TPS65219_INT_LDO4_OC, 263 237 TPS65219_INT_LDO4_UV, 238 + /* TPS65215 LDO1*/ 239 + TPS65215_INT_LDO1_SCG, 240 + TPS65215_INT_LDO1_OC, 241 + TPS65215_INT_LDO1_UV, 242 + /* TPS65215 LDO2*/ 243 + TPS65215_INT_LDO2_SCG, 244 + TPS65215_INT_LDO2_OC, 245 + TPS65215_INT_LDO2_UV, 264 246 /* LDO1-2 */ 265 247 TPS65219_INT_LDO1_SCG, 266 248 TPS65219_INT_LDO1_OC, ··· 305 271 TPS65219_INT_BUCK3_RV, 306 272 TPS65219_INT_LDO1_RV, 307 273 TPS65219_INT_LDO2_RV, 274 + TPS65215_INT_LDO2_RV, 308 275 TPS65219_INT_LDO3_RV, 309 276 TPS65219_INT_LDO4_RV, 310 277 /* Residual Voltage ShutDown */ ··· 313 278 TPS65219_INT_BUCK2_RV_SD, 314 279 TPS65219_INT_BUCK3_RV_SD, 315 280 TPS65219_INT_LDO1_RV_SD, 281 + TPS65215_INT_LDO2_RV_SD, 316 282 TPS65219_INT_LDO2_RV_SD, 317 283 TPS65219_INT_LDO3_RV_SD, 318 284 TPS65219_INT_LDO4_RV_SD, ··· 321 285 /* Power Button */ 322 286 TPS65219_INT_PB_FALLING_EDGE_DETECT, 323 287 TPS65219_INT_PB_RISING_EDGE_DETECT, 288 + }; 289 + 290 + enum tps65215_regulator_id { 291 + /* DCDC's same as TPS65219 */ 292 + /* LDO1 is the same as TPS65219 */ 293 + TPS65215_LDO_2 = 4, 324 294 }; 325 295 326 296 enum tps65219_regulator_id { ··· 342 300 }; 343 301 344 302 /* Number of step-down converters available */ 345 - #define TPS65219_NUM_DCDC 3 303 + #define TPS6521X_NUM_BUCKS 3 346 304 /* Number of LDO voltage regulators available */ 347 305 #define TPS65219_NUM_LDO 4 306 + #define TPS65215_NUM_LDO 2 348 307 /* Number of total regulators available */ 349 - #define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO) 308 + #define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO) 309 + #define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO) 310 + 311 + /* Define the TPS65215 IRQ numbers */ 312 + enum tps65215_irqs { 313 + /* INT source registers */ 314 + TPS65215_TO_RV_SD_SET_IRQ, 315 + TPS65215_RV_SET_IRQ, 316 + TPS65215_SYS_SET_IRQ, 317 + TPS65215_BUCK_1_2_SET_IRQ, 318 + TPS65215_BUCK_3_SET_IRQ, 319 + TPS65215_LDO_1_SET_IRQ, 320 + TPS65215_LDO_2_SET_IRQ, 321 + TPS65215_PB_SET_IRQ, 322 + }; 350 323 351 324 /* Define the TPS65219 IRQ numbers */ 352 325 enum tps65219_irqs { ··· 383 326 * 384 327 * @dev: MFD device 385 328 * @regmap: Regmap for accessing the device registers 329 + * @chip_id: Chip ID 386 330 * @irq_data: Regmap irq data used for the irq chip 387 331 * @nb: notifier block for the restart handler 388 332 */ ··· 391 333 struct device *dev; 392 334 struct regmap *regmap; 393 335 336 + unsigned int chip_id; 394 337 struct regmap_irq_chip_data *irq_data; 395 338 struct notifier_block nb; 396 339 };