Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 6994/1: smp_twd: Fix typo in 'twd_timer_rate' printing
ARM: 6987/1: l2x0: fix disabling function to avoid deadlock
ARM: 6966/1: ep93xx: fix inverted RTS/DTR signals on uart1
ARM: 6980/1: mmci: use StartBitErr to detect bad connections
ARM: 6979/1: mach-vt8500: add forgotten irq_data conversion
ARM: move memory layout sanity checking before meminfo initialization
ARM: 6990/1: MAINTAINERS: add entry for ARM PMU profiling and debugging
ARM: 6989/1: perf: do not start the PMU when no events are present
ARM: dmabounce: fix map_single() error return value
+58
-24
+10
MAINTAINERS
+10
MAINTAINERS
···
594
594
F: arch/arm/lib/floppydma.S
595
595
F: arch/arm/include/asm/floppy.h
596
596
597
+
ARM PMU PROFILING AND DEBUGGING
598
+
M: Will Deacon <will.deacon@arm.com>
599
+
S: Maintained
600
+
F: arch/arm/kernel/perf_event*
601
+
F: arch/arm/oprofile/common.c
602
+
F: arch/arm/kernel/pmu.c
603
+
F: arch/arm/include/asm/pmu.h
604
+
F: arch/arm/kernel/hw_breakpoint.c
605
+
F: arch/arm/include/asm/hw_breakpoint.h
606
+
597
607
ARM PORT
598
608
M: Russell King <linux@arm.linux.org.uk>
599
609
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+1
-1
arch/arm/common/dmabounce.c
+1
-1
arch/arm/common/dmabounce.c
+4
-2
arch/arm/kernel/perf_event.c
+4
-2
arch/arm/kernel/perf_event.c
···
583
583
static void armpmu_enable(struct pmu *pmu)
584
584
{
585
585
/* Enable all of the perf events on hardware. */
586
-
int idx;
586
+
int idx, enabled = 0;
587
587
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
588
588
589
589
if (!armpmu)
···
596
596
continue;
597
597
598
598
armpmu->enable(&event->hw, idx);
599
+
enabled = 1;
599
600
}
600
601
601
-
armpmu->start();
602
+
if (enabled)
603
+
armpmu->start();
602
604
}
603
605
604
606
static void armpmu_disable(struct pmu *pmu)
+2
arch/arm/kernel/setup.c
+2
arch/arm/kernel/setup.c
···
73
73
#endif
74
74
75
75
extern void paging_init(struct machine_desc *desc);
76
+
extern void sanity_check_meminfo(void);
76
77
extern void reboot_setup(char *str);
77
78
78
79
unsigned int processor_id;
···
901
900
902
901
parse_early_param();
903
902
903
+
sanity_check_meminfo();
904
904
arm_memblock_init(&meminfo, mdesc);
905
905
906
906
paging_init(mdesc);
+1
-1
arch/arm/kernel/smp_twd.c
+1
-1
arch/arm/kernel/smp_twd.c
+2
-2
arch/arm/mach-ep93xx/core.c
+2
-2
arch/arm/mach-ep93xx/core.c
+12
-9
arch/arm/mach-vt8500/irq.c
+12
-9
arch/arm/mach-vt8500/irq.c
···
39
39
static void __iomem *ic_regbase;
40
40
static void __iomem *sic_regbase;
41
41
42
-
static void vt8500_irq_mask(unsigned int irq)
42
+
static void vt8500_irq_mask(struct irq_data *d)
43
43
{
44
44
void __iomem *base = ic_regbase;
45
+
unsigned irq = d->irq;
45
46
u8 edge;
46
47
47
48
if (irq >= 64) {
···
65
64
}
66
65
}
67
66
68
-
static void vt8500_irq_unmask(unsigned int irq)
67
+
static void vt8500_irq_unmask(struct irq_data *d)
69
68
{
70
69
void __iomem *base = ic_regbase;
70
+
unsigned irq = d->irq;
71
71
u8 dctr;
72
72
73
73
if (irq >= 64) {
···
80
78
writeb(dctr, base + VT8500_IC_DCTR + irq);
81
79
}
82
80
83
-
static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type)
81
+
static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
84
82
{
85
83
void __iomem *base = ic_regbase;
86
-
unsigned int orig_irq = irq;
84
+
unsigned irq = d->irq;
85
+
unsigned orig_irq = irq;
87
86
u8 dctr;
88
87
89
88
if (irq >= 64) {
···
117
114
}
118
115
119
116
static struct irq_chip vt8500_irq_chip = {
120
-
.name = "vt8500",
121
-
.ack = vt8500_irq_mask,
122
-
.mask = vt8500_irq_mask,
123
-
.unmask = vt8500_irq_unmask,
124
-
.set_type = vt8500_irq_set_type,
117
+
.name = "vt8500",
118
+
.irq_ack = vt8500_irq_mask,
119
+
.irq_mask = vt8500_irq_mask,
120
+
.irq_unmask = vt8500_irq_unmask,
121
+
.irq_set_type = vt8500_irq_set_type,
125
122
};
126
123
127
124
void __init vt8500_init_irq(void)
+13
-6
arch/arm/mm/cache-l2x0.c
+13
-6
arch/arm/mm/cache-l2x0.c
···
120
120
spin_unlock_irqrestore(&l2x0_lock, flags);
121
121
}
122
122
123
+
static void __l2x0_flush_all(void)
124
+
{
125
+
debug_writel(0x03);
126
+
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
127
+
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
128
+
cache_sync();
129
+
debug_writel(0x00);
130
+
}
131
+
123
132
static void l2x0_flush_all(void)
124
133
{
125
134
unsigned long flags;
126
135
127
136
/* clean all ways */
128
137
spin_lock_irqsave(&l2x0_lock, flags);
129
-
debug_writel(0x03);
130
-
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
131
-
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
132
-
cache_sync();
133
-
debug_writel(0x00);
138
+
__l2x0_flush_all();
134
139
spin_unlock_irqrestore(&l2x0_lock, flags);
135
140
}
136
141
···
271
266
unsigned long flags;
272
267
273
268
spin_lock_irqsave(&l2x0_lock, flags);
274
-
writel(0, l2x0_base + L2X0_CTRL);
269
+
__l2x0_flush_all();
270
+
writel_relaxed(0, l2x0_base + L2X0_CTRL);
271
+
dsb();
275
272
spin_unlock_irqrestore(&l2x0_lock, flags);
276
273
}
277
274
+3
-2
arch/arm/mm/mmu.c
+3
-2
arch/arm/mm/mmu.c
···
759
759
760
760
static phys_addr_t lowmem_limit __initdata = 0;
761
761
762
-
static void __init sanity_check_meminfo(void)
762
+
void __init sanity_check_meminfo(void)
763
763
{
764
764
int i, j, highmem = 0;
765
765
···
1032
1032
{
1033
1033
void *zero_page;
1034
1034
1035
+
memblock_set_current_limit(lowmem_limit);
1036
+
1035
1037
build_mem_type_table();
1036
-
sanity_check_meminfo();
1037
1038
prepare_page_table();
1038
1039
map_lowmem();
1039
1040
devicemaps_init(mdesc);
+4
arch/arm/mm/nommu.c
+4
arch/arm/mm/nommu.c
+2
drivers/mmc/host/mmci.c
+2
drivers/mmc/host/mmci.c
···
582
582
data->error = -EILSEQ;
583
583
} else if (status & MCI_DATATIMEOUT) {
584
584
data->error = -ETIMEDOUT;
585
+
} else if (status & MCI_STARTBITERR) {
586
+
data->error = -ECOMM;
585
587
} else if (status & MCI_TXUNDERRUN) {
586
588
data->error = -EIO;
587
589
} else if (status & MCI_RXOVERRUN) {
+4
-1
drivers/mmc/host/mmci.h
+4
-1
drivers/mmc/host/mmci.h
···
86
86
#define MCI_CMDRESPEND (1 << 6)
87
87
#define MCI_CMDSENT (1 << 7)
88
88
#define MCI_DATAEND (1 << 8)
89
+
#define MCI_STARTBITERR (1 << 9)
89
90
#define MCI_DATABLOCKEND (1 << 10)
90
91
#define MCI_CMDACTIVE (1 << 11)
91
92
#define MCI_TXACTIVE (1 << 12)
···
113
112
#define MCI_CMDRESPENDCLR (1 << 6)
114
113
#define MCI_CMDSENTCLR (1 << 7)
115
114
#define MCI_DATAENDCLR (1 << 8)
115
+
#define MCI_STARTBITERRCLR (1 << 9)
116
116
#define MCI_DATABLOCKENDCLR (1 << 10)
117
117
/* Extended status bits for the ST Micro variants */
118
118
#define MCI_ST_SDIOITC (1 << 22)
···
129
127
#define MCI_CMDRESPENDMASK (1 << 6)
130
128
#define MCI_CMDSENTMASK (1 << 7)
131
129
#define MCI_DATAENDMASK (1 << 8)
130
+
#define MCI_STARTBITERRMASK (1 << 9)
132
131
#define MCI_DATABLOCKENDMASK (1 << 10)
133
132
#define MCI_CMDACTIVEMASK (1 << 11)
134
133
#define MCI_TXACTIVEMASK (1 << 12)
···
153
150
#define MCI_IRQENABLE \
154
151
(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
155
152
MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
156
-
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK)
153
+
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK)
157
154
158
155
/* These interrupts are directed to IRQ1 when two IRQ lines are available */
159
156
#define MCI_IRQ1MASK \