tjh.dev / kernel
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Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/radeon/kms: clean up multiple crtc handling for evergreen+ (v2)

Linus Torvalds 8733449b f1a04dbd

+97 -60
+97 -60
drivers/gpu/drm/radeon/evergreen.c
··· 985 985 { 986 986 save->vga_control[0] = RREG32(D1VGA_CONTROL); 987 987 save->vga_control[1] = RREG32(D2VGA_CONTROL); 988 - save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); 989 - save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); 990 - save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); 991 - save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); 992 988 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 993 989 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 994 990 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 995 991 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 996 - if (!(rdev->flags & RADEON_IS_IGP)) { 992 + if (rdev->num_crtc >= 4) { 993 + save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); 994 + save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); 997 995 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 998 996 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 997 + } 998 + if (rdev->num_crtc >= 6) { 999 + save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); 1000 + save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); 999 1001 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 1000 1002 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 1001 1003 } ··· 1006 1004 WREG32(VGA_RENDER_CONTROL, 0); 1007 1005 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1008 1006 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1009 - if (!(rdev->flags & RADEON_IS_IGP)) { 1007 + if (rdev->num_crtc >= 4) { 1010 1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1011 1009 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1010 + } 1011 + if (rdev->num_crtc >= 6) { 1012 1012 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1013 1013 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1014 1014 } 1015 1015 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1016 1016 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1017 - if (!(rdev->flags & RADEON_IS_IGP)) { 1017 + if (rdev->num_crtc >= 4) { 1018 1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1019 1019 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1020 + } 1021 + if (rdev->num_crtc >= 6) { 1020 1022 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1021 1023 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1022 1024 } 1023 1025 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1024 1026 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1025 - if (!(rdev->flags & RADEON_IS_IGP)) { 1027 + if (rdev->num_crtc >= 4) { 1026 1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1027 1029 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1030 + } 1031 + if (rdev->num_crtc >= 6) { 1028 1032 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1029 1033 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1030 1034 } 1031 1035 1032 1036 WREG32(D1VGA_CONTROL, 0); 1033 1037 WREG32(D2VGA_CONTROL, 0); 1034 - WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1035 - WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1036 - WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1037 - WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1038 + if (rdev->num_crtc >= 4) { 1039 + WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1040 + WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1041 + } 1042 + if (rdev->num_crtc >= 6) { 1043 + WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1044 + WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1045 + } 1038 1046 } 1039 1047 1040 1048 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) ··· 1067 1055 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1068 1056 (u32)rdev->mc.vram_start); 1069 1057 1070 - if (!(rdev->flags & RADEON_IS_IGP)) { 1058 + if (rdev->num_crtc >= 4) { 1071 1059 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1072 1060 upper_32_bits(rdev->mc.vram_start)); 1073 1061 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, ··· 1085 1073 (u32)rdev->mc.vram_start); 1086 1074 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1087 1075 (u32)rdev->mc.vram_start); 1088 - 1076 + } 1077 + if (rdev->num_crtc >= 6) { 1089 1078 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1090 1079 upper_32_bits(rdev->mc.vram_start)); 1091 1080 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, ··· 1114 1101 /* Restore video state */ 1115 1102 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1116 1103 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1117 - WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1118 - WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1119 - WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1120 - WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1104 + if (rdev->num_crtc >= 4) { 1105 + WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1106 + WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1107 + } 1108 + if (rdev->num_crtc >= 6) { 1109 + WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1110 + WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1111 + } 1121 1112 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1122 1113 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1123 - if (!(rdev->flags & RADEON_IS_IGP)) { 1114 + if (rdev->num_crtc >= 4) { 1124 1115 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1125 1116 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1117 + } 1118 + if (rdev->num_crtc >= 6) { 1126 1119 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1127 1120 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1128 1121 } 1129 1122 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1130 1123 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1131 - if (!(rdev->flags & RADEON_IS_IGP)) { 1124 + if (rdev->num_crtc >= 4) { 1132 1125 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1133 1126 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1127 + } 1128 + if (rdev->num_crtc >= 6) { 1134 1129 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1135 1130 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1136 1131 } 1137 1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1138 1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1139 - if (!(rdev->flags & RADEON_IS_IGP)) { 1134 + if (rdev->num_crtc >= 4) { 1140 1135 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1141 1136 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1137 + } 1138 + if (rdev->num_crtc >= 6) { 1142 1139 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1143 1140 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1144 1141 } ··· 2440 2417 WREG32(GRBM_INT_CNTL, 0); 2441 2418 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2442 2419 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2443 - if (!(rdev->flags & RADEON_IS_IGP)) { 2420 + if (rdev->num_crtc >= 4) { 2444 2421 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2445 2422 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2423 + } 2424 + if (rdev->num_crtc >= 6) { 2446 2425 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2447 2426 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2448 2427 } 2449 2428 2450 2429 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2451 2430 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2452 - if (!(rdev->flags & RADEON_IS_IGP)) { 2431 + if (rdev->num_crtc >= 4) { 2453 2432 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2454 2433 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2434 + } 2435 + if (rdev->num_crtc >= 6) { 2455 2436 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2456 2437 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2457 2438 } ··· 2574 2547 2575 2548 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2576 2549 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2577 - if (!(rdev->flags & RADEON_IS_IGP)) { 2550 + if (rdev->num_crtc >= 4) { 2578 2551 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2579 2552 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2553 + } 2554 + if (rdev->num_crtc >= 6) { 2580 2555 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2581 2556 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2582 2557 } 2583 2558 2584 2559 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2585 2560 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2586 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2587 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2588 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2589 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2561 + if (rdev->num_crtc >= 4) { 2562 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2563 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2564 + } 2565 + if (rdev->num_crtc >= 6) { 2566 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2567 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2568 + } 2590 2569 2591 2570 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2592 2571 WREG32(DC_HPD2_INT_CONTROL, hpd2); ··· 2616 2583 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2617 2584 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2618 2585 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2619 - rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2620 - rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2621 - rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2622 - rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2586 + if (rdev->num_crtc >= 4) { 2587 + rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2588 + rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2589 + } 2590 + if (rdev->num_crtc >= 6) { 2591 + rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2592 + rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2593 + } 2623 2594 2624 2595 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2625 2596 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2626 2597 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2627 2598 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2628 - if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 2629 - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2630 - if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 2631 - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2632 - if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 2633 - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2634 - if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 2635 - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2636 - 2637 2599 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2638 2600 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2639 2601 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2640 2602 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2641 - 2642 2603 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2643 2604 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2644 2605 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2645 2606 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2646 2607 2647 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2648 - WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2649 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2650 - WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2608 + if (rdev->num_crtc >= 4) { 2609 + if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 2610 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2611 + if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 2612 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2613 + if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2614 + WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2615 + if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2616 + WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2617 + if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2618 + WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2619 + if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2620 + WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2621 + } 2651 2622 2652 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2653 - WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2654 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2655 - WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2656 - 2657 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2658 - WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2659 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2660 - WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2661 - 2662 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2663 - WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2664 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2665 - WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2623 + if (rdev->num_crtc >= 6) { 2624 + if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 2625 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2626 + if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 2627 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2628 + if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2629 + WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2630 + if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2631 + WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2632 + if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2633 + WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2634 + if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2635 + WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2636 + } 2666 2637 2667 2638 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2668 2639 tmp = RREG32(DC_HPD1_INT_CONTROL);