+15

Documentation/ABI/testing/sysfs-class-tee

reviewed

··· 1 1 + What: /sys/class/tee/tee{,priv}X/rpmb_routing_model 2 2 + Date: May 2024 3 3 + KernelVersion: 6.10 4 4 + Contact: op-tee@lists.trustedfirmware.org 5 5 + Description: 6 6 + RPMB frames can be routed to the RPMB device via the 7 7 + user-space daemon tee-supplicant or the RPMB subsystem 8 8 + in the kernel. The value "user" means that the driver 9 9 + will route the RPMB frames via user space. Conversely, 10 10 + "kernel" means that the frames are routed via the RPMB 11 11 + subsystem without assistance from tee-supplicant. It 12 12 + should be assumed that RPMB frames are routed via user 13 13 + space if the variable is absent. The primary purpose 14 14 + of this variable is to let systemd know whether 15 15 + tee-supplicant is needed in the early boot with initramfs.

+92

Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/mmc/atmel,sama5d2-sdhci.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Atmel SDHCI controller 8 8 + 9 9 + maintainers: 10 10 + - Aubin Constans <aubin.constans@microchip.com> 11 11 + - Nicolas Ferre <nicolas.ferre@microchip.com> 12 12 + 13 13 + description: 14 14 + Bindings for the SDHCI controller found in Atmel/Microchip SoCs. 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + oneOf: 19 19 + - enum: 20 20 + - atmel,sama5d2-sdhci 21 21 + - microchip,sam9x60-sdhci 22 22 + - items: 23 23 + - enum: 24 24 + - microchip,sam9x7-sdhci 25 25 + - microchip,sama7g5-sdhci 26 26 + - const: microchip,sam9x60-sdhci 27 27 + 28 28 + reg: 29 29 + maxItems: 1 30 30 + 31 31 + interrupts: 32 32 + maxItems: 1 33 33 + 34 34 + clocks: 35 35 + items: 36 36 + - description: hclock 37 37 + - description: multclk 38 38 + - description: baseclk 39 39 + minItems: 2 40 40 + 41 41 + clock-names: 42 42 + items: 43 43 + - const: hclock 44 44 + - const: multclk 45 45 + - const: baseclk 46 46 + minItems: 2 47 47 + 48 48 + microchip,sdcal-inverted: 49 49 + type: boolean 50 50 + description: 51 51 + When present, polarity on the SDCAL SoC pin is inverted. The default 52 52 + polarity for this signal is described in the datasheet. For instance on 53 53 + SAMA5D2, the pin is usually tied to the GND with a resistor and a 54 54 + capacitor (see "SDMMC I/O Calibration" chapter). 55 55 + 56 56 + required: 57 57 + - compatible 58 58 + - reg 59 59 + - interrupts 60 60 + - clocks 61 61 + - clock-names 62 62 + 63 63 + allOf: 64 64 + - $ref: sdhci-common.yaml# 65 65 + - if: 66 66 + properties: 67 67 + compatible: 68 68 + contains: 69 69 + enum: 70 70 + - atmel,sama5d2-sdhci 71 71 + then: 72 72 + properties: 73 73 + clocks: 74 74 + minItems: 3 75 75 + clock-names: 76 76 + minItems: 3 77 77 + 78 78 + unevaluatedProperties: false 79 79 + 80 80 + examples: 81 81 + - | 82 82 + #include <dt-bindings/interrupt-controller/irq.h> 83 83 + #include <dt-bindings/clock/at91.h> 84 84 + mmc@a0000000 { 85 85 + compatible = "atmel,sama5d2-sdhci"; 86 86 + reg = <0xa0000000 0x300>; 87 87 + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 88 88 + clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; 89 89 + clock-names = "hclock", "multclk", "baseclk"; 90 90 + assigned-clocks = <&sdmmc0_gclk>; 91 91 + assigned-clock-rates = <480000000>; 92 92 + };

+87

Documentation/devicetree/bindings/mmc/nuvoton,ma35d1-sdhci.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/mmc/nuvoton,ma35d1-sdhci.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Nuvoton MA35D1 SD/SDIO/MMC Controller 8 8 + 9 9 + maintainers: 10 10 + - Shan-Chun Hung <shanchun1218@gmail.com> 11 11 + 12 12 + allOf: 13 13 + - $ref: sdhci-common.yaml# 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + enum: 18 18 + - nuvoton,ma35d1-sdhci 19 19 + 20 20 + reg: 21 21 + maxItems: 1 22 22 + 23 23 + interrupts: 24 24 + maxItems: 1 25 25 + 26 26 + clocks: 27 27 + maxItems: 1 28 28 + 29 29 + pinctrl-names: 30 30 + minItems: 1 31 31 + items: 32 32 + - const: default 33 33 + - const: state_uhs 34 34 + 35 35 + pinctrl-0: 36 36 + description: 37 37 + Should contain default/high speed pin ctrl. 38 38 + maxItems: 1 39 39 + 40 40 + pinctrl-1: 41 41 + description: 42 42 + Should contain uhs mode pin ctrl. 43 43 + maxItems: 1 44 44 + 45 45 + resets: 46 46 + maxItems: 1 47 47 + 48 48 + nuvoton,sys: 49 49 + $ref: /schemas/types.yaml#/definitions/phandle 50 50 + description: phandle to access GCR (Global Control Register) registers. 51 51 + 52 52 + required: 53 53 + - compatible 54 54 + - reg 55 55 + - interrupts 56 56 + - clocks 57 57 + - pinctrl-names 58 58 + - pinctrl-0 59 59 + - resets 60 60 + - nuvoton,sys 61 61 + 62 62 + unevaluatedProperties: false 63 63 + 64 64 + examples: 65 65 + - | 66 66 + #include <dt-bindings/interrupt-controller/arm-gic.h> 67 67 + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 68 68 + #include <dt-bindings/reset/nuvoton,ma35d1-reset.h> 69 69 + 70 70 + soc { 71 71 + #address-cells = <2>; 72 72 + #size-cells = <2>; 73 73 + mmc@40190000 { 74 74 + compatible = "nuvoton,ma35d1-sdhci"; 75 75 + reg = <0x0 0x40190000 0x0 0x2000>; 76 76 + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 77 77 + clocks = <&clk SDH1_GATE>; 78 78 + pinctrl-names = "default", "state_uhs"; 79 79 + pinctrl-0 = <&pinctrl_sdhci1>; 80 80 + pinctrl-1 = <&pinctrl_sdhci1_uhs>; 81 81 + resets = <&sys MA35D1_RESET_SDH1>; 82 82 + nuvoton,sys = <&sys>; 83 83 + vqmmc-supply = <&sdhci1_vqmmc_regulator>; 84 84 + bus-width = <8>; 85 85 + max-frequency = <200000000>; 86 86 + }; 87 87 + };

+10 -3

Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml

reviewed

··· 18 18 - renesas,sdhi-r7s9210 # SH-Mobile AG5 19 19 - renesas,sdhi-r8a73a4 # R-Mobile APE6 20 20 - renesas,sdhi-r8a7740 # R-Mobile A1 21 21 + - renesas,sdhi-r9a09g057 # RZ/V2H(P) 21 22 - renesas,sdhi-sh73a0 # R-Mobile APE6 22 23 - items: 23 24 - enum: ··· 76 75 minItems: 1 77 76 maxItems: 3 78 77 79 79 - clocks: true 78 78 + clocks: 79 79 + minItems: 1 80 80 + maxItems: 4 80 81 81 81 - clock-names: true 82 82 + clock-names: 83 83 + minItems: 1 84 84 + maxItems: 4 82 85 83 86 dmas: 84 87 minItems: 4 ··· 123 118 properties: 124 119 compatible: 125 120 contains: 126 126 - const: renesas,rzg2l-sdhi 121 121 + enum: 122 122 + - renesas,sdhi-r9a09g057 123 123 + - renesas,rzg2l-sdhi 127 124 then: 128 125 properties: 129 126 clocks:

+2

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml

reviewed

··· 43 43 - rockchip,rv1108-dw-mshc 44 44 - rockchip,rv1126-dw-mshc 45 45 - const: rockchip,rk3288-dw-mshc 46 46 + # for Rockchip RK3576 with phase tuning inside the controller 47 47 + - const: rockchip,rk3576-dw-mshc 46 48 47 49 reg: 48 50 maxItems: 1

-35

Documentation/devicetree/bindings/mmc/sdhci-atmel.txt

reviewed

··· 1 1 - * Atmel SDHCI controller 2 2 - 3 3 - This file documents the differences between the core properties in 4 4 - Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the 5 5 - sdhci-of-at91 driver. 6 6 - 7 7 - Required properties: 8 8 - - compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci" 9 9 - or "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci". 10 10 - - clocks: Phandlers to the clocks. 11 11 - - clock-names: Must be "hclock", "multclk", "baseclk" for 12 12 - "atmel,sama5d2-sdhci". 13 13 - Must be "hclock", "multclk" for "microchip,sam9x60-sdhci". 14 14 - Must be "hclock", "multclk" for "microchip,sam9x7-sdhci". 15 15 - 16 16 - Optional properties: 17 17 - - assigned-clocks: The same with "multclk". 18 18 - - assigned-clock-rates The rate of "multclk" in order to not rely on the 19 19 - gck configuration set by previous components. 20 20 - - microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is 21 21 - inverted. The default polarity for this signal is described in the datasheet. 22 22 - For instance on SAMA5D2, the pin is usually tied to the GND with a resistor 23 23 - and a capacitor (see "SDMMC I/O Calibration" chapter). 24 24 - 25 25 - Example: 26 26 - 27 27 - mmc0: sdio-host@a0000000 { 28 28 - compatible = "atmel,sama5d2-sdhci"; 29 29 - reg = <0xa0000000 0x300>; 30 30 - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 31 31 - clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; 32 32 - clock-names = "hclock", "multclk", "baseclk"; 33 33 - assigned-clocks = <&sdmmc0_gclk>; 34 34 - assigned-clock-rates = <480000000>; 35 35 - };

+71 -24

Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml

reviewed

··· 10 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com> 12 12 13 13 - allOf: 14 14 - - $ref: mmc-controller.yaml# 15 15 - 16 13 properties: 17 14 compatible: 18 18 - enum: 19 19 - - rockchip,rk3568-dwcmshc 20 20 - - rockchip,rk3588-dwcmshc 21 21 - - snps,dwcmshc-sdhci 22 22 - - sophgo,cv1800b-dwcmshc 23 23 - - sophgo,sg2002-dwcmshc 24 24 - - thead,th1520-dwcmshc 15 15 + oneOf: 16 16 + - items: 17 17 + - const: rockchip,rk3576-dwcmshc 18 18 + - const: rockchip,rk3588-dwcmshc 19 19 + - enum: 20 20 + - rockchip,rk3568-dwcmshc 21 21 + - rockchip,rk3588-dwcmshc 22 22 + - snps,dwcmshc-sdhci 23 23 + - sophgo,cv1800b-dwcmshc 24 24 + - sophgo,sg2002-dwcmshc 25 25 + - sophgo,sg2042-dwcmshc 26 26 + - thead,th1520-dwcmshc 25 27 26 28 reg: 27 29 maxItems: 1 ··· 33 31 34 32 clocks: 35 33 minItems: 1 36 36 - items: 37 37 - - description: core clock 38 38 - - description: bus clock for optional 39 39 - - description: axi clock for rockchip specified 40 40 - - description: block clock for rockchip specified 41 41 - - description: timer clock for rockchip specified 42 42 - 34 34 + maxItems: 5 43 35 44 36 clock-names: 45 37 minItems: 1 46 46 - items: 47 47 - - const: core 48 48 - - const: bus 49 49 - - const: axi 50 50 - - const: block 51 51 - - const: timer 38 38 + maxItems: 5 39 39 + 40 40 + power-domains: 41 41 + maxItems: 1 52 42 53 43 resets: 54 44 maxItems: 5 ··· 57 63 description: Specify the number of delay for tx sampling. 58 64 $ref: /schemas/types.yaml#/definitions/uint8 59 65 60 60 - 61 66 required: 62 67 - compatible 63 68 - reg 64 69 - interrupts 65 70 - clocks 66 71 - clock-names 72 72 + 73 73 + allOf: 74 74 + - $ref: mmc-controller.yaml# 75 75 + 76 76 + - if: 77 77 + properties: 78 78 + compatible: 79 79 + contains: 80 80 + const: sophgo,sg2042-dwcmshc 81 81 + 82 82 + then: 83 83 + properties: 84 84 + clocks: 85 85 + items: 86 86 + - description: core clock 87 87 + - description: bus clock 88 88 + - description: timer clock 89 89 + clock-names: 90 90 + items: 91 91 + - const: core 92 92 + - const: bus 93 93 + - const: timer 94 94 + else: 95 95 + properties: 96 96 + clocks: 97 97 + minItems: 1 98 98 + items: 99 99 + - description: core clock 100 100 + - description: bus clock for optional 101 101 + - description: axi clock for rockchip specified 102 102 + - description: block clock for rockchip specified 103 103 + - description: timer clock for rockchip specified 104 104 + clock-names: 105 105 + minItems: 1 106 106 + items: 107 107 + - const: core 108 108 + - const: bus 109 109 + - const: axi 110 110 + - const: block 111 111 + - const: timer 112 112 + 113 113 + - if: 114 114 + properties: 115 115 + compatible: 116 116 + contains: 117 117 + const: rockchip,rk3576-dwcmshc 118 118 + 119 119 + then: 120 120 + required: 121 121 + - power-domains 122 122 + 123 123 + else: 124 124 + properties: 125 125 + power-domains: false 67 126 68 127 unevaluatedProperties: false 69 128

+1

Documentation/driver-api/mmc/index.rst

reviewed

··· 10 10 mmc-dev-attrs 11 11 mmc-dev-parts 12 12 mmc-async-req 13 13 + mmc-test 13 14 mmc-tools

+299

Documentation/driver-api/mmc/mmc-test.rst

reviewed

··· 1 1 + .. SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + ======================== 4 4 + MMC Test Framework 5 5 + ======================== 6 6 + 7 7 + Overview 8 8 + ======== 9 9 + 10 10 + The `mmc_test` framework is designed to test the performance and reliability of host controller drivers and all devices handled by the MMC subsystem. This includes not only MMC devices but also SD cards and other devices supported by the subsystem. 11 11 + 12 12 + The framework provides a variety of tests to evaluate different aspects of the host controller and device interactions, such as read and write performance, data integrity, and error handling. These tests help ensure that the host controller drivers and devices operate correctly under various conditions. 13 13 + 14 14 + The `mmc_test` framework is particularly useful for: 15 15 + 16 16 + - Verifying the functionality and performance of MMC and SD host controller drivers. 17 17 + - Ensuring compatibility and reliability of MMC and SD devices. 18 18 + - Identifying and diagnosing issues in the MMC subsystem. 19 19 + 20 20 + The results of the tests are logged in the kernel log, providing detailed information about the test outcomes and any encountered issues. 21 21 + 22 22 + Note: whatever is on your card will be overwritten by these tests. 23 23 + 24 24 + Initialization 25 25 + ============== 26 26 + 27 27 + To use the ``mmc_test`` framework, follow these steps: 28 28 + 29 29 + 1. **Enable the MMC Test Framework**: 30 30 + 31 31 + Ensure that the ``CONFIG_MMC_TEST`` kernel configuration option is enabled. This can be done by configuring the kernel: 32 32 + 33 33 + .. code-block:: none 34 34 + 35 35 + make menuconfig 36 36 + 37 37 + Navigate to: 38 38 + 39 39 + Device Drivers ---> 40 40 + <*> MMC/SD/SDIO card support ---> 41 41 + [*] MMC host test driver 42 42 + 43 43 + Alternatively, you can enable it directly in the kernel configuration file: 44 44 + 45 45 + .. code-block:: none 46 46 + 47 47 + echo "CONFIG_MMC_TEST=y" >> .config 48 48 + 49 49 + Rebuild and install the kernel if necessary. 50 50 + 51 51 + 2. **Load the MMC Test Module**: 52 52 + 53 53 + If the ``mmc_test`` framework is built as a module, you need to load it using ``modprobe``: 54 54 + 55 55 + .. code-block:: none 56 56 + 57 57 + modprobe mmc_test 58 58 + 59 59 + Binding the MMC Card for Testing 60 60 + ================================ 61 61 + 62 62 + To enable MMC testing, you need to unbind the MMC card from the ``mmcblk`` driver and bind it to the ``mmc_test`` driver. This allows the ``mmc_test`` framework to take control of the MMC card for testing purposes. 63 63 + 64 64 + 1. Identify the MMC card: 65 65 + 66 66 + .. code-block:: sh 67 67 + 68 68 + ls /sys/bus/mmc/devices/ 69 69 + 70 70 + This will list the MMC devices, such as ``mmc0:0001``. 71 71 + 72 72 + 2. Unbind the MMC card from the ``mmcblk`` driver: 73 73 + 74 74 + .. code-block:: sh 75 75 + 76 76 + echo 'mmc0:0001' > /sys/bus/mmc/drivers/mmcblk/unbind 77 77 + 78 78 + 3. Bind the MMC card to the ``mmc_test`` driver: 79 79 + 80 80 + .. code-block:: sh 81 81 + 82 82 + echo 'mmc0:0001' > /sys/bus/mmc/drivers/mmc_test/bind 83 83 + 84 84 + After binding, you should see a line in the kernel log indicating that the card has been claimed for testing: 85 85 + 86 86 + .. code-block:: none 87 87 + 88 88 + mmc_test mmc0:0001: Card claimed for testing. 89 89 + 90 90 + 91 91 + Usage - Debugfs Entries 92 92 + ======================= 93 93 + 94 94 + Once the ``mmc_test`` framework is enabled, you can interact with the following debugfs entries located in ``/sys/kernel/debug/mmc0/mmc0:0001``: 95 95 + 96 96 + 1. **test**: 97 97 + 98 98 + This file is used to run specific tests. Write the test number to this file to execute a test. 99 99 + 100 100 + .. code-block:: sh 101 101 + 102 102 + echo <test_number> > /sys/kernel/debug/mmc0/mmc0:0001/test 103 103 + 104 104 + The test result is indicated in the kernel log info. You can view the kernel log using the `dmesg` command or by checking the log file in `/var/log/`. 105 105 + 106 106 + .. code-block:: sh 107 107 + 108 108 + dmesg | grep mmc0 109 109 + 110 110 + Example: 111 111 + 112 112 + To run test number 4 (Basic read with data verification): 113 113 + 114 114 + .. code-block:: sh 115 115 + 116 116 + echo 4 > /sys/kernel/debug/mmc0/mmc0:0001/test 117 117 + 118 118 + Check the kernel log for the result: 119 119 + 120 120 + .. code-block:: sh 121 121 + 122 122 + dmesg | grep mmc0 123 123 + 124 124 + 2. **testlist**: 125 125 + 126 126 + This file lists all available tests. You can read this file to see the list of tests and their corresponding numbers. 127 127 + 128 128 + .. code-block:: sh 129 129 + 130 130 + cat /sys/kernel/debug/mmc0/mmc0:0001/testlist 131 131 + 132 132 + The available tests are listed in the table below: 133 133 + 134 134 + +------+--------------------------------+---------------------------------------------+ 135 135 + | Test | Test Name | Test Description | 136 136 + +======+================================+=============================================+ 137 137 + | 0 | Run all tests | Runs all available tests | 138 138 + +------+--------------------------------+---------------------------------------------+ 139 139 + | 1 | Basic write | Performs a basic write operation of a | 140 140 + | | | single 512-Byte block to the MMC card | 141 141 + | | | without data verification. | 142 142 + +------+--------------------------------+---------------------------------------------+ 143 143 + | 2 | Basic read | Same for read | 144 144 + +------+--------------------------------+---------------------------------------------+ 145 145 + | 3 | Basic write | Performs a basic write operation of a | 146 146 + | | (with data verification) | single 512-Byte block to the MMC card | 147 147 + | | | with data verification by reading back | 148 148 + | | | the written data and comparing it. | 149 149 + +------+--------------------------------+---------------------------------------------+ 150 150 + | 4 | Basic read | Same for read | 151 151 + | | (with data verification) | | 152 152 + +------+--------------------------------+---------------------------------------------+ 153 153 + | 5 | Multi-block write | Performs a multi-block write operation of | 154 154 + | | | 8 blocks (each 512 bytes) to the MMC card. | 155 155 + +------+--------------------------------+---------------------------------------------+ 156 156 + | 6 | Multi-block read | Same for read | 157 157 + +------+--------------------------------+---------------------------------------------+ 158 158 + | 7 | Power of two block writes | Performs write operations with block sizes | 159 159 + | | | that are powers of two, starting from 1 | 160 160 + | | | byte up to 256 bytes, to the MMC card. | 161 161 + +------+--------------------------------+---------------------------------------------+ 162 162 + | 8 | Power of two block reads | Same for read | 163 163 + +------+--------------------------------+---------------------------------------------+ 164 164 + | 9 | Weird sized block writes | Performs write operations with varying | 165 165 + | | | block sizes starting from 3 bytes and | 166 166 + | | | increasing by 7 bytes each iteration, up | 167 167 + | | | to 511 bytes, to the MMC card. | 168 168 + +------+--------------------------------+---------------------------------------------+ 169 169 + | 10 | Weird sized block reads | same for read | 170 170 + +------+--------------------------------+---------------------------------------------+ 171 171 + | 11 | Badly aligned write | Performs write operations with buffers | 172 172 + | | | starting at different alignments (0 to 7 | 173 173 + | | | bytes offset) to test how the MMC card | 174 174 + | | | handles unaligned data transfers. | 175 175 + +------+--------------------------------+---------------------------------------------+ 176 176 + | 12 | Badly aligned read | same for read | 177 177 + +------+--------------------------------+---------------------------------------------+ 178 178 + | 13 | Badly aligned multi-block write| same for multi-write | 179 179 + +------+--------------------------------+---------------------------------------------+ 180 180 + | 14 | Badly aligned multi-block read | same for multi-read | 181 181 + +------+--------------------------------+---------------------------------------------+ 182 182 + | 15 | Proper xfer_size at write | intentionally create a broken transfer by | 183 183 + | | (Start failure) | modifying the MMC request in a way that it | 184 184 + | | | will not perform as expected, e.g. use | 185 185 + | | | MMC_WRITE_BLOCK for a multi-block transfer | 186 186 + +------+--------------------------------+---------------------------------------------+ 187 187 + | 16 | Proper xfer_size at read | same for read | 188 188 + | | (Start failure) | | 189 189 + +------+--------------------------------+---------------------------------------------+ 190 190 + | 17 | Proper xfer_size at write | same for 2 blocks | 191 191 + | | (Midway failure) | | 192 192 + +------+--------------------------------+---------------------------------------------+ 193 193 + | 18 | Proper xfer_size at read | same for read | 194 194 + | | (Midway failure) | | 195 195 + +------+--------------------------------+---------------------------------------------+ 196 196 + | 19 | Highmem write | use a high memory page | 197 197 + +------+--------------------------------+---------------------------------------------+ 198 198 + | 20 | Highmem read | same for read | 199 199 + +------+--------------------------------+---------------------------------------------+ 200 200 + | 21 | Multi-block highmem write | same for multi-write | 201 201 + +------+--------------------------------+---------------------------------------------+ 202 202 + | 22 | Multi-block highmem read | same for mult-read | 203 203 + +------+--------------------------------+---------------------------------------------+ 204 204 + | 23 | Best-case read performance | Performs 512K sequential read (non sg) | 205 205 + +------+--------------------------------+---------------------------------------------+ 206 206 + | 24 | Best-case write performance | same for write | 207 207 + +------+--------------------------------+---------------------------------------------+ 208 208 + | 25 | Best-case read performance | Same using sg | 209 209 + | | (Into scattered pages) | | 210 210 + +------+--------------------------------+---------------------------------------------+ 211 211 + | 26 | Best-case write performance | same for write | 212 212 + | | (From scattered pages) | | 213 213 + +------+--------------------------------+---------------------------------------------+ 214 214 + | 27 | Single read performance | By transfer size | 215 215 + +------+--------------------------------+---------------------------------------------+ 216 216 + | 28 | Single write performance | By transfer size | 217 217 + +------+--------------------------------+---------------------------------------------+ 218 218 + | 29 | Single trim performance | By transfer size | 219 219 + +------+--------------------------------+---------------------------------------------+ 220 220 + | 30 | Consecutive read performance | By transfer size | 221 221 + +------+--------------------------------+---------------------------------------------+ 222 222 + | 31 | Consecutive write performance | By transfer size | 223 223 + +------+--------------------------------+---------------------------------------------+ 224 224 + | 32 | Consecutive trim performance | By transfer size | 225 225 + +------+--------------------------------+---------------------------------------------+ 226 226 + | 33 | Random read performance | By transfer size | 227 227 + +------+--------------------------------+---------------------------------------------+ 228 228 + | 34 | Random write performance | By transfer size | 229 229 + +------+--------------------------------+---------------------------------------------+ 230 230 + | 35 | Large sequential read | Into scattered pages | 231 231 + +------+--------------------------------+---------------------------------------------+ 232 232 + | 36 | Large sequential write | From scattered pages | 233 233 + +------+--------------------------------+---------------------------------------------+ 234 234 + | 37 | Write performance | With blocking req 4k to 4MB | 235 235 + +------+--------------------------------+---------------------------------------------+ 236 236 + | 38 | Write performance | With non-blocking req 4k to 4MB | 237 237 + +------+--------------------------------+---------------------------------------------+ 238 238 + | 39 | Read performance | With blocking req 4k to 4MB | 239 239 + +------+--------------------------------+---------------------------------------------+ 240 240 + | 40 | Read performance | With non-blocking req 4k to 4MB | 241 241 + +------+--------------------------------+---------------------------------------------+ 242 242 + | 41 | Write performance | Blocking req 1 to 512 sg elems | 243 243 + +------+--------------------------------+---------------------------------------------+ 244 244 + | 42 | Write performance | Non-blocking req 1 to 512 sg elems | 245 245 + +------+--------------------------------+---------------------------------------------+ 246 246 + | 43 | Read performance | Blocking req 1 to 512 sg elems | 247 247 + +------+--------------------------------+---------------------------------------------+ 248 248 + | 44 | Read performance | Non-blocking req 1 to 512 sg elems | 249 249 + +------+--------------------------------+---------------------------------------------+ 250 250 + | 45 | Reset test | | 251 251 + +------+--------------------------------+---------------------------------------------+ 252 252 + | 46 | Commands during read | No Set Block Count (CMD23) | 253 253 + +------+--------------------------------+---------------------------------------------+ 254 254 + | 47 | Commands during write | No Set Block Count (CMD23) | 255 255 + +------+--------------------------------+---------------------------------------------+ 256 256 + | 48 | Commands during read | Use Set Block Count (CMD23) | 257 257 + +------+--------------------------------+---------------------------------------------+ 258 258 + | 49 | Commands during write | Use Set Block Count (CMD23) | 259 259 + +------+--------------------------------+---------------------------------------------+ 260 260 + | 50 | Commands during non-blocking | Read - use Set Block Count (CMD23) | 261 261 + +------+--------------------------------+---------------------------------------------+ 262 262 + | 51 | Commands during non-blocking | Write - use Set Block Count (CMD23) | 263 263 + +------+--------------------------------+---------------------------------------------+ 264 264 + 265 265 + Test Results 266 266 + ============ 267 267 + 268 268 + The results of the tests are logged in the kernel log. Each test logs the start, end, and result of the test. The possible results are: 269 269 + 270 270 + - **OK**: The test completed successfully. 271 271 + - **FAILED**: The test failed. 272 272 + - **UNSUPPORTED (by host)**: The test is unsupported by the host. 273 273 + - **UNSUPPORTED (by card)**: The test is unsupported by the card. 274 274 + - **ERROR**: An error occurred during the test. 275 275 + 276 276 + Example Kernel Log Output 277 277 + ========================= 278 278 + 279 279 + When running a test, you will see log entries similar to the following in the kernel log: 280 280 + 281 281 + .. code-block:: none 282 282 + 283 283 + [ 1234.567890] mmc0: Starting tests of card mmc0:0001... 284 284 + [ 1234.567891] mmc0: Test case 4. Basic read (with data verification)... 285 285 + [ 1234.567892] mmc0: Result: OK 286 286 + [ 1234.567893] mmc0: Tests completed. 287 287 + 288 288 + In this example, test case 4 (Basic read with data verification) was executed, and the result was OK. 289 289 + 290 290 + 291 291 + Contributing 292 292 + ============ 293 293 + 294 294 + Contributions to the `mmc_test` framework are welcome. Please follow the standard Linux kernel contribution guidelines and submit patches to the appropriate maintainers. 295 295 + 296 296 + Contact 297 297 + ======= 298 298 + 299 299 + For more information or to report issues, please contact the MMC subsystem maintainers.

+8

MAINTAINERS

reviewed

··· 19974 19974 F: Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-de2-rotate.yaml 19975 19975 F: drivers/media/platform/sunxi/sun8i-rotate/ 19976 19976 19977 19977 + RPMB SUBSYSTEM 19978 19978 + M: Jens Wiklander <jens.wiklander@linaro.org> 19979 19979 + L: linux-kernel@vger.kernel.org 19980 19980 + S: Supported 19981 19981 + F: drivers/misc/rpmb-core.c 19982 19982 + F: include/linux/rpmb.h 19983 19983 + 19977 19984 RPMSG TTY DRIVER 19978 19985 M: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 19979 19986 L: linux-remoteproc@vger.kernel.org ··· 22587 22580 R: Sumit Garg <sumit.garg@linaro.org> 22588 22581 L: op-tee@lists.trustedfirmware.org 22589 22582 S: Maintained 22583 22583 + F: Documentation/ABI/testing/sysfs-class-tee 22590 22584 F: Documentation/driver-api/tee.rst 22591 22585 F: Documentation/tee/ 22592 22586 F: Documentation/userspace-api/tee.rst

+10

drivers/misc/Kconfig

reviewed

··· 104 104 If you choose to build module, its name will be phantom. If unsure, 105 105 say N here. 106 106 107 107 + config RPMB 108 108 + tristate "RPMB partition interface" 109 109 + depends on MMC 110 110 + help 111 111 + Unified RPMB unit interface for RPMB capable devices such as eMMC and 112 112 + UFS. Provides interface for in-kernel security controllers to access 113 113 + RPMB unit. 114 114 + 115 115 + If unsure, select N. 116 116 + 107 117 config TIFM_CORE 108 118 tristate "TI Flash Media interface support" 109 119 depends on PCI

+1

drivers/misc/Makefile

reviewed

··· 15 15 obj-$(CONFIG_TIFM_CORE) += tifm_core.o 16 16 obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o 17 17 obj-$(CONFIG_PHANTOM) += phantom.o 18 18 + obj-$(CONFIG_RPMB) += rpmb-core.o 18 19 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o 19 20 obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o 20 21 obj-$(CONFIG_SENSORS_BH1770) += bh1770glc.o

+231

drivers/misc/rpmb-core.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright(c) 2015 - 2019 Intel Corporation. All rights reserved. 4 4 + * Copyright(c) 2021 - 2024 Linaro Ltd. 5 5 + */ 6 6 + #include <linux/device.h> 7 7 + #include <linux/init.h> 8 8 + #include <linux/kernel.h> 9 9 + #include <linux/list.h> 10 10 + #include <linux/module.h> 11 11 + #include <linux/mutex.h> 12 12 + #include <linux/rpmb.h> 13 13 + #include <linux/slab.h> 14 14 + 15 15 + static DEFINE_IDA(rpmb_ida); 16 16 + static DEFINE_MUTEX(rpmb_mutex); 17 17 + 18 18 + /** 19 19 + * rpmb_dev_get() - increase rpmb device ref counter 20 20 + * @rdev: rpmb device 21 21 + */ 22 22 + struct rpmb_dev *rpmb_dev_get(struct rpmb_dev *rdev) 23 23 + { 24 24 + if (rdev) 25 25 + get_device(&rdev->dev); 26 26 + return rdev; 27 27 + } 28 28 + EXPORT_SYMBOL_GPL(rpmb_dev_get); 29 29 + 30 30 + /** 31 31 + * rpmb_dev_put() - decrease rpmb device ref counter 32 32 + * @rdev: rpmb device 33 33 + */ 34 34 + void rpmb_dev_put(struct rpmb_dev *rdev) 35 35 + { 36 36 + if (rdev) 37 37 + put_device(&rdev->dev); 38 38 + } 39 39 + EXPORT_SYMBOL_GPL(rpmb_dev_put); 40 40 + 41 41 + /** 42 42 + * rpmb_route_frames() - route rpmb frames to rpmb device 43 43 + * @rdev: rpmb device 44 44 + * @req: rpmb request frames 45 45 + * @req_len: length of rpmb request frames in bytes 46 46 + * @rsp: rpmb response frames 47 47 + * @rsp_len: length of rpmb response frames in bytes 48 48 + * 49 49 + * Returns: < 0 on failure 50 50 + */ 51 51 + int rpmb_route_frames(struct rpmb_dev *rdev, u8 *req, 52 52 + unsigned int req_len, u8 *rsp, unsigned int rsp_len) 53 53 + { 54 54 + if (!req || !req_len || !rsp || !rsp_len) 55 55 + return -EINVAL; 56 56 + 57 57 + return rdev->descr.route_frames(rdev->dev.parent, req, req_len, 58 58 + rsp, rsp_len); 59 59 + } 60 60 + EXPORT_SYMBOL_GPL(rpmb_route_frames); 61 61 + 62 62 + static void rpmb_dev_release(struct device *dev) 63 63 + { 64 64 + struct rpmb_dev *rdev = to_rpmb_dev(dev); 65 65 + 66 66 + mutex_lock(&rpmb_mutex); 67 67 + ida_simple_remove(&rpmb_ida, rdev->id); 68 68 + mutex_unlock(&rpmb_mutex); 69 69 + kfree(rdev->descr.dev_id); 70 70 + kfree(rdev); 71 71 + } 72 72 + 73 73 + static struct class rpmb_class = { 74 74 + .name = "rpmb", 75 75 + .dev_release = rpmb_dev_release, 76 76 + }; 77 77 + 78 78 + /** 79 79 + * rpmb_dev_find_device() - return first matching rpmb device 80 80 + * @start: rpmb device to begin with 81 81 + * @data: data for the match function 82 82 + * @match: the matching function 83 83 + * 84 84 + * Iterate over registered RPMB devices, and call @match() for each passing 85 85 + * it the RPMB device and @data. 86 86 + * 87 87 + * The return value of @match() is checked for each call. If it returns 88 88 + * anything other 0, break and return the found RPMB device. 89 89 + * 90 90 + * It's the callers responsibility to call rpmb_dev_put() on the returned 91 91 + * device, when it's done with it. 92 92 + * 93 93 + * Returns: a matching rpmb device or NULL on failure 94 94 + */ 95 95 + struct rpmb_dev *rpmb_dev_find_device(const void *data, 96 96 + const struct rpmb_dev *start, 97 97 + int (*match)(struct device *dev, 98 98 + const void *data)) 99 99 + { 100 100 + struct device *dev; 101 101 + const struct device *start_dev = NULL; 102 102 + 103 103 + if (start) 104 104 + start_dev = &start->dev; 105 105 + dev = class_find_device(&rpmb_class, start_dev, data, match); 106 106 + 107 107 + return dev ? to_rpmb_dev(dev) : NULL; 108 108 + } 109 109 + EXPORT_SYMBOL_GPL(rpmb_dev_find_device); 110 110 + 111 111 + int rpmb_interface_register(struct class_interface *intf) 112 112 + { 113 113 + intf->class = &rpmb_class; 114 114 + 115 115 + return class_interface_register(intf); 116 116 + } 117 117 + EXPORT_SYMBOL_GPL(rpmb_interface_register); 118 118 + 119 119 + void rpmb_interface_unregister(struct class_interface *intf) 120 120 + { 121 121 + class_interface_unregister(intf); 122 122 + } 123 123 + EXPORT_SYMBOL_GPL(rpmb_interface_unregister); 124 124 + 125 125 + /** 126 126 + * rpmb_dev_unregister() - unregister RPMB partition from the RPMB subsystem 127 127 + * @rdev: the rpmb device to unregister 128 128 + * 129 129 + * This function should be called from the release function of the 130 130 + * underlying device used when the RPMB device was registered. 131 131 + * 132 132 + * Returns: < 0 on failure 133 133 + */ 134 134 + int rpmb_dev_unregister(struct rpmb_dev *rdev) 135 135 + { 136 136 + if (!rdev) 137 137 + return -EINVAL; 138 138 + 139 139 + device_del(&rdev->dev); 140 140 + 141 141 + rpmb_dev_put(rdev); 142 142 + 143 143 + return 0; 144 144 + } 145 145 + EXPORT_SYMBOL_GPL(rpmb_dev_unregister); 146 146 + 147 147 + /** 148 148 + * rpmb_dev_register - register RPMB partition with the RPMB subsystem 149 149 + * @dev: storage device of the rpmb device 150 150 + * @descr: RPMB device description 151 151 + * 152 152 + * While registering the RPMB partition extract needed device information 153 153 + * while needed resources are available. 154 154 + * 155 155 + * Returns: a pointer to a 'struct rpmb_dev' or an ERR_PTR on failure 156 156 + */ 157 157 + struct rpmb_dev *rpmb_dev_register(struct device *dev, 158 158 + struct rpmb_descr *descr) 159 159 + { 160 160 + struct rpmb_dev *rdev; 161 161 + int ret; 162 162 + 163 163 + if (!dev || !descr || !descr->route_frames || !descr->dev_id || 164 164 + !descr->dev_id_len) 165 165 + return ERR_PTR(-EINVAL); 166 166 + 167 167 + rdev = kzalloc(sizeof(*rdev), GFP_KERNEL); 168 168 + if (!rdev) 169 169 + return ERR_PTR(-ENOMEM); 170 170 + rdev->descr = *descr; 171 171 + rdev->descr.dev_id = kmemdup(descr->dev_id, descr->dev_id_len, 172 172 + GFP_KERNEL); 173 173 + if (!rdev->descr.dev_id) { 174 174 + ret = -ENOMEM; 175 175 + goto err_free_rdev; 176 176 + } 177 177 + 178 178 + mutex_lock(&rpmb_mutex); 179 179 + ret = ida_simple_get(&rpmb_ida, 0, 0, GFP_KERNEL); 180 180 + mutex_unlock(&rpmb_mutex); 181 181 + if (ret < 0) 182 182 + goto err_free_dev_id; 183 183 + rdev->id = ret; 184 184 + 185 185 + dev_set_name(&rdev->dev, "rpmb%d", rdev->id); 186 186 + rdev->dev.class = &rpmb_class; 187 187 + rdev->dev.parent = dev; 188 188 + 189 189 + ret = device_register(&rdev->dev); 190 190 + if (ret) { 191 191 + put_device(&rdev->dev); 192 192 + return ERR_PTR(ret); 193 193 + } 194 194 + 195 195 + dev_dbg(&rdev->dev, "registered device\n"); 196 196 + 197 197 + return rdev; 198 198 + 199 199 + err_free_dev_id: 200 200 + kfree(rdev->descr.dev_id); 201 201 + err_free_rdev: 202 202 + kfree(rdev); 203 203 + return ERR_PTR(ret); 204 204 + } 205 205 + EXPORT_SYMBOL_GPL(rpmb_dev_register); 206 206 + 207 207 + static int __init rpmb_init(void) 208 208 + { 209 209 + int ret; 210 210 + 211 211 + ret = class_register(&rpmb_class); 212 212 + if (ret) { 213 213 + pr_err("couldn't create class\n"); 214 214 + return ret; 215 215 + } 216 216 + ida_init(&rpmb_ida); 217 217 + return 0; 218 218 + } 219 219 + 220 220 + static void __exit rpmb_exit(void) 221 221 + { 222 222 + ida_destroy(&rpmb_ida); 223 223 + class_unregister(&rpmb_class); 224 224 + } 225 225 + 226 226 + subsys_initcall(rpmb_init); 227 227 + module_exit(rpmb_exit); 228 228 + 229 229 + MODULE_AUTHOR("Jens Wiklander <jens.wiklander@linaro.org>"); 230 230 + MODULE_DESCRIPTION("RPMB class"); 231 231 + MODULE_LICENSE("GPL");

+1

drivers/mmc/core/Kconfig

reviewed

··· 37 37 config MMC_BLOCK 38 38 tristate "MMC block device driver" 39 39 depends on BLOCK 40 40 + depends on RPMB || !RPMB 40 41 imply IOSCHED_BFQ 41 42 default y 42 43 help

+244 -6

drivers/mmc/core/block.c

reviewed

··· 33 33 #include <linux/cdev.h> 34 34 #include <linux/mutex.h> 35 35 #include <linux/scatterlist.h> 36 36 + #include <linux/string.h> 36 37 #include <linux/string_helpers.h> 37 38 #include <linux/delay.h> 38 39 #include <linux/capability.h> ··· 41 40 #include <linux/pm_runtime.h> 42 41 #include <linux/idr.h> 43 42 #include <linux/debugfs.h> 43 43 + #include <linux/rpmb.h> 44 44 45 45 #include <linux/mmc/ioctl.h> 46 46 #include <linux/mmc/card.h> ··· 77 75 #define MMC_BLK_TIMEOUT_MS (10 * 1000) 78 76 #define MMC_EXTRACT_INDEX_FROM_ARG(x) ((x & 0x00FF0000) >> 16) 79 77 #define MMC_EXTRACT_VALUE_FROM_ARG(x) ((x & 0x0000FF00) >> 8) 78 78 + 79 79 + /** 80 80 + * struct rpmb_frame - rpmb frame as defined by eMMC 5.1 (JESD84-B51) 81 81 + * 82 82 + * @stuff : stuff bytes 83 83 + * @key_mac : The authentication key or the message authentication 84 84 + * code (MAC) depending on the request/response type. 85 85 + * The MAC will be delivered in the last (or the only) 86 86 + * block of data. 87 87 + * @data : Data to be written or read by signed access. 88 88 + * @nonce : Random number generated by the host for the requests 89 89 + * and copied to the response by the RPMB engine. 90 90 + * @write_counter: Counter value for the total amount of the successful 91 91 + * authenticated data write requests made by the host. 92 92 + * @addr : Address of the data to be programmed to or read 93 93 + * from the RPMB. Address is the serial number of 94 94 + * the accessed block (half sector 256B). 95 95 + * @block_count : Number of blocks (half sectors, 256B) requested to be 96 96 + * read/programmed. 97 97 + * @result : Includes information about the status of the write counter 98 98 + * (valid, expired) and result of the access made to the RPMB. 99 99 + * @req_resp : Defines the type of request and response to/from the memory. 100 100 + * 101 101 + * The stuff bytes and big-endian properties are modeled to fit to the spec. 102 102 + */ 103 103 + struct rpmb_frame { 104 104 + u8 stuff[196]; 105 105 + u8 key_mac[32]; 106 106 + u8 data[256]; 107 107 + u8 nonce[16]; 108 108 + __be32 write_counter; 109 109 + __be16 addr; 110 110 + __be16 block_count; 111 111 + __be16 result; 112 112 + __be16 req_resp; 113 113 + } __packed; 114 114 + 115 115 + #define RPMB_PROGRAM_KEY 0x1 /* Program RPMB Authentication Key */ 116 116 + #define RPMB_GET_WRITE_COUNTER 0x2 /* Read RPMB write counter */ 117 117 + #define RPMB_WRITE_DATA 0x3 /* Write data to RPMB partition */ 118 118 + #define RPMB_READ_DATA 0x4 /* Read data from RPMB partition */ 119 119 + #define RPMB_RESULT_READ 0x5 /* Read result request (Internal) */ 80 120 81 121 static DEFINE_MUTEX(block_mutex); 82 122 ··· 199 155 * @id: unique device ID number 200 156 * @part_index: partition index (0 on first) 201 157 * @md: parent MMC block device 158 158 + * @rdev: registered RPMB device 202 159 * @node: list item, so we can put this device on a list 203 160 */ 204 161 struct mmc_rpmb_data { ··· 208 163 int id; 209 164 unsigned int part_index; 210 165 struct mmc_blk_data *md; 166 166 + struct rpmb_dev *rdev; 211 167 struct list_head node; 212 168 }; 213 169 ··· 353 307 const char *buf, size_t count) 354 308 { 355 309 int ret; 356 356 - char *end; 357 310 struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); 358 358 - unsigned long set = simple_strtoul(buf, &end, 0); 359 359 - if (end == buf) { 311 311 + unsigned long set; 312 312 + 313 313 + if (kstrtoul(buf, 0, &set)) { 360 314 ret = -EINVAL; 361 315 goto out; 362 316 } ··· 2530 2484 return ERR_PTR(devidx); 2531 2485 } 2532 2486 2533 2533 - md = kzalloc(sizeof(struct mmc_blk_data), GFP_KERNEL); 2487 2487 + md = kzalloc(sizeof(*md), GFP_KERNEL); 2534 2488 if (!md) { 2535 2489 ret = -ENOMEM; 2536 2490 goto out; ··· 2716 2670 2717 2671 get_device(&rpmb->dev); 2718 2672 filp->private_data = rpmb; 2719 2719 - mmc_blk_get(rpmb->md->disk); 2720 2673 2721 2674 return nonseekable_open(inode, filp); 2722 2675 } ··· 2725 2680 struct mmc_rpmb_data *rpmb = container_of(inode->i_cdev, 2726 2681 struct mmc_rpmb_data, chrdev); 2727 2682 2728 2728 - mmc_blk_put(rpmb->md); 2729 2683 put_device(&rpmb->dev); 2730 2684 2731 2685 return 0; ··· 2745 2701 { 2746 2702 struct mmc_rpmb_data *rpmb = dev_get_drvdata(dev); 2747 2703 2704 2704 + rpmb_dev_unregister(rpmb->rdev); 2705 2705 + mmc_blk_put(rpmb->md); 2748 2706 ida_free(&mmc_rpmb_ida, rpmb->id); 2749 2707 kfree(rpmb); 2708 2708 + } 2709 2709 + 2710 2710 + static void free_idata(struct mmc_blk_ioc_data **idata, unsigned int cmd_count) 2711 2711 + { 2712 2712 + unsigned int n; 2713 2713 + 2714 2714 + for (n = 0; n < cmd_count; n++) 2715 2715 + kfree(idata[n]); 2716 2716 + kfree(idata); 2717 2717 + } 2718 2718 + 2719 2719 + static struct mmc_blk_ioc_data **alloc_idata(struct mmc_rpmb_data *rpmb, 2720 2720 + unsigned int cmd_count) 2721 2721 + { 2722 2722 + struct mmc_blk_ioc_data **idata; 2723 2723 + unsigned int n; 2724 2724 + 2725 2725 + idata = kcalloc(cmd_count, sizeof(*idata), GFP_KERNEL); 2726 2726 + if (!idata) 2727 2727 + return NULL; 2728 2728 + 2729 2729 + for (n = 0; n < cmd_count; n++) { 2730 2730 + idata[n] = kcalloc(1, sizeof(**idata), GFP_KERNEL); 2731 2731 + if (!idata[n]) { 2732 2732 + free_idata(idata, n); 2733 2733 + return NULL; 2734 2734 + } 2735 2735 + idata[n]->rpmb = rpmb; 2736 2736 + } 2737 2737 + 2738 2738 + return idata; 2739 2739 + } 2740 2740 + 2741 2741 + static void set_idata(struct mmc_blk_ioc_data *idata, u32 opcode, 2742 2742 + int write_flag, u8 *buf, unsigned int buf_bytes) 2743 2743 + { 2744 2744 + /* 2745 2745 + * The size of an RPMB frame must match what's expected by the 2746 2746 + * hardware. 2747 2747 + */ 2748 2748 + BUILD_BUG_ON(sizeof(struct rpmb_frame) != 512); 2749 2749 + 2750 2750 + idata->ic.opcode = opcode; 2751 2751 + idata->ic.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2752 2752 + idata->ic.write_flag = write_flag; 2753 2753 + idata->ic.blksz = sizeof(struct rpmb_frame); 2754 2754 + idata->ic.blocks = buf_bytes / idata->ic.blksz; 2755 2755 + idata->buf = buf; 2756 2756 + idata->buf_bytes = buf_bytes; 2757 2757 + } 2758 2758 + 2759 2759 + static int mmc_route_rpmb_frames(struct device *dev, u8 *req, 2760 2760 + unsigned int req_len, u8 *resp, 2761 2761 + unsigned int resp_len) 2762 2762 + { 2763 2763 + struct rpmb_frame *frm = (struct rpmb_frame *)req; 2764 2764 + struct mmc_rpmb_data *rpmb = dev_get_drvdata(dev); 2765 2765 + struct mmc_blk_data *md = rpmb->md; 2766 2766 + struct mmc_blk_ioc_data **idata; 2767 2767 + struct mmc_queue_req *mq_rq; 2768 2768 + unsigned int cmd_count; 2769 2769 + struct request *rq; 2770 2770 + u16 req_type; 2771 2771 + bool write; 2772 2772 + int ret; 2773 2773 + 2774 2774 + if (IS_ERR(md->queue.card)) 2775 2775 + return PTR_ERR(md->queue.card); 2776 2776 + 2777 2777 + if (req_len < sizeof(*frm)) 2778 2778 + return -EINVAL; 2779 2779 + 2780 2780 + req_type = be16_to_cpu(frm->req_resp); 2781 2781 + switch (req_type) { 2782 2782 + case RPMB_PROGRAM_KEY: 2783 2783 + if (req_len != sizeof(struct rpmb_frame) || 2784 2784 + resp_len != sizeof(struct rpmb_frame)) 2785 2785 + return -EINVAL; 2786 2786 + write = true; 2787 2787 + break; 2788 2788 + case RPMB_GET_WRITE_COUNTER: 2789 2789 + if (req_len != sizeof(struct rpmb_frame) || 2790 2790 + resp_len != sizeof(struct rpmb_frame)) 2791 2791 + return -EINVAL; 2792 2792 + write = false; 2793 2793 + break; 2794 2794 + case RPMB_WRITE_DATA: 2795 2795 + if (req_len % sizeof(struct rpmb_frame) || 2796 2796 + resp_len != sizeof(struct rpmb_frame)) 2797 2797 + return -EINVAL; 2798 2798 + write = true; 2799 2799 + break; 2800 2800 + case RPMB_READ_DATA: 2801 2801 + if (req_len != sizeof(struct rpmb_frame) || 2802 2802 + resp_len % sizeof(struct rpmb_frame)) 2803 2803 + return -EINVAL; 2804 2804 + write = false; 2805 2805 + break; 2806 2806 + default: 2807 2807 + return -EINVAL; 2808 2808 + } 2809 2809 + 2810 2810 + if (write) 2811 2811 + cmd_count = 3; 2812 2812 + else 2813 2813 + cmd_count = 2; 2814 2814 + 2815 2815 + idata = alloc_idata(rpmb, cmd_count); 2816 2816 + if (!idata) 2817 2817 + return -ENOMEM; 2818 2818 + 2819 2819 + if (write) { 2820 2820 + struct rpmb_frame *frm = (struct rpmb_frame *)resp; 2821 2821 + 2822 2822 + /* Send write request frame(s) */ 2823 2823 + set_idata(idata[0], MMC_WRITE_MULTIPLE_BLOCK, 2824 2824 + 1 | MMC_CMD23_ARG_REL_WR, req, req_len); 2825 2825 + 2826 2826 + /* Send result request frame */ 2827 2827 + memset(frm, 0, sizeof(*frm)); 2828 2828 + frm->req_resp = cpu_to_be16(RPMB_RESULT_READ); 2829 2829 + set_idata(idata[1], MMC_WRITE_MULTIPLE_BLOCK, 1, resp, 2830 2830 + resp_len); 2831 2831 + 2832 2832 + /* Read response frame */ 2833 2833 + set_idata(idata[2], MMC_READ_MULTIPLE_BLOCK, 0, resp, resp_len); 2834 2834 + } else { 2835 2835 + /* Send write request frame(s) */ 2836 2836 + set_idata(idata[0], MMC_WRITE_MULTIPLE_BLOCK, 1, req, req_len); 2837 2837 + 2838 2838 + /* Read response frame */ 2839 2839 + set_idata(idata[1], MMC_READ_MULTIPLE_BLOCK, 0, resp, resp_len); 2840 2840 + } 2841 2841 + 2842 2842 + rq = blk_mq_alloc_request(md->queue.queue, REQ_OP_DRV_OUT, 0); 2843 2843 + if (IS_ERR(rq)) { 2844 2844 + ret = PTR_ERR(rq); 2845 2845 + goto out; 2846 2846 + } 2847 2847 + 2848 2848 + mq_rq = req_to_mmc_queue_req(rq); 2849 2849 + mq_rq->drv_op = MMC_DRV_OP_IOCTL_RPMB; 2850 2850 + mq_rq->drv_op_result = -EIO; 2851 2851 + mq_rq->drv_op_data = idata; 2852 2852 + mq_rq->ioc_count = cmd_count; 2853 2853 + blk_execute_rq(rq, false); 2854 2854 + ret = req_to_mmc_queue_req(rq)->drv_op_result; 2855 2855 + 2856 2856 + blk_mq_free_request(rq); 2857 2857 + 2858 2858 + out: 2859 2859 + free_idata(idata, cmd_count); 2860 2860 + return ret; 2750 2861 } 2751 2862 2752 2863 static int mmc_blk_alloc_rpmb_part(struct mmc_card *card, ··· 2938 2739 rpmb->dev.release = mmc_blk_rpmb_device_release; 2939 2740 device_initialize(&rpmb->dev); 2940 2741 dev_set_drvdata(&rpmb->dev, rpmb); 2742 2742 + mmc_blk_get(md->disk); 2941 2743 rpmb->md = md; 2942 2744 2943 2745 cdev_init(&rpmb->chrdev, &mmc_rpmb_fileops); ··· 3200 3000 3201 3001 #endif /* CONFIG_DEBUG_FS */ 3202 3002 3003 3003 + static void mmc_blk_rpmb_add(struct mmc_card *card) 3004 3004 + { 3005 3005 + struct mmc_blk_data *md = dev_get_drvdata(&card->dev); 3006 3006 + struct mmc_rpmb_data *rpmb; 3007 3007 + struct rpmb_dev *rdev; 3008 3008 + unsigned int n; 3009 3009 + u32 cid[4]; 3010 3010 + struct rpmb_descr descr = { 3011 3011 + .type = RPMB_TYPE_EMMC, 3012 3012 + .route_frames = mmc_route_rpmb_frames, 3013 3013 + .reliable_wr_count = card->ext_csd.enhanced_rpmb_supported ? 3014 3014 + 2 : 32, 3015 3015 + .capacity = card->ext_csd.raw_rpmb_size_mult, 3016 3016 + .dev_id = (void *)cid, 3017 3017 + .dev_id_len = sizeof(cid), 3018 3018 + }; 3019 3019 + 3020 3020 + /* 3021 3021 + * Provice CID as an octet array. The CID needs to be interpreted 3022 3022 + * when used as input to derive the RPMB key since some fields 3023 3023 + * will change due to firmware updates. 3024 3024 + */ 3025 3025 + for (n = 0; n < 4; n++) 3026 3026 + cid[n] = be32_to_cpu((__force __be32)card->raw_cid[n]); 3027 3027 + 3028 3028 + list_for_each_entry(rpmb, &md->rpmbs, node) { 3029 3029 + rdev = rpmb_dev_register(&rpmb->dev, &descr); 3030 3030 + if (IS_ERR(rdev)) { 3031 3031 + pr_warn("%s: could not register RPMB device\n", 3032 3032 + dev_name(&rpmb->dev)); 3033 3033 + continue; 3034 3034 + } 3035 3035 + rpmb->rdev = rdev; 3036 3036 + } 3037 3037 + } 3038 3038 + 3203 3039 static int mmc_blk_probe(struct mmc_card *card) 3204 3040 { 3205 3041 struct mmc_blk_data *md; ··· 3280 3044 pm_runtime_set_active(&card->dev); 3281 3045 pm_runtime_enable(&card->dev); 3282 3046 } 3047 3047 + 3048 3048 + mmc_blk_rpmb_add(card); 3283 3049 3284 3050 return 0; 3285 3051

+46 -60

drivers/mmc/core/mmc.c

reviewed

··· 51 51 35, 40, 45, 50, 55, 60, 70, 80, 52 52 }; 53 53 54 54 - #define UNSTUFF_BITS(resp,start,size) \ 55 55 - ({ \ 56 56 - const int __size = size; \ 57 57 - const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ 58 58 - const int __off = 3 - ((start) / 32); \ 59 59 - const int __shft = (start) & 31; \ 60 60 - u32 __res; \ 61 61 - \ 62 62 - __res = resp[__off] >> __shft; \ 63 63 - if (__size + __shft > 32) \ 64 64 - __res |= resp[__off-1] << ((32 - __shft) % 32); \ 65 65 - __res & __mask; \ 66 66 - }) 67 67 - 68 54 /* 69 55 * Given the decoded CSD structure, decode the raw CID to our CID structure. 70 56 */ ··· 71 85 switch (card->csd.mmca_vsn) { 72 86 case 0: /* MMC v1.0 - v1.2 */ 73 87 case 1: /* MMC v1.4 */ 74 74 - card->cid.manfid = UNSTUFF_BITS(resp, 104, 24); 75 75 - card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8); 76 76 - card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8); 77 77 - card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8); 78 78 - card->cid.prod_name[3] = UNSTUFF_BITS(resp, 72, 8); 79 79 - card->cid.prod_name[4] = UNSTUFF_BITS(resp, 64, 8); 80 80 - card->cid.prod_name[5] = UNSTUFF_BITS(resp, 56, 8); 81 81 - card->cid.prod_name[6] = UNSTUFF_BITS(resp, 48, 8); 82 82 - card->cid.hwrev = UNSTUFF_BITS(resp, 44, 4); 83 83 - card->cid.fwrev = UNSTUFF_BITS(resp, 40, 4); 84 84 - card->cid.serial = UNSTUFF_BITS(resp, 16, 24); 85 85 - card->cid.month = UNSTUFF_BITS(resp, 12, 4); 86 86 - card->cid.year = UNSTUFF_BITS(resp, 8, 4) + 1997; 88 88 + card->cid.manfid = unstuff_bits(resp, 104, 24); 89 89 + card->cid.prod_name[0] = unstuff_bits(resp, 96, 8); 90 90 + card->cid.prod_name[1] = unstuff_bits(resp, 88, 8); 91 91 + card->cid.prod_name[2] = unstuff_bits(resp, 80, 8); 92 92 + card->cid.prod_name[3] = unstuff_bits(resp, 72, 8); 93 93 + card->cid.prod_name[4] = unstuff_bits(resp, 64, 8); 94 94 + card->cid.prod_name[5] = unstuff_bits(resp, 56, 8); 95 95 + card->cid.prod_name[6] = unstuff_bits(resp, 48, 8); 96 96 + card->cid.hwrev = unstuff_bits(resp, 44, 4); 97 97 + card->cid.fwrev = unstuff_bits(resp, 40, 4); 98 98 + card->cid.serial = unstuff_bits(resp, 16, 24); 99 99 + card->cid.month = unstuff_bits(resp, 12, 4); 100 100 + card->cid.year = unstuff_bits(resp, 8, 4) + 1997; 87 101 break; 88 102 89 103 case 2: /* MMC v2.0 - v2.2 */ 90 104 case 3: /* MMC v3.1 - v3.3 */ 91 105 case 4: /* MMC v4 */ 92 92 - card->cid.manfid = UNSTUFF_BITS(resp, 120, 8); 93 93 - card->cid.oemid = UNSTUFF_BITS(resp, 104, 16); 94 94 - card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8); 95 95 - card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8); 96 96 - card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8); 97 97 - card->cid.prod_name[3] = UNSTUFF_BITS(resp, 72, 8); 98 98 - card->cid.prod_name[4] = UNSTUFF_BITS(resp, 64, 8); 99 99 - card->cid.prod_name[5] = UNSTUFF_BITS(resp, 56, 8); 100 100 - card->cid.prv = UNSTUFF_BITS(resp, 48, 8); 101 101 - card->cid.serial = UNSTUFF_BITS(resp, 16, 32); 102 102 - card->cid.month = UNSTUFF_BITS(resp, 12, 4); 103 103 - card->cid.year = UNSTUFF_BITS(resp, 8, 4) + 1997; 106 106 + card->cid.manfid = unstuff_bits(resp, 120, 8); 107 107 + card->cid.oemid = unstuff_bits(resp, 104, 16); 108 108 + card->cid.prod_name[0] = unstuff_bits(resp, 96, 8); 109 109 + card->cid.prod_name[1] = unstuff_bits(resp, 88, 8); 110 110 + card->cid.prod_name[2] = unstuff_bits(resp, 80, 8); 111 111 + card->cid.prod_name[3] = unstuff_bits(resp, 72, 8); 112 112 + card->cid.prod_name[4] = unstuff_bits(resp, 64, 8); 113 113 + card->cid.prod_name[5] = unstuff_bits(resp, 56, 8); 114 114 + card->cid.prv = unstuff_bits(resp, 48, 8); 115 115 + card->cid.serial = unstuff_bits(resp, 16, 32); 116 116 + card->cid.month = unstuff_bits(resp, 12, 4); 117 117 + card->cid.year = unstuff_bits(resp, 8, 4) + 1997; 104 118 break; 105 119 106 120 default: ··· 147 161 * v1.2 has extra information in bits 15, 11 and 10. 148 162 * We also support eMMC v4.4 & v4.41. 149 163 */ 150 150 - csd->structure = UNSTUFF_BITS(resp, 126, 2); 164 164 + csd->structure = unstuff_bits(resp, 126, 2); 151 165 if (csd->structure == 0) { 152 166 pr_err("%s: unrecognised CSD structure version %d\n", 153 167 mmc_hostname(card->host), csd->structure); 154 168 return -EINVAL; 155 169 } 156 170 157 157 - csd->mmca_vsn = UNSTUFF_BITS(resp, 122, 4); 158 158 - m = UNSTUFF_BITS(resp, 115, 4); 159 159 - e = UNSTUFF_BITS(resp, 112, 3); 171 171 + csd->mmca_vsn = unstuff_bits(resp, 122, 4); 172 172 + m = unstuff_bits(resp, 115, 4); 173 173 + e = unstuff_bits(resp, 112, 3); 160 174 csd->taac_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; 161 161 - csd->taac_clks = UNSTUFF_BITS(resp, 104, 8) * 100; 175 175 + csd->taac_clks = unstuff_bits(resp, 104, 8) * 100; 162 176 163 163 - m = UNSTUFF_BITS(resp, 99, 4); 164 164 - e = UNSTUFF_BITS(resp, 96, 3); 177 177 + m = unstuff_bits(resp, 99, 4); 178 178 + e = unstuff_bits(resp, 96, 3); 165 179 csd->max_dtr = tran_exp[e] * tran_mant[m]; 166 166 - csd->cmdclass = UNSTUFF_BITS(resp, 84, 12); 180 180 + csd->cmdclass = unstuff_bits(resp, 84, 12); 167 181 168 168 - e = UNSTUFF_BITS(resp, 47, 3); 169 169 - m = UNSTUFF_BITS(resp, 62, 12); 182 182 + e = unstuff_bits(resp, 47, 3); 183 183 + m = unstuff_bits(resp, 62, 12); 170 184 csd->capacity = (1 + m) << (e + 2); 171 185 172 172 - csd->read_blkbits = UNSTUFF_BITS(resp, 80, 4); 173 173 - csd->read_partial = UNSTUFF_BITS(resp, 79, 1); 174 174 - csd->write_misalign = UNSTUFF_BITS(resp, 78, 1); 175 175 - csd->read_misalign = UNSTUFF_BITS(resp, 77, 1); 176 176 - csd->dsr_imp = UNSTUFF_BITS(resp, 76, 1); 177 177 - csd->r2w_factor = UNSTUFF_BITS(resp, 26, 3); 178 178 - csd->write_blkbits = UNSTUFF_BITS(resp, 22, 4); 179 179 - csd->write_partial = UNSTUFF_BITS(resp, 21, 1); 186 186 + csd->read_blkbits = unstuff_bits(resp, 80, 4); 187 187 + csd->read_partial = unstuff_bits(resp, 79, 1); 188 188 + csd->write_misalign = unstuff_bits(resp, 78, 1); 189 189 + csd->read_misalign = unstuff_bits(resp, 77, 1); 190 190 + csd->dsr_imp = unstuff_bits(resp, 76, 1); 191 191 + csd->r2w_factor = unstuff_bits(resp, 26, 3); 192 192 + csd->write_blkbits = unstuff_bits(resp, 22, 4); 193 193 + csd->write_partial = unstuff_bits(resp, 21, 1); 180 194 181 195 if (csd->write_blkbits >= 9) { 182 182 - a = UNSTUFF_BITS(resp, 42, 5); 183 183 - b = UNSTUFF_BITS(resp, 37, 5); 196 196 + a = unstuff_bits(resp, 42, 5); 197 197 + b = unstuff_bits(resp, 37, 5); 184 198 csd->erase_size = (a + 1) * (b + 1); 185 199 csd->erase_size <<= csd->write_blkbits - 9; 186 186 - csd->wp_grp_size = UNSTUFF_BITS(resp, 32, 5); 200 200 + csd->wp_grp_size = unstuff_bits(resp, 32, 5); 187 201 } 188 202 189 203 return 0;

+14

drivers/mmc/core/mmc_ops.h

reviewed

··· 56 56 int mmc_cmdq_disable(struct mmc_card *card); 57 57 int mmc_sanitize(struct mmc_card *card, unsigned int timeout_ms); 58 58 59 59 + static inline u32 unstuff_bits(const u32 *resp, int start, int size) 60 60 + { 61 61 + const int __size = size; 62 62 + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; 63 63 + const int __off = 3 - (start / 32); 64 64 + const int __shft = start & 31; 65 65 + u32 __res = resp[__off] >> __shft; 66 66 + 67 67 + if (__size + __shft > 32) 68 68 + __res |= resp[__off - 1] << ((32 - __shft) % 32); 69 69 + 70 70 + return __res & __mask; 71 71 + } 72 72 + 59 73 #endif 60 74

+6 -2

drivers/mmc/core/regulator.c

reviewed

··· 255 255 256 256 if (IS_ERR(mmc->supply.vmmc)) { 257 257 if (PTR_ERR(mmc->supply.vmmc) == -EPROBE_DEFER) 258 258 - return -EPROBE_DEFER; 258 258 + return dev_err_probe(dev, -EPROBE_DEFER, 259 259 + "vmmc regulator not available\n"); 260 260 + 259 261 dev_dbg(dev, "No vmmc regulator found\n"); 260 262 } else { 261 263 ret = mmc_regulator_get_ocrmask(mmc->supply.vmmc); ··· 269 267 270 268 if (IS_ERR(mmc->supply.vqmmc)) { 271 269 if (PTR_ERR(mmc->supply.vqmmc) == -EPROBE_DEFER) 272 272 - return -EPROBE_DEFER; 270 270 + return dev_err_probe(dev, -EPROBE_DEFER, 271 271 + "vqmmc regulator not available\n"); 272 272 + 273 273 dev_dbg(dev, "No vqmmc regulator found\n"); 274 274 } 275 275

+61 -72

drivers/mmc/core/sd.c

reviewed

··· 56 56 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512, 57 57 }; 58 58 59 59 - #define UNSTUFF_BITS(resp,start,size) \ 60 60 - ({ \ 61 61 - const int __size = size; \ 62 62 - const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ 63 63 - const int __off = 3 - ((start) / 32); \ 64 64 - const int __shft = (start) & 31; \ 65 65 - u32 __res; \ 66 66 - \ 67 67 - __res = resp[__off] >> __shft; \ 68 68 - if (__size + __shft > 32) \ 69 69 - __res |= resp[__off-1] << ((32 - __shft) % 32); \ 70 70 - __res & __mask; \ 71 71 - }) 72 72 - 73 59 #define SD_POWEROFF_NOTIFY_TIMEOUT_MS 1000 74 60 #define SD_WRITE_EXTR_SINGLE_TIMEOUT_MS 1000 75 61 ··· 81 95 * SD doesn't currently have a version field so we will 82 96 * have to assume we can parse this. 83 97 */ 84 84 - card->cid.manfid = UNSTUFF_BITS(resp, 120, 8); 85 85 - card->cid.oemid = UNSTUFF_BITS(resp, 104, 16); 86 86 - card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8); 87 87 - card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8); 88 88 - card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8); 89 89 - card->cid.prod_name[3] = UNSTUFF_BITS(resp, 72, 8); 90 90 - card->cid.prod_name[4] = UNSTUFF_BITS(resp, 64, 8); 91 91 - card->cid.hwrev = UNSTUFF_BITS(resp, 60, 4); 92 92 - card->cid.fwrev = UNSTUFF_BITS(resp, 56, 4); 93 93 - card->cid.serial = UNSTUFF_BITS(resp, 24, 32); 94 94 - card->cid.year = UNSTUFF_BITS(resp, 12, 8); 95 95 - card->cid.month = UNSTUFF_BITS(resp, 8, 4); 98 98 + card->cid.manfid = unstuff_bits(resp, 120, 8); 99 99 + card->cid.oemid = unstuff_bits(resp, 104, 16); 100 100 + card->cid.prod_name[0] = unstuff_bits(resp, 96, 8); 101 101 + card->cid.prod_name[1] = unstuff_bits(resp, 88, 8); 102 102 + card->cid.prod_name[2] = unstuff_bits(resp, 80, 8); 103 103 + card->cid.prod_name[3] = unstuff_bits(resp, 72, 8); 104 104 + card->cid.prod_name[4] = unstuff_bits(resp, 64, 8); 105 105 + card->cid.hwrev = unstuff_bits(resp, 60, 4); 106 106 + card->cid.fwrev = unstuff_bits(resp, 56, 4); 107 107 + card->cid.serial = unstuff_bits(resp, 24, 32); 108 108 + card->cid.year = unstuff_bits(resp, 12, 8); 109 109 + card->cid.month = unstuff_bits(resp, 8, 4); 96 110 97 111 card->cid.year += 2000; /* SD cards year offset */ 98 112 } ··· 106 120 unsigned int e, m, csd_struct; 107 121 u32 *resp = card->raw_csd; 108 122 109 109 - csd_struct = UNSTUFF_BITS(resp, 126, 2); 123 123 + csd_struct = unstuff_bits(resp, 126, 2); 110 124 111 125 switch (csd_struct) { 112 126 case 0: 113 113 - m = UNSTUFF_BITS(resp, 115, 4); 114 114 - e = UNSTUFF_BITS(resp, 112, 3); 127 127 + m = unstuff_bits(resp, 115, 4); 128 128 + e = unstuff_bits(resp, 112, 3); 115 129 csd->taac_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; 116 116 - csd->taac_clks = UNSTUFF_BITS(resp, 104, 8) * 100; 130 130 + csd->taac_clks = unstuff_bits(resp, 104, 8) * 100; 117 131 118 118 - m = UNSTUFF_BITS(resp, 99, 4); 119 119 - e = UNSTUFF_BITS(resp, 96, 3); 132 132 + m = unstuff_bits(resp, 99, 4); 133 133 + e = unstuff_bits(resp, 96, 3); 120 134 csd->max_dtr = tran_exp[e] * tran_mant[m]; 121 121 - csd->cmdclass = UNSTUFF_BITS(resp, 84, 12); 135 135 + csd->cmdclass = unstuff_bits(resp, 84, 12); 122 136 123 123 - e = UNSTUFF_BITS(resp, 47, 3); 124 124 - m = UNSTUFF_BITS(resp, 62, 12); 137 137 + e = unstuff_bits(resp, 47, 3); 138 138 + m = unstuff_bits(resp, 62, 12); 125 139 csd->capacity = (1 + m) << (e + 2); 126 140 127 127 - csd->read_blkbits = UNSTUFF_BITS(resp, 80, 4); 128 128 - csd->read_partial = UNSTUFF_BITS(resp, 79, 1); 129 129 - csd->write_misalign = UNSTUFF_BITS(resp, 78, 1); 130 130 - csd->read_misalign = UNSTUFF_BITS(resp, 77, 1); 131 131 - csd->dsr_imp = UNSTUFF_BITS(resp, 76, 1); 132 132 - csd->r2w_factor = UNSTUFF_BITS(resp, 26, 3); 133 133 - csd->write_blkbits = UNSTUFF_BITS(resp, 22, 4); 134 134 - csd->write_partial = UNSTUFF_BITS(resp, 21, 1); 141 141 + csd->read_blkbits = unstuff_bits(resp, 80, 4); 142 142 + csd->read_partial = unstuff_bits(resp, 79, 1); 143 143 + csd->write_misalign = unstuff_bits(resp, 78, 1); 144 144 + csd->read_misalign = unstuff_bits(resp, 77, 1); 145 145 + csd->dsr_imp = unstuff_bits(resp, 76, 1); 146 146 + csd->r2w_factor = unstuff_bits(resp, 26, 3); 147 147 + csd->write_blkbits = unstuff_bits(resp, 22, 4); 148 148 + csd->write_partial = unstuff_bits(resp, 21, 1); 135 149 136 136 - if (UNSTUFF_BITS(resp, 46, 1)) { 150 150 + if (unstuff_bits(resp, 46, 1)) { 137 151 csd->erase_size = 1; 138 152 } else if (csd->write_blkbits >= 9) { 139 139 - csd->erase_size = UNSTUFF_BITS(resp, 39, 7) + 1; 153 153 + csd->erase_size = unstuff_bits(resp, 39, 7) + 1; 140 154 csd->erase_size <<= csd->write_blkbits - 9; 141 155 } 142 156 143 143 - if (UNSTUFF_BITS(resp, 13, 1)) 157 157 + if (unstuff_bits(resp, 13, 1)) 144 158 mmc_card_set_readonly(card); 145 159 break; 146 160 case 1: ··· 155 169 csd->taac_ns = 0; /* Unused */ 156 170 csd->taac_clks = 0; /* Unused */ 157 171 158 158 - m = UNSTUFF_BITS(resp, 99, 4); 159 159 - e = UNSTUFF_BITS(resp, 96, 3); 172 172 + m = unstuff_bits(resp, 99, 4); 173 173 + e = unstuff_bits(resp, 96, 3); 160 174 csd->max_dtr = tran_exp[e] * tran_mant[m]; 161 161 - csd->cmdclass = UNSTUFF_BITS(resp, 84, 12); 162 162 - csd->c_size = UNSTUFF_BITS(resp, 48, 22); 175 175 + csd->cmdclass = unstuff_bits(resp, 84, 12); 176 176 + csd->c_size = unstuff_bits(resp, 48, 22); 163 177 164 178 /* SDXC cards have a minimum C_SIZE of 0x00FFFF */ 165 179 if (csd->c_size >= 0xFFFF) 166 180 mmc_card_set_ext_capacity(card); 167 181 168 168 - m = UNSTUFF_BITS(resp, 48, 22); 182 182 + m = unstuff_bits(resp, 48, 22); 169 183 csd->capacity = (1 + m) << 10; 170 184 171 185 csd->read_blkbits = 9; ··· 177 191 csd->write_partial = 0; 178 192 csd->erase_size = 1; 179 193 180 180 - if (UNSTUFF_BITS(resp, 13, 1)) 194 194 + if (unstuff_bits(resp, 13, 1)) 181 195 mmc_card_set_readonly(card); 182 196 break; 183 197 default: ··· 203 217 resp[3] = card->raw_scr[1]; 204 218 resp[2] = card->raw_scr[0]; 205 219 206 206 - scr_struct = UNSTUFF_BITS(resp, 60, 4); 220 220 + scr_struct = unstuff_bits(resp, 60, 4); 207 221 if (scr_struct != 0) { 208 222 pr_err("%s: unrecognised SCR structure version %d\n", 209 223 mmc_hostname(card->host), scr_struct); 210 224 return -EINVAL; 211 225 } 212 226 213 213 - scr->sda_vsn = UNSTUFF_BITS(resp, 56, 4); 214 214 - scr->bus_widths = UNSTUFF_BITS(resp, 48, 4); 227 227 + scr->sda_vsn = unstuff_bits(resp, 56, 4); 228 228 + scr->bus_widths = unstuff_bits(resp, 48, 4); 215 229 if (scr->sda_vsn == SCR_SPEC_VER_2) 216 230 /* Check if Physical Layer Spec v3.0 is supported */ 217 217 - scr->sda_spec3 = UNSTUFF_BITS(resp, 47, 1); 231 231 + scr->sda_spec3 = unstuff_bits(resp, 47, 1); 218 232 219 233 if (scr->sda_spec3) { 220 220 - scr->sda_spec4 = UNSTUFF_BITS(resp, 42, 1); 221 221 - scr->sda_specx = UNSTUFF_BITS(resp, 38, 4); 234 234 + scr->sda_spec4 = unstuff_bits(resp, 42, 1); 235 235 + scr->sda_specx = unstuff_bits(resp, 38, 4); 222 236 } 223 237 224 224 - if (UNSTUFF_BITS(resp, 55, 1)) 238 238 + if (unstuff_bits(resp, 55, 1)) 225 239 card->erased_byte = 0xFF; 226 240 else 227 241 card->erased_byte = 0x0; 228 242 229 243 if (scr->sda_spec4) 230 230 - scr->cmds = UNSTUFF_BITS(resp, 32, 4); 244 244 + scr->cmds = unstuff_bits(resp, 32, 4); 231 245 else if (scr->sda_spec3) 232 232 - scr->cmds = UNSTUFF_BITS(resp, 32, 2); 246 246 + scr->cmds = unstuff_bits(resp, 32, 2); 233 247 234 248 /* SD Spec says: any SD Card shall set at least bits 0 and 2 */ 235 249 if (!(scr->bus_widths & SD_SCR_BUS_WIDTH_1) || ··· 275 289 kfree(raw_ssr); 276 290 277 291 /* 278 278 - * UNSTUFF_BITS only works with four u32s so we have to offset the 292 292 + * unstuff_bits only works with four u32s so we have to offset the 279 293 * bitfield positions accordingly. 280 294 */ 281 281 - au = UNSTUFF_BITS(card->raw_ssr, 428 - 384, 4); 295 295 + au = unstuff_bits(card->raw_ssr, 428 - 384, 4); 282 296 if (au) { 283 297 if (au <= 9 || card->scr.sda_spec3) { 284 298 card->ssr.au = sd_au_size[au]; 285 285 - es = UNSTUFF_BITS(card->raw_ssr, 408 - 384, 16); 286 286 - et = UNSTUFF_BITS(card->raw_ssr, 402 - 384, 6); 299 299 + es = unstuff_bits(card->raw_ssr, 408 - 384, 16); 300 300 + et = unstuff_bits(card->raw_ssr, 402 - 384, 6); 287 301 if (es && et) { 288 288 - eo = UNSTUFF_BITS(card->raw_ssr, 400 - 384, 2); 302 302 + eo = unstuff_bits(card->raw_ssr, 400 - 384, 2); 289 303 card->ssr.erase_timeout = (et * 1000) / es; 290 304 card->ssr.erase_offset = eo * 1000; 291 305 } ··· 299 313 * starting SD5.1 discard is supported if DISCARD_SUPPORT (b313) is set 300 314 */ 301 315 resp[3] = card->raw_ssr[6]; 302 302 - discard_support = UNSTUFF_BITS(resp, 313 - 288, 1); 316 316 + discard_support = unstuff_bits(resp, 313 - 288, 1); 303 317 card->erase_arg = (card->scr.sda_specx && discard_support) ? 304 318 SD_DISCARD_ARG : SD_ERASE_ARG; 305 319 ··· 332 346 * The argument does not matter, as the support bits do not 333 347 * change with the arguments. 334 348 */ 335 335 - err = mmc_sd_switch(card, 0, 0, 0, status); 349 349 + err = mmc_sd_switch(card, SD_SWITCH_CHECK, 0, 0, status); 336 350 if (err) { 337 351 /* 338 352 * If the host or the card can't do the switch, ··· 388 402 if (!status) 389 403 return -ENOMEM; 390 404 391 391 - err = mmc_sd_switch(card, 1, 0, HIGH_SPEED_BUS_SPEED, status); 405 405 + err = mmc_sd_switch(card, SD_SWITCH_SET, 0, 406 406 + HIGH_SPEED_BUS_SPEED, status); 392 407 if (err) 393 408 goto out; 394 409 ··· 421 434 card_drv_type, &drv_type); 422 435 423 436 if (drive_strength) { 424 424 - err = mmc_sd_switch(card, 1, 2, drive_strength, status); 437 437 + err = mmc_sd_switch(card, SD_SWITCH_SET, 2, 438 438 + drive_strength, status); 425 439 if (err) 426 440 return err; 427 441 if ((status[15] & 0xF) != drive_strength) { ··· 502 514 return 0; 503 515 } 504 516 505 505 - err = mmc_sd_switch(card, 1, 0, card->sd_bus_speed, status); 517 517 + err = mmc_sd_switch(card, SD_SWITCH_SET, 0, card->sd_bus_speed, status); 506 518 if (err) 507 519 return err; 508 520 ··· 593 605 current_limit = SD_SET_CURRENT_LIMIT_200; 594 606 595 607 if (current_limit != SD_SET_CURRENT_NO_CHANGE) { 596 596 - err = mmc_sd_switch(card, 1, 3, current_limit, status); 608 608 + err = mmc_sd_switch(card, SD_SWITCH_SET, 3, 609 609 + current_limit, status); 597 610 if (err) 598 611 return err; 599 612

+1 -2

drivers/mmc/core/sd_ops.c

reviewed

··· 336 336 return 0; 337 337 } 338 338 339 339 - int mmc_sd_switch(struct mmc_card *card, int mode, int group, 339 339 + int mmc_sd_switch(struct mmc_card *card, bool mode, int group, 340 340 u8 value, u8 *resp) 341 341 { 342 342 u32 cmd_args; 343 343 344 344 /* NOTE: caller guarantees resp is heap-allocated */ 345 345 346 346 - mode = !!mode; 347 346 value &= 0xF; 348 347 cmd_args = mode << 31 | 0x00FFFFFF; 349 348 cmd_args &= ~(0xF << (group * 4));

+12

drivers/mmc/host/Kconfig

reviewed

··· 252 252 253 253 If unsure, say N. 254 254 255 255 + config MMC_SDHCI_OF_MA35D1 256 256 + tristate "SDHCI OF support for the MA35D1 SDHCI controller" 257 257 + depends on ARCH_MA35 || COMPILE_TEST 258 258 + depends on MMC_SDHCI_PLTFM 259 259 + help 260 260 + This selects the MA35D1 Secure Digital Host Controller Interface. 261 261 + The controller supports SD/MMC/SDIO devices. 262 262 + 263 263 + If you have a controller with this interface, say Y or M here. 264 264 + 265 265 + If unsure, say N. 266 266 + 255 267 config MMC_SDHCI_CADENCE 256 268 tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" 257 269 depends on MMC_SDHCI_PLTFM

+1

drivers/mmc/host/Makefile

reviewed

··· 88 88 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o 89 89 obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o 90 90 obj-$(CONFIG_MMC_SDHCI_OF_SPARX5) += sdhci-of-sparx5.o 91 91 + obj-$(CONFIG_MMC_SDHCI_OF_MA35D1) += sdhci-of-ma35d1.o 91 92 obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o 92 93 obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o 93 94 obj-$(CONFIG_MMC_SDHCI_NPCM) += sdhci-npcm.o

+7 -7

drivers/mmc/host/cqhci-core.c

reviewed

··· 33 33 #define CQHCI_HOST_OTHER BIT(4) 34 34 }; 35 35 36 36 + static bool cqhci_halted(struct cqhci_host *cq_host) 37 37 + { 38 38 + return cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT; 39 39 + } 40 40 + 36 41 static inline u8 *get_desc(struct cqhci_host *cq_host, u8 tag) 37 42 { 38 43 return cq_host->desc_base + (tag * cq_host->slot_sz); ··· 287 282 288 283 cqhci_writel(cq_host, cqcfg, CQHCI_CFG); 289 284 290 290 - if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) 285 285 + if (cqhci_halted(cq_host)) 291 286 cqhci_writel(cq_host, 0, CQHCI_CTL); 292 287 293 288 mmc->cqe_on = true; ··· 622 617 cqhci_writel(cq_host, 0, CQHCI_CTL); 623 618 mmc->cqe_on = true; 624 619 pr_debug("%s: cqhci: CQE on\n", mmc_hostname(mmc)); 625 625 - if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { 620 620 + if (cqhci_halted(cq_host)) { 626 621 pr_err("%s: cqhci: CQE failed to exit halt state\n", 627 622 mmc_hostname(mmc)); 628 623 } ··· 956 951 mmc_hostname(mmc)); 957 952 958 953 return ret; 959 959 - } 960 960 - 961 961 - static bool cqhci_halted(struct cqhci_host *cq_host) 962 962 - { 963 963 - return cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT; 964 954 } 965 955 966 956 static bool cqhci_halt(struct mmc_host *mmc, unsigned int timeout)

+202 -15

drivers/mmc/host/dw_mmc-rockchip.c

reviewed

··· 15 15 #include "dw_mmc.h" 16 16 #include "dw_mmc-pltfm.h" 17 17 18 18 - #define RK3288_CLKGEN_DIV 2 18 18 + #define RK3288_CLKGEN_DIV 2 19 19 + #define SDMMC_TIMING_CON0 0x130 20 20 + #define SDMMC_TIMING_CON1 0x134 21 21 + #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 22 22 + #define ROCKCHIP_MMC_DEGREE_MASK 0x3 23 23 + #define ROCKCHIP_MMC_DEGREE_OFFSET 1 24 24 + #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 25 25 + #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 26 26 + #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 27 27 + #define HIWORD_UPDATE(val, mask, shift) \ 28 28 + ((val) << (shift) | (mask) << ((shift) + 16)) 19 29 20 30 static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; 21 31 ··· 34 24 struct clk *sample_clk; 35 25 int default_sample_phase; 36 26 int num_phases; 27 27 + bool internal_phase; 37 28 }; 29 29 + 30 30 + /* 31 31 + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 32 32 + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 33 33 + */ 34 34 + static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample) 35 35 + { 36 36 + unsigned long rate = clk_get_rate(host->ciu_clk); 37 37 + u32 raw_value; 38 38 + u16 degrees; 39 39 + u32 delay_num = 0; 40 40 + 41 41 + /* Constant signal, no measurable phase shift */ 42 42 + if (!rate) 43 43 + return 0; 44 44 + 45 45 + if (sample) 46 46 + raw_value = mci_readl(host, TIMING_CON1); 47 47 + else 48 48 + raw_value = mci_readl(host, TIMING_CON0); 49 49 + 50 50 + raw_value >>= ROCKCHIP_MMC_DEGREE_OFFSET; 51 51 + degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 52 52 + 53 53 + if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 54 54 + /* degrees/delaynum * 1000000 */ 55 55 + unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 56 56 + 36 * (rate / 10000); 57 57 + 58 58 + delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 59 59 + delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 60 60 + degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); 61 61 + } 62 62 + 63 63 + return degrees % 360; 64 64 + } 65 65 + 66 66 + static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) 67 67 + { 68 68 + struct dw_mci_rockchip_priv_data *priv = host->priv; 69 69 + struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; 70 70 + 71 71 + if (priv->internal_phase) 72 72 + return rockchip_mmc_get_internal_phase(host, sample); 73 73 + else 74 74 + return clk_get_phase(clock); 75 75 + } 76 76 + 77 77 + static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees) 78 78 + { 79 79 + unsigned long rate = clk_get_rate(host->ciu_clk); 80 80 + u8 nineties, remainder; 81 81 + u8 delay_num; 82 82 + u32 raw_value; 83 83 + u32 delay; 84 84 + 85 85 + /* 86 86 + * The below calculation is based on the output clock from 87 87 + * MMC host to the card, which expects the phase clock inherits 88 88 + * the clock rate from its parent, namely the output clock 89 89 + * provider of MMC host. However, things may go wrong if 90 90 + * (1) It is orphan. 91 91 + * (2) It is assigned to the wrong parent. 92 92 + * 93 93 + * This check help debug the case (1), which seems to be the 94 94 + * most likely problem we often face and which makes it difficult 95 95 + * for people to debug unstable mmc tuning results. 96 96 + */ 97 97 + if (!rate) { 98 98 + dev_err(host->dev, "%s: invalid clk rate\n", __func__); 99 99 + return -EINVAL; 100 100 + } 101 101 + 102 102 + nineties = degrees / 90; 103 103 + remainder = (degrees % 90); 104 104 + 105 105 + /* 106 106 + * Due to the inexact nature of the "fine" delay, we might 107 107 + * actually go non-monotonic. We don't go _too_ monotonic 108 108 + * though, so we should be OK. Here are options of how we may 109 109 + * work: 110 110 + * 111 111 + * Ideally we end up with: 112 112 + * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 113 113 + * 114 114 + * On one extreme (if delay is actually 44ps): 115 115 + * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 116 116 + * The other (if delay is actually 77ps): 117 117 + * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 118 118 + * 119 119 + * It's possible we might make a delay that is up to 25 120 120 + * degrees off from what we think we're making. That's OK 121 121 + * though because we should be REALLY far from any bad range. 122 122 + */ 123 123 + 124 124 + /* 125 125 + * Convert to delay; do a little extra work to make sure we 126 126 + * don't overflow 32-bit / 64-bit numbers. 127 127 + */ 128 128 + delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 129 129 + delay *= remainder; 130 130 + delay = DIV_ROUND_CLOSEST(delay, 131 131 + (rate / 1000) * 36 * 132 132 + (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 133 133 + 134 134 + delay_num = (u8) min_t(u32, delay, 255); 135 135 + 136 136 + raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 137 137 + raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 138 138 + raw_value |= nineties; 139 139 + 140 140 + if (sample) 141 141 + mci_writel(host, TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); 142 142 + else 143 143 + mci_writel(host, TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); 144 144 + 145 145 + dev_dbg(host->dev, "set %s_phase(%d) delay_nums=%u actual_degrees=%d\n", 146 146 + sample ? "sample" : "drv", degrees, delay_num, 147 147 + rockchip_mmc_get_phase(host, sample) 148 148 + ); 149 149 + 150 150 + return 0; 151 151 + } 152 152 + 153 153 + static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees) 154 154 + { 155 155 + struct dw_mci_rockchip_priv_data *priv = host->priv; 156 156 + struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; 157 157 + 158 158 + if (priv->internal_phase) 159 159 + return rockchip_mmc_set_internal_phase(host, sample, degrees); 160 160 + else 161 161 + return clk_set_phase(clock, degrees); 162 162 + } 38 163 39 164 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) 40 165 { ··· 209 64 210 65 /* Make sure we use phases which we can enumerate with */ 211 66 if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS) 212 212 - clk_set_phase(priv->sample_clk, priv->default_sample_phase); 67 67 + rockchip_mmc_set_phase(host, true, priv->default_sample_phase); 213 68 214 69 /* 215 70 * Set the drive phase offset based on speed mode to achieve hold times. ··· 272 127 break; 273 128 } 274 129 275 275 - clk_set_phase(priv->drv_clk, phase); 130 130 + rockchip_mmc_set_phase(host, false, phase); 276 131 } 277 132 } 278 133 ··· 296 151 int longest_range_len = -1; 297 152 int longest_range = -1; 298 153 int middle_phase; 154 154 + int phase; 299 155 300 156 if (IS_ERR(priv->sample_clk)) { 301 157 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); ··· 310 164 311 165 /* Try each phase and extract good ranges */ 312 166 for (i = 0; i < priv->num_phases; ) { 313 313 - clk_set_phase(priv->sample_clk, 314 314 - TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); 167 167 + rockchip_mmc_set_phase(host, true, 168 168 + TUNING_ITERATION_TO_PHASE( 169 169 + i, 170 170 + priv->num_phases)); 315 171 316 172 v = !mmc_send_tuning(mmc, opcode, NULL); 317 173 ··· 359 211 } 360 212 361 213 if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { 362 362 - clk_set_phase(priv->sample_clk, priv->default_sample_phase); 214 214 + rockchip_mmc_set_phase(host, true, priv->default_sample_phase); 215 215 + 363 216 dev_info(host->dev, "All phases work, using default phase %d.", 364 217 priv->default_sample_phase); 365 218 goto free; ··· 397 248 398 249 middle_phase = ranges[longest_range].start + longest_range_len / 2; 399 250 middle_phase %= priv->num_phases; 400 400 - dev_info(host->dev, "Successfully tuned phase to %d\n", 401 401 - TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases)); 251 251 + phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases); 252 252 + dev_info(host->dev, "Successfully tuned phase to %d\n", phase); 402 253 403 403 - clk_set_phase(priv->sample_clk, 404 404 - TUNING_ITERATION_TO_PHASE(middle_phase, 405 405 - priv->num_phases)); 254 254 + rockchip_mmc_set_phase(host, true, phase); 406 255 407 256 free: 408 257 kfree(ranges); 409 258 return ret; 410 259 } 411 260 412 412 - static int dw_mci_rk3288_parse_dt(struct dw_mci *host) 261 261 + static int dw_mci_common_parse_dt(struct dw_mci *host) 413 262 { 414 263 struct device_node *np = host->dev->of_node; 415 264 struct dw_mci_rockchip_priv_data *priv; ··· 417 270 return -ENOMEM; 418 271 419 272 if (of_property_read_u32(np, "rockchip,desired-num-phases", 420 420 - &priv->num_phases)) 273 273 + &priv->num_phases)) 421 274 priv->num_phases = 360; 422 275 423 276 if (of_property_read_u32(np, "rockchip,default-sample-phase", 424 424 - &priv->default_sample_phase)) 277 277 + &priv->default_sample_phase)) 425 278 priv->default_sample_phase = 0; 279 279 + 280 280 + host->priv = priv; 281 281 + 282 282 + return 0; 283 283 + } 284 284 + 285 285 + static int dw_mci_rk3288_parse_dt(struct dw_mci *host) 286 286 + { 287 287 + struct dw_mci_rockchip_priv_data *priv; 288 288 + int err; 289 289 + 290 290 + err = dw_mci_common_parse_dt(host); 291 291 + if (err) 292 292 + return err; 293 293 + 294 294 + priv = host->priv; 426 295 427 296 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); 428 297 if (IS_ERR(priv->drv_clk)) ··· 448 285 if (IS_ERR(priv->sample_clk)) 449 286 dev_dbg(host->dev, "ciu-sample not available\n"); 450 287 451 451 - host->priv = priv; 288 288 + priv->internal_phase = false; 289 289 + 290 290 + return 0; 291 291 + } 292 292 + 293 293 + static int dw_mci_rk3576_parse_dt(struct dw_mci *host) 294 294 + { 295 295 + struct dw_mci_rockchip_priv_data *priv; 296 296 + int err = dw_mci_common_parse_dt(host); 297 297 + if (err) 298 298 + return err; 299 299 + 300 300 + priv = host->priv; 301 301 + 302 302 + priv->internal_phase = true; 452 303 453 304 return 0; 454 305 } ··· 508 331 .init = dw_mci_rockchip_init, 509 332 }; 510 333 334 334 + static const struct dw_mci_drv_data rk3576_drv_data = { 335 335 + .common_caps = MMC_CAP_CMD23, 336 336 + .set_ios = dw_mci_rk3288_set_ios, 337 337 + .execute_tuning = dw_mci_rk3288_execute_tuning, 338 338 + .parse_dt = dw_mci_rk3576_parse_dt, 339 339 + .init = dw_mci_rockchip_init, 340 340 + }; 341 341 + 511 342 static const struct of_device_id dw_mci_rockchip_match[] = { 512 343 { .compatible = "rockchip,rk2928-dw-mshc", 513 344 .data = &rk2928_drv_data }, 514 345 { .compatible = "rockchip,rk3288-dw-mshc", 515 346 .data = &rk3288_drv_data }, 347 347 + { .compatible = "rockchip,rk3576-dw-mshc", 348 348 + .data = &rk3576_drv_data }, 516 349 {}, 517 350 }; 518 351 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);

+5 -6

drivers/mmc/host/mtk-sd.c

reviewed

··· 795 795 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 796 796 { 797 797 struct mmc_host *mmc = mmc_from_priv(host); 798 798 - u64 timeout, clk_ns; 799 799 - u32 mode = 0; 798 798 + u64 timeout; 799 799 + u32 clk_ns, mode = 0; 800 800 801 801 if (mmc->actual_clock == 0) { 802 802 timeout = 0; 803 803 } else { 804 804 - clk_ns = 1000000000ULL; 805 805 - do_div(clk_ns, mmc->actual_clock); 804 804 + clk_ns = 1000000000U / mmc->actual_clock; 806 805 timeout = ns + clk_ns - 1; 807 806 do_div(timeout, clk_ns); 808 807 timeout += clks; ··· 830 831 831 832 timeout = msdc_timeout_cal(host, ns, clks); 832 833 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 833 833 - (u32)(timeout > 255 ? 255 : timeout)); 834 834 + min_t(u32, timeout, 255)); 834 835 } 835 836 836 837 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) ··· 839 840 840 841 timeout = msdc_timeout_cal(host, ns, clks); 841 842 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 842 842 - (u32)(timeout > 8191 ? 8191 : timeout)); 843 843 + min_t(u32, timeout, 8191)); 843 844 } 844 845 845 846 static void msdc_gate_clock(struct msdc_host *host)

+1

drivers/mmc/host/renesas_sdhi_internal_dmac.c

reviewed

··· 285 285 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 286 286 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 287 287 { .compatible = "renesas,sdhi-r9a09g011", .data = &of_rzg2l_compatible, }, 288 288 + { .compatible = "renesas,sdhi-r9a09g057", .data = &of_rzg2l_compatible, }, 288 289 { .compatible = "renesas,rzg2l-sdhi", .data = &of_rzg2l_compatible, }, 289 290 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 290 291 { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, },

+322 -156

drivers/mmc/host/sdhci-of-dwcmshc.c

reviewed

··· 8 8 */ 9 9 10 10 #include <linux/acpi.h> 11 11 + #include <linux/arm-smccc.h> 11 12 #include <linux/bitfield.h> 12 13 #include <linux/clk.h> 13 14 #include <linux/dma-mapping.h> ··· 109 108 #define DLL_LOCK_WO_TMOUT(x) \ 110 109 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 111 110 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 112 112 - #define RK35xx_MAX_CLKS 3 113 111 114 112 /* PHY register area pointer */ 115 113 #define DWC_MSHC_PTR_PHY_R 0x300 116 114 117 115 /* PHY general configuration */ 118 118 - #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) 119 119 - #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ 120 120 - #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ 121 121 - #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ 122 122 - #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ 123 123 - #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ 116 116 + #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) 117 117 + #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ 118 118 + #define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */ 119 119 + #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ 120 120 + #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ 121 121 + #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */ 122 122 + #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ 123 123 + #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ 124 124 + #define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */ 124 125 125 126 /* PHY command/response pad settings */ 126 127 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) ··· 151 148 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ 152 149 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ 153 150 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ 151 151 + #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */ 154 152 155 153 /* PHY CLK delay line settings */ 156 154 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) 157 157 - #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ 155 155 + #define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0) 156 156 + #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ 158 157 159 158 /* PHY CLK delay line delay code */ 160 159 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) ··· 164 159 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ 165 160 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ 166 161 162 162 + #define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20) 163 163 + #define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1) 164 164 + 167 165 /* PHY drift_cclk_rx delay line configuration setting */ 168 166 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) 169 167 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ 170 168 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ 169 169 + #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */ 171 170 172 171 /* PHY DLL control settings */ 173 172 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) ··· 202 193 SDHCI_TRNS_BLK_CNT_EN | \ 203 194 SDHCI_TRNS_DMA) 204 195 196 196 + /* SMC call for BlueField-3 eMMC RST_N */ 197 197 + #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 198 198 + 205 199 enum dwcmshc_rk_type { 206 200 DWCMSHC_RK3568, 207 201 DWCMSHC_RK3588, 208 202 }; 209 203 210 204 struct rk35xx_priv { 211 211 - /* Rockchip specified optional clocks */ 212 212 - struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; 213 205 struct reset_control *reset; 214 206 enum dwcmshc_rk_type devtype; 215 207 u8 txclk_tapnum; 216 208 }; 209 209 + 210 210 + #define DWCMSHC_MAX_OTHER_CLKS 3 217 211 218 212 struct dwcmshc_priv { 219 213 struct clk *bus_clk; 220 214 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ 221 215 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */ 222 216 217 217 + int num_other_clks; 218 218 + struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS]; 219 219 + 223 220 void *priv; /* pointer to SoC private stuff */ 224 221 u16 delay_line; 225 222 u16 flags; 226 223 }; 224 224 + 225 225 + struct dwcmshc_pltfm_data { 226 226 + const struct sdhci_pltfm_data pdata; 227 227 + int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 228 228 + void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 229 229 + }; 230 230 + 231 231 + static int dwcmshc_get_enable_other_clks(struct device *dev, 232 232 + struct dwcmshc_priv *priv, 233 233 + int num_clks, 234 234 + const char * const clk_ids[]) 235 235 + { 236 236 + int err; 237 237 + 238 238 + if (num_clks > DWCMSHC_MAX_OTHER_CLKS) 239 239 + return -EINVAL; 240 240 + 241 241 + for (int i = 0; i < num_clks; i++) 242 242 + priv->other_clks[i].id = clk_ids[i]; 243 243 + 244 244 + err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks); 245 245 + if (err) { 246 246 + dev_err(dev, "failed to get clocks %d\n", err); 247 247 + return err; 248 248 + } 249 249 + 250 250 + err = clk_bulk_prepare_enable(num_clks, priv->other_clks); 251 251 + if (err) 252 252 + dev_err(dev, "failed to enable clocks %d\n", err); 253 253 + 254 254 + priv->num_other_clks = num_clks; 255 255 + 256 256 + return err; 257 257 + } 227 258 228 259 /* 229 260 * If DMA addr spans 128MB boundary, we split the DMA transfer into two ··· 730 681 sdhci_reset(host, mask); 731 682 } 732 683 684 684 + static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host, 685 685 + struct dwcmshc_priv *dwc_priv) 686 686 + { 687 687 + static const char * const clk_ids[] = {"axi", "block", "timer"}; 688 688 + struct rk35xx_priv *priv; 689 689 + int err; 690 690 + 691 691 + priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 692 692 + if (!priv) 693 693 + return -ENOMEM; 694 694 + 695 695 + if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc")) 696 696 + priv->devtype = DWCMSHC_RK3588; 697 697 + else 698 698 + priv->devtype = DWCMSHC_RK3568; 699 699 + 700 700 + priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 701 701 + if (IS_ERR(priv->reset)) { 702 702 + err = PTR_ERR(priv->reset); 703 703 + dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 704 704 + return err; 705 705 + } 706 706 + 707 707 + err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 708 708 + ARRAY_SIZE(clk_ids), clk_ids); 709 709 + if (err) 710 710 + return err; 711 711 + 712 712 + if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 713 713 + &priv->txclk_tapnum)) 714 714 + priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 715 715 + 716 716 + /* Disable cmd conflict check */ 717 717 + sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 718 718 + /* Reset previous settings */ 719 719 + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 720 720 + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 721 721 + 722 722 + dwc_priv->priv = priv; 723 723 + 724 724 + return 0; 725 725 + } 726 726 + 727 727 + static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 728 728 + { 729 729 + /* 730 730 + * Don't support highspeed bus mode with low clk speed as we 731 731 + * cannot use DLL for this condition. 732 732 + */ 733 733 + if (host->mmc->f_max <= 52000000) { 734 734 + dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 735 735 + host->mmc->f_max); 736 736 + host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 737 737 + host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 738 738 + } 739 739 + } 740 740 + 733 741 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) 734 742 { 735 743 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ··· 859 753 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 860 754 } 861 755 } 756 756 + } 757 757 + 758 758 + static int th1520_init(struct device *dev, 759 759 + struct sdhci_host *host, 760 760 + struct dwcmshc_priv *dwc_priv) 761 761 + { 762 762 + dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; 763 763 + 764 764 + if (device_property_read_bool(dev, "mmc-ddr-1_8v") || 765 765 + device_property_read_bool(dev, "mmc-hs200-1_8v") || 766 766 + device_property_read_bool(dev, "mmc-hs400-1_8v")) 767 767 + dwc_priv->flags |= FLAG_IO_FIXED_1V8; 768 768 + else 769 769 + dwc_priv->flags &= ~FLAG_IO_FIXED_1V8; 770 770 + 771 771 + /* 772 772 + * start_signal_voltage_switch() will try 3.3V first 773 773 + * then 1.8V. Use SDHCI_SIGNALING_180 rather than 774 774 + * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V 775 775 + * in sdhci_start_signal_voltage_switch(). 776 776 + */ 777 777 + if (dwc_priv->flags & FLAG_IO_FIXED_1V8) { 778 778 + host->flags &= ~SDHCI_SIGNALING_330; 779 779 + host->flags |= SDHCI_SIGNALING_180; 780 780 + } 781 781 + 782 782 + sdhci_enable_v4_mode(host); 783 783 + 784 784 + return 0; 862 785 } 863 786 864 787 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) ··· 1026 891 return ret; 1027 892 } 1028 893 894 894 + static inline void sg2042_sdhci_phy_init(struct sdhci_host *host) 895 895 + { 896 896 + u32 val; 897 897 + 898 898 + /* Asset phy reset & set tx drive strength */ 899 899 + val = sdhci_readl(host, PHY_CNFG_R); 900 900 + val &= ~PHY_CNFG_RSTN_DEASSERT; 901 901 + val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1); 902 902 + val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042); 903 903 + val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042); 904 904 + sdhci_writel(host, val, PHY_CNFG_R); 905 905 + 906 906 + /* Configure phy pads */ 907 907 + val = PHY_PAD_RXSEL_3V3; 908 908 + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 909 909 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 910 910 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 911 911 + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 912 912 + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 913 913 + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 914 914 + 915 915 + val = PHY_PAD_RXSEL_3V3; 916 916 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 917 917 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 918 918 + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 919 919 + 920 920 + val = PHY_PAD_RXSEL_3V3; 921 921 + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 922 922 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 923 923 + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 924 924 + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 925 925 + 926 926 + /* Configure delay line */ 927 927 + /* Enable fixed delay */ 928 928 + sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R); 929 929 + /* 930 930 + * Set delay line. 931 931 + * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written. 932 932 + * Ensure UPDATE_DC[4] is '0' when not updating code. 933 933 + */ 934 934 + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 935 935 + val |= PHY_SDCLKDL_CNFG_UPDATE; 936 936 + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 937 937 + /* Add 10 * 70ps = 0.7ns for output delay */ 938 938 + sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R); 939 939 + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 940 940 + val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 941 941 + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 942 942 + 943 943 + /* Set SMPLDL_CNFG, Bypass */ 944 944 + sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R); 945 945 + 946 946 + /* Set ATDL_CNFG, tuning clk not use for init */ 947 947 + val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042); 948 948 + sdhci_writeb(host, val, PHY_ATDL_CNFG_R); 949 949 + 950 950 + /* Deasset phy reset */ 951 951 + val = sdhci_readl(host, PHY_CNFG_R); 952 952 + val |= PHY_CNFG_RSTN_DEASSERT; 953 953 + sdhci_writel(host, val, PHY_CNFG_R); 954 954 + } 955 955 + 956 956 + static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask) 957 957 + { 958 958 + sdhci_reset(host, mask); 959 959 + 960 960 + if (mask & SDHCI_RESET_ALL) 961 961 + sg2042_sdhci_phy_init(host); 962 962 + } 963 963 + 964 964 + static int sg2042_init(struct device *dev, struct sdhci_host *host, 965 965 + struct dwcmshc_priv *dwc_priv) 966 966 + { 967 967 + static const char * const clk_ids[] = {"timer"}; 968 968 + 969 969 + return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 970 970 + ARRAY_SIZE(clk_ids), clk_ids); 971 971 + } 972 972 + 1029 973 static const struct sdhci_ops sdhci_dwcmshc_ops = { 1030 974 .set_clock = sdhci_set_clock, 1031 975 .set_bus_width = sdhci_set_bus_width, ··· 1114 900 .adma_write_desc = dwcmshc_adma_write_desc, 1115 901 .irq = dwcmshc_cqe_irq_handler, 1116 902 }; 903 903 + 904 904 + #ifdef CONFIG_ACPI 905 905 + static void dwcmshc_bf3_hw_reset(struct sdhci_host *host) 906 906 + { 907 907 + struct arm_smccc_res res = { 0 }; 908 908 + 909 909 + arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res); 910 910 + 911 911 + if (res.a0) 912 912 + pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc)); 913 913 + } 914 914 + 915 915 + static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = { 916 916 + .set_clock = sdhci_set_clock, 917 917 + .set_bus_width = sdhci_set_bus_width, 918 918 + .set_uhs_signaling = dwcmshc_set_uhs_signaling, 919 919 + .get_max_clock = dwcmshc_get_max_clock, 920 920 + .reset = sdhci_reset, 921 921 + .adma_write_desc = dwcmshc_adma_write_desc, 922 922 + .irq = dwcmshc_cqe_irq_handler, 923 923 + .hw_reset = dwcmshc_bf3_hw_reset, 924 924 + }; 925 925 + #endif 1117 926 1118 927 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { 1119 928 .set_clock = dwcmshc_rk3568_set_clock, ··· 1169 932 .platform_execute_tuning = cv18xx_sdhci_execute_tuning, 1170 933 }; 1171 934 1172 1172 - static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { 1173 1173 - .ops = &sdhci_dwcmshc_ops, 1174 1174 - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1175 1175 - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 935 935 + static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { 936 936 + .set_clock = sdhci_set_clock, 937 937 + .set_bus_width = sdhci_set_bus_width, 938 938 + .set_uhs_signaling = dwcmshc_set_uhs_signaling, 939 939 + .get_max_clock = dwcmshc_get_max_clock, 940 940 + .reset = sg2042_sdhci_reset, 941 941 + .adma_write_desc = dwcmshc_adma_write_desc, 942 942 + .platform_execute_tuning = th1520_execute_tuning, 943 943 + }; 944 944 + 945 945 + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { 946 946 + .pdata = { 947 947 + .ops = &sdhci_dwcmshc_ops, 948 948 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 949 949 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 950 950 + }, 1176 951 }; 1177 952 1178 953 #ifdef CONFIG_ACPI 1179 1179 - static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { 1180 1180 - .ops = &sdhci_dwcmshc_ops, 1181 1181 - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1182 1182 - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1183 1183 - SDHCI_QUIRK2_ACMD23_BROKEN, 954 954 + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = { 955 955 + .pdata = { 956 956 + .ops = &sdhci_dwcmshc_bf3_ops, 957 957 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 958 958 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 959 959 + SDHCI_QUIRK2_ACMD23_BROKEN, 960 960 + }, 1184 961 }; 1185 962 #endif 1186 963 1187 1187 - static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 1188 1188 - .ops = &sdhci_dwcmshc_rk35xx_ops, 1189 1189 - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1190 1190 - SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 1191 1191 - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1192 1192 - SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 964 964 + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 965 965 + .pdata = { 966 966 + .ops = &sdhci_dwcmshc_rk35xx_ops, 967 967 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 968 968 + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 969 969 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 970 970 + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 971 971 + }, 972 972 + .init = dwcmshc_rk35xx_init, 973 973 + .postinit = dwcmshc_rk35xx_postinit, 1193 974 }; 1194 975 1195 1195 - static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = { 1196 1196 - .ops = &sdhci_dwcmshc_th1520_ops, 1197 1197 - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1198 1198 - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 976 976 + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { 977 977 + .pdata = { 978 978 + .ops = &sdhci_dwcmshc_th1520_ops, 979 979 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 980 980 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 981 981 + }, 982 982 + .init = th1520_init, 1199 983 }; 1200 984 1201 1201 - static const struct sdhci_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { 1202 1202 - .ops = &sdhci_dwcmshc_cv18xx_ops, 1203 1203 - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1204 1204 - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 985 985 + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { 986 986 + .pdata = { 987 987 + .ops = &sdhci_dwcmshc_cv18xx_ops, 988 988 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 989 989 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 990 990 + }, 991 991 + }; 992 992 + 993 993 + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { 994 994 + .pdata = { 995 995 + .ops = &sdhci_dwcmshc_sg2042_ops, 996 996 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 997 997 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 998 998 + }, 999 999 + .init = sg2042_init, 1205 1000 }; 1206 1001 1207 1002 static const struct cqhci_host_ops dwcmshc_cqhci_ops = { ··· 1303 1034 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); 1304 1035 } 1305 1036 1306 1306 - static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 1307 1307 - { 1308 1308 - int err; 1309 1309 - struct rk35xx_priv *priv = dwc_priv->priv; 1310 1310 - 1311 1311 - priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 1312 1312 - if (IS_ERR(priv->reset)) { 1313 1313 - err = PTR_ERR(priv->reset); 1314 1314 - dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 1315 1315 - return err; 1316 1316 - } 1317 1317 - 1318 1318 - priv->rockchip_clks[0].id = "axi"; 1319 1319 - priv->rockchip_clks[1].id = "block"; 1320 1320 - priv->rockchip_clks[2].id = "timer"; 1321 1321 - err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, 1322 1322 - priv->rockchip_clks); 1323 1323 - if (err) { 1324 1324 - dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); 1325 1325 - return err; 1326 1326 - } 1327 1327 - 1328 1328 - err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); 1329 1329 - if (err) { 1330 1330 - dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); 1331 1331 - return err; 1332 1332 - } 1333 1333 - 1334 1334 - if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 1335 1335 - &priv->txclk_tapnum)) 1336 1336 - priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 1337 1337 - 1338 1338 - /* Disable cmd conflict check */ 1339 1339 - sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 1340 1340 - /* Reset previous settings */ 1341 1341 - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 1342 1342 - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 1343 1343 - 1344 1344 - return 0; 1345 1345 - } 1346 1346 - 1347 1347 - static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 1348 1348 - { 1349 1349 - /* 1350 1350 - * Don't support highspeed bus mode with low clk speed as we 1351 1351 - * cannot use DLL for this condition. 1352 1352 - */ 1353 1353 - if (host->mmc->f_max <= 52000000) { 1354 1354 - dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 1355 1355 - host->mmc->f_max); 1356 1356 - host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 1357 1357 - host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 1358 1358 - } 1359 1359 - } 1360 1360 - 1361 1037 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { 1362 1038 { 1363 1039 .compatible = "rockchip,rk3588-dwcmshc", ··· 1328 1114 .compatible = "thead,th1520-dwcmshc", 1329 1115 .data = &sdhci_dwcmshc_th1520_pdata, 1330 1116 }, 1117 1117 + { 1118 1118 + .compatible = "sophgo,sg2042-dwcmshc", 1119 1119 + .data = &sdhci_dwcmshc_sg2042_pdata, 1120 1120 + }, 1331 1121 {}, 1332 1122 }; 1333 1123 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); ··· 1353 1135 struct sdhci_pltfm_host *pltfm_host; 1354 1136 struct sdhci_host *host; 1355 1137 struct dwcmshc_priv *priv; 1356 1356 - struct rk35xx_priv *rk_priv = NULL; 1357 1357 - const struct sdhci_pltfm_data *pltfm_data; 1138 1138 + const struct dwcmshc_pltfm_data *pltfm_data; 1358 1139 int err; 1359 1140 u32 extra, caps; 1360 1141 ··· 1363 1146 return -ENODEV; 1364 1147 } 1365 1148 1366 1366 - host = sdhci_pltfm_init(pdev, pltfm_data, 1149 1149 + host = sdhci_pltfm_init(pdev, &pltfm_data->pdata, 1367 1150 sizeof(struct dwcmshc_priv)); 1368 1151 if (IS_ERR(host)) 1369 1152 return PTR_ERR(host); ··· 1408 1191 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 1409 1192 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; 1410 1193 1411 1411 - if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { 1412 1412 - rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 1413 1413 - if (!rk_priv) { 1414 1414 - err = -ENOMEM; 1415 1415 - goto err_clk; 1416 1416 - } 1417 1417 - 1418 1418 - if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) 1419 1419 - rk_priv->devtype = DWCMSHC_RK3588; 1420 1420 - else 1421 1421 - rk_priv->devtype = DWCMSHC_RK3568; 1422 1422 - 1423 1423 - priv->priv = rk_priv; 1424 1424 - 1425 1425 - err = dwcmshc_rk35xx_init(host, priv); 1194 1194 + if (pltfm_data->init) { 1195 1195 + err = pltfm_data->init(&pdev->dev, host, priv); 1426 1196 if (err) 1427 1197 goto err_clk; 1428 1428 - } 1429 1429 - 1430 1430 - if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { 1431 1431 - priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; 1432 1432 - 1433 1433 - if (device_property_read_bool(dev, "mmc-ddr-1_8v") || 1434 1434 - device_property_read_bool(dev, "mmc-hs200-1_8v") || 1435 1435 - device_property_read_bool(dev, "mmc-hs400-1_8v")) 1436 1436 - priv->flags |= FLAG_IO_FIXED_1V8; 1437 1437 - else 1438 1438 - priv->flags &= ~FLAG_IO_FIXED_1V8; 1439 1439 - 1440 1440 - /* 1441 1441 - * start_signal_voltage_switch() will try 3.3V first 1442 1442 - * then 1.8V. Use SDHCI_SIGNALING_180 rather than 1443 1443 - * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V 1444 1444 - * in sdhci_start_signal_voltage_switch(). 1445 1445 - */ 1446 1446 - if (priv->flags & FLAG_IO_FIXED_1V8) { 1447 1447 - host->flags &= ~SDHCI_SIGNALING_330; 1448 1448 - host->flags |= SDHCI_SIGNALING_180; 1449 1449 - } 1450 1450 - 1451 1451 - sdhci_enable_v4_mode(host); 1452 1198 } 1453 1199 1454 1200 #ifdef CONFIG_ACPI ··· 1441 1261 dwcmshc_cqhci_init(host, pdev); 1442 1262 } 1443 1263 1444 1444 - if (rk_priv) 1445 1445 - dwcmshc_rk35xx_postinit(host, priv); 1264 1264 + if (pltfm_data->postinit) 1265 1265 + pltfm_data->postinit(host, priv); 1446 1266 1447 1267 err = __sdhci_add_host(host); 1448 1268 if (err) ··· 1460 1280 err_clk: 1461 1281 clk_disable_unprepare(pltfm_host->clk); 1462 1282 clk_disable_unprepare(priv->bus_clk); 1463 1463 - if (rk_priv) 1464 1464 - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1465 1465 - rk_priv->rockchip_clks); 1283 1283 + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1466 1284 free_pltfm: 1467 1285 sdhci_pltfm_free(pdev); 1468 1286 return err; ··· 1482 1304 struct sdhci_host *host = platform_get_drvdata(pdev); 1483 1305 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1484 1306 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1485 1485 - struct rk35xx_priv *rk_priv = priv->priv; 1486 1307 1487 1308 pm_runtime_get_sync(&pdev->dev); 1488 1309 pm_runtime_disable(&pdev->dev); ··· 1493 1316 1494 1317 clk_disable_unprepare(pltfm_host->clk); 1495 1318 clk_disable_unprepare(priv->bus_clk); 1496 1496 - if (rk_priv) 1497 1497 - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1498 1498 - rk_priv->rockchip_clks); 1319 1319 + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1499 1320 sdhci_pltfm_free(pdev); 1500 1321 } 1501 1322 ··· 1503 1328 struct sdhci_host *host = dev_get_drvdata(dev); 1504 1329 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1505 1330 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1506 1506 - struct rk35xx_priv *rk_priv = priv->priv; 1507 1331 int ret; 1508 1332 1509 1333 pm_runtime_resume(dev); ··· 1521 1347 if (!IS_ERR(priv->bus_clk)) 1522 1348 clk_disable_unprepare(priv->bus_clk); 1523 1349 1524 1524 - if (rk_priv) 1525 1525 - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1526 1526 - rk_priv->rockchip_clks); 1350 1350 + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1527 1351 1528 1352 return ret; 1529 1353 } ··· 1531 1359 struct sdhci_host *host = dev_get_drvdata(dev); 1532 1360 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1533 1361 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1534 1534 - struct rk35xx_priv *rk_priv = priv->priv; 1535 1362 int ret; 1536 1363 1537 1364 ret = clk_prepare_enable(pltfm_host->clk); ··· 1543 1372 goto disable_clk; 1544 1373 } 1545 1374 1546 1546 - if (rk_priv) { 1547 1547 - ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, 1548 1548 - rk_priv->rockchip_clks); 1549 1549 - if (ret) 1550 1550 - goto disable_bus_clk; 1551 1551 - } 1375 1375 + ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks); 1376 1376 + if (ret) 1377 1377 + goto disable_bus_clk; 1552 1378 1553 1379 ret = sdhci_resume_host(host); 1554 1380 if (ret) 1555 1555 - goto disable_rockchip_clks; 1381 1381 + goto disable_other_clks; 1556 1382 1557 1383 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1558 1384 ret = cqhci_resume(host->mmc); 1559 1385 if (ret) 1560 1560 - goto disable_rockchip_clks; 1386 1386 + goto disable_other_clks; 1561 1387 } 1562 1388 1563 1389 return 0; 1564 1390 1565 1565 - disable_rockchip_clks: 1566 1566 - if (rk_priv) 1567 1567 - clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1568 1568 - rk_priv->rockchip_clks); 1391 1391 + disable_other_clks: 1392 1392 + clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1569 1393 disable_bus_clk: 1570 1394 if (!IS_ERR(priv->bus_clk)) 1571 1395 clk_disable_unprepare(priv->bus_clk);

+314

drivers/mmc/host/sdhci-of-ma35d1.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Copyright (C) 2024 Nuvoton Technology Corp. 4 4 + * 5 5 + * Author: Shan-Chun Hung <shanchun1218@gmail.com> 6 6 + */ 7 7 + 8 8 + #include <linux/align.h> 9 9 + #include <linux/array_size.h> 10 10 + #include <linux/bits.h> 11 11 + #include <linux/build_bug.h> 12 12 + #include <linux/clk.h> 13 13 + #include <linux/delay.h> 14 14 + #include <linux/dev_printk.h> 15 15 + #include <linux/device.h> 16 16 + #include <linux/dma-mapping.h> 17 17 + #include <linux/err.h> 18 18 + #include <linux/math.h> 19 19 + #include <linux/mfd/syscon.h> 20 20 + #include <linux/minmax.h> 21 21 + #include <linux/mmc/card.h> 22 22 + #include <linux/mmc/host.h> 23 23 + #include <linux/mod_devicetable.h> 24 24 + #include <linux/module.h> 25 25 + #include <linux/pinctrl/consumer.h> 26 26 + #include <linux/platform_device.h> 27 27 + #include <linux/regmap.h> 28 28 + #include <linux/reset.h> 29 29 + #include <linux/sizes.h> 30 30 + #include <linux/types.h> 31 31 + 32 32 + #include "sdhci-pltfm.h" 33 33 + #include "sdhci.h" 34 34 + 35 35 + #define MA35_SYS_MISCFCR0 0x070 36 36 + #define MA35_SDHCI_MSHCCTL 0x508 37 37 + #define MA35_SDHCI_MBIUCTL 0x510 38 38 + 39 39 + #define MA35_SDHCI_CMD_CONFLICT_CHK BIT(0) 40 40 + #define MA35_SDHCI_INCR_MSK GENMASK(3, 0) 41 41 + #define MA35_SDHCI_INCR16 BIT(3) 42 42 + #define MA35_SDHCI_INCR8 BIT(2) 43 43 + 44 44 + struct ma35_priv { 45 45 + struct reset_control *rst; 46 46 + struct pinctrl *pinctrl; 47 47 + struct pinctrl_state *pins_uhs; 48 48 + struct pinctrl_state *pins_default; 49 49 + }; 50 50 + 51 51 + struct ma35_restore_data { 52 52 + u32 reg; 53 53 + u32 width; 54 54 + }; 55 55 + 56 56 + static const struct ma35_restore_data restore_data[] = { 57 57 + { SDHCI_CLOCK_CONTROL, sizeof(u32)}, 58 58 + { SDHCI_BLOCK_SIZE, sizeof(u32)}, 59 59 + { SDHCI_INT_ENABLE, sizeof(u32)}, 60 60 + { SDHCI_SIGNAL_ENABLE, sizeof(u32)}, 61 61 + { SDHCI_AUTO_CMD_STATUS, sizeof(u32)}, 62 62 + { SDHCI_HOST_CONTROL, sizeof(u32)}, 63 63 + { SDHCI_TIMEOUT_CONTROL, sizeof(u8) }, 64 64 + { MA35_SDHCI_MSHCCTL, sizeof(u16)}, 65 65 + { MA35_SDHCI_MBIUCTL, sizeof(u16)}, 66 66 + }; 67 67 + 68 68 + /* 69 69 + * If DMA addr spans 128MB boundary, we split the DMA transfer into two 70 70 + * so that each DMA transfer doesn't exceed the boundary. 71 71 + */ 72 72 + static void ma35_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, 73 73 + unsigned int cmd) 74 74 + { 75 75 + int tmplen, offset; 76 76 + 77 77 + if (likely(!len || (ALIGN(addr, SZ_128M) == ALIGN(addr + len - 1, SZ_128M)))) { 78 78 + sdhci_adma_write_desc(host, desc, addr, len, cmd); 79 79 + return; 80 80 + } 81 81 + 82 82 + offset = addr & (SZ_128M - 1); 83 83 + tmplen = SZ_128M - offset; 84 84 + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); 85 85 + 86 86 + addr += tmplen; 87 87 + len -= tmplen; 88 88 + sdhci_adma_write_desc(host, desc, addr, len, cmd); 89 89 + } 90 90 + 91 91 + static void ma35_set_clock(struct sdhci_host *host, unsigned int clock) 92 92 + { 93 93 + u32 ctl; 94 94 + 95 95 + /* 96 96 + * If the clock frequency exceeds MMC_HIGH_52_MAX_DTR, 97 97 + * disable command conflict check. 98 98 + */ 99 99 + ctl = sdhci_readw(host, MA35_SDHCI_MSHCCTL); 100 100 + if (clock > MMC_HIGH_52_MAX_DTR) 101 101 + ctl &= ~MA35_SDHCI_CMD_CONFLICT_CHK; 102 102 + else 103 103 + ctl |= MA35_SDHCI_CMD_CONFLICT_CHK; 104 104 + sdhci_writew(host, ctl, MA35_SDHCI_MSHCCTL); 105 105 + 106 106 + sdhci_set_clock(host, clock); 107 107 + } 108 108 + 109 109 + static int ma35_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 110 110 + { 111 111 + struct sdhci_host *host = mmc_priv(mmc); 112 112 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 113 113 + struct ma35_priv *priv = sdhci_pltfm_priv(pltfm_host); 114 114 + 115 115 + switch (ios->signal_voltage) { 116 116 + case MMC_SIGNAL_VOLTAGE_180: 117 117 + if (!IS_ERR(priv->pinctrl) && !IS_ERR(priv->pins_uhs)) 118 118 + pinctrl_select_state(priv->pinctrl, priv->pins_uhs); 119 119 + break; 120 120 + case MMC_SIGNAL_VOLTAGE_330: 121 121 + if (!IS_ERR(priv->pinctrl) && !IS_ERR(priv->pins_default)) 122 122 + pinctrl_select_state(priv->pinctrl, priv->pins_default); 123 123 + break; 124 124 + default: 125 125 + dev_err(mmc_dev(host->mmc), "Unsupported signal voltage!\n"); 126 126 + return -EINVAL; 127 127 + } 128 128 + 129 129 + return sdhci_start_signal_voltage_switch(mmc, ios); 130 130 + } 131 131 + 132 132 + static void ma35_voltage_switch(struct sdhci_host *host) 133 133 + { 134 134 + /* Wait for 5ms after set 1.8V signal enable bit */ 135 135 + fsleep(5000); 136 136 + } 137 137 + 138 138 + static int ma35_execute_tuning(struct mmc_host *mmc, u32 opcode) 139 139 + { 140 140 + struct sdhci_host *host = mmc_priv(mmc); 141 141 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 142 142 + struct ma35_priv *priv = sdhci_pltfm_priv(pltfm_host); 143 143 + int idx; 144 144 + u32 regs[ARRAY_SIZE(restore_data)] = {}; 145 145 + 146 146 + /* 147 147 + * Limitations require a reset of SD/eMMC before tuning and 148 148 + * saving the registers before resetting, then restoring 149 149 + * after the reset. 150 150 + */ 151 151 + for (idx = 0; idx < ARRAY_SIZE(restore_data); idx++) { 152 152 + if (restore_data[idx].width == sizeof(u32)) 153 153 + regs[idx] = sdhci_readl(host, restore_data[idx].reg); 154 154 + else if (restore_data[idx].width == sizeof(u16)) 155 155 + regs[idx] = sdhci_readw(host, restore_data[idx].reg); 156 156 + else if (restore_data[idx].width == sizeof(u8)) 157 157 + regs[idx] = sdhci_readb(host, restore_data[idx].reg); 158 158 + } 159 159 + 160 160 + reset_control_assert(priv->rst); 161 161 + reset_control_deassert(priv->rst); 162 162 + 163 163 + for (idx = 0; idx < ARRAY_SIZE(restore_data); idx++) { 164 164 + if (restore_data[idx].width == sizeof(u32)) 165 165 + sdhci_writel(host, regs[idx], restore_data[idx].reg); 166 166 + else if (restore_data[idx].width == sizeof(u16)) 167 167 + sdhci_writew(host, regs[idx], restore_data[idx].reg); 168 168 + else if (restore_data[idx].width == sizeof(u8)) 169 169 + sdhci_writeb(host, regs[idx], restore_data[idx].reg); 170 170 + } 171 171 + 172 172 + return sdhci_execute_tuning(mmc, opcode); 173 173 + } 174 174 + 175 175 + static const struct sdhci_ops sdhci_ma35_ops = { 176 176 + .set_clock = ma35_set_clock, 177 177 + .set_bus_width = sdhci_set_bus_width, 178 178 + .set_uhs_signaling = sdhci_set_uhs_signaling, 179 179 + .get_max_clock = sdhci_pltfm_clk_get_max_clock, 180 180 + .reset = sdhci_reset, 181 181 + .adma_write_desc = ma35_adma_write_desc, 182 182 + .voltage_switch = ma35_voltage_switch, 183 183 + }; 184 184 + 185 185 + static const struct sdhci_pltfm_data sdhci_ma35_pdata = { 186 186 + .ops = &sdhci_ma35_ops, 187 187 + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 188 188 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_BROKEN_DDR50 | 189 189 + SDHCI_QUIRK2_ACMD23_BROKEN, 190 190 + }; 191 191 + 192 192 + static int ma35_probe(struct platform_device *pdev) 193 193 + { 194 194 + struct device *dev = &pdev->dev; 195 195 + struct sdhci_pltfm_host *pltfm_host; 196 196 + struct sdhci_host *host; 197 197 + struct ma35_priv *priv; 198 198 + int err; 199 199 + u32 extra, ctl; 200 200 + 201 201 + host = sdhci_pltfm_init(pdev, &sdhci_ma35_pdata, sizeof(struct ma35_priv)); 202 202 + if (IS_ERR(host)) 203 203 + return PTR_ERR(host); 204 204 + 205 205 + /* Extra adma table cnt for cross 128M boundary handling. */ 206 206 + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); 207 207 + extra = min(extra, SDHCI_MAX_SEGS); 208 208 + 209 209 + host->adma_table_cnt += extra; 210 210 + pltfm_host = sdhci_priv(host); 211 211 + priv = sdhci_pltfm_priv(pltfm_host); 212 212 + 213 213 + pltfm_host->clk = devm_clk_get_optional_enabled(dev, NULL); 214 214 + if (IS_ERR(pltfm_host->clk)) { 215 215 + err = dev_err_probe(dev, PTR_ERR(pltfm_host->clk), "failed to get clk\n"); 216 216 + goto err_sdhci; 217 217 + } 218 218 + 219 219 + err = mmc_of_parse(host->mmc); 220 220 + if (err) 221 221 + goto err_sdhci; 222 222 + 223 223 + priv->rst = devm_reset_control_get_exclusive(dev, NULL); 224 224 + if (IS_ERR(priv->rst)) { 225 225 + err = dev_err_probe(dev, PTR_ERR(priv->rst), "failed to get reset control\n"); 226 226 + goto err_sdhci; 227 227 + } 228 228 + 229 229 + sdhci_get_of_property(pdev); 230 230 + 231 231 + priv->pinctrl = devm_pinctrl_get(dev); 232 232 + if (!IS_ERR(priv->pinctrl)) { 233 233 + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, "default"); 234 234 + priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, "state_uhs"); 235 235 + pinctrl_select_state(priv->pinctrl, priv->pins_default); 236 236 + } 237 237 + 238 238 + if (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)) { 239 239 + struct regmap *regmap; 240 240 + u32 reg; 241 241 + 242 242 + regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sys"); 243 243 + if (!IS_ERR(regmap)) { 244 244 + /* Enable SDHCI voltage stable for 1.8V */ 245 245 + regmap_read(regmap, MA35_SYS_MISCFCR0, &reg); 246 246 + reg |= BIT(17); 247 247 + regmap_write(regmap, MA35_SYS_MISCFCR0, reg); 248 248 + } 249 249 + 250 250 + host->mmc_host_ops.start_signal_voltage_switch = 251 251 + ma35_start_signal_voltage_switch; 252 252 + } 253 253 + 254 254 + host->mmc_host_ops.execute_tuning = ma35_execute_tuning; 255 255 + 256 256 + err = sdhci_add_host(host); 257 257 + if (err) 258 258 + goto err_sdhci; 259 259 + 260 260 + /* 261 261 + * Split data into chunks of 16 or 8 bytes for transmission. 262 262 + * Each chunk transfer is guaranteed to be uninterrupted on the bus. 263 263 + * This likely corresponds to the AHB bus DMA burst size. 264 264 + */ 265 265 + ctl = sdhci_readw(host, MA35_SDHCI_MBIUCTL); 266 266 + ctl &= ~MA35_SDHCI_INCR_MSK; 267 267 + ctl |= MA35_SDHCI_INCR16 | MA35_SDHCI_INCR8; 268 268 + sdhci_writew(host, ctl, MA35_SDHCI_MBIUCTL); 269 269 + 270 270 + return 0; 271 271 + 272 272 + err_sdhci: 273 273 + sdhci_pltfm_free(pdev); 274 274 + return err; 275 275 + } 276 276 + 277 277 + static void ma35_disable_card_clk(struct sdhci_host *host) 278 278 + { 279 279 + u16 ctrl; 280 280 + 281 281 + ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 282 282 + if (ctrl & SDHCI_CLOCK_CARD_EN) { 283 283 + ctrl &= ~SDHCI_CLOCK_CARD_EN; 284 284 + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 285 285 + } 286 286 + } 287 287 + 288 288 + static void ma35_remove(struct platform_device *pdev) 289 289 + { 290 290 + struct sdhci_host *host = platform_get_drvdata(pdev); 291 291 + 292 292 + sdhci_remove_host(host, 0); 293 293 + ma35_disable_card_clk(host); 294 294 + sdhci_pltfm_free(pdev); 295 295 + } 296 296 + 297 297 + static const struct of_device_id sdhci_ma35_dt_ids[] = { 298 298 + { .compatible = "nuvoton,ma35d1-sdhci" }, 299 299 + {} 300 300 + }; 301 301 + 302 302 + static struct platform_driver sdhci_ma35_driver = { 303 303 + .driver = { 304 304 + .name = "sdhci-ma35", 305 305 + .of_match_table = sdhci_ma35_dt_ids, 306 306 + }, 307 307 + .probe = ma35_probe, 308 308 + .remove_new = ma35_remove, 309 309 + }; 310 310 + module_platform_driver(sdhci_ma35_driver); 311 311 + 312 312 + MODULE_DESCRIPTION("SDHCI platform driver for Nuvoton MA35"); 313 313 + MODULE_AUTHOR("Shan-Chun Hung <shanchun1218@gmail.com>"); 314 314 + MODULE_LICENSE("GPL");

+1 -1

drivers/mmc/host/sdhci-pxav2.c

reviewed

··· 126 126 struct sdhci_pxav2_host *pxav2_host; 127 127 128 128 /* If this is an SDIO command, perform errata workaround for silicon bug */ 129 129 - if (mrq->cmd && !mrq->cmd->error && 129 129 + if (!mrq->cmd->error && 130 130 (mrq->cmd->opcode == SD_IO_RW_DIRECT || 131 131 mrq->cmd->opcode == SD_IO_RW_EXTENDED)) { 132 132 /* Reset data port */

+43 -11

drivers/mmc/host/sdhci_am654.c

reviewed

··· 86 86 87 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 89 89 + #define RETRY_TUNING_MAX 10 89 90 90 91 /* Command Queue Host Controller Interface Base address */ 91 92 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 ··· 152 151 u32 flags; 153 152 u32 quirks; 154 153 bool dll_enable; 154 154 + u32 tuning_loop; 155 155 156 156 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 157 157 }; ··· 445 443 #define ITAPDLY_LENGTH 32 446 444 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 447 445 448 448 - static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 446 446 + static int sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 449 447 *fail_window, u8 num_fails, bool circular_buffer) 450 448 { 451 449 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; ··· 455 453 int prev_fail_end = -1; 456 454 u8 i; 457 455 458 458 - if (!num_fails) 459 459 - return ITAPDLY_LAST_INDEX >> 1; 456 456 + if (!num_fails) { 457 457 + /* Retry tuning */ 458 458 + dev_dbg(dev, "No failing region found, retry tuning\n"); 459 459 + return -1; 460 460 + } 460 461 461 462 if (fail_window->length == ITAPDLY_LENGTH) { 462 462 - dev_err(dev, "No passing ITAPDLY, return 0\n"); 463 463 - return 0; 463 463 + /* Retry tuning */ 464 464 + dev_dbg(dev, "No passing itapdly, retry tuning\n"); 465 465 + return -1; 464 466 } 465 467 466 468 first_fail_start = fail_window->start; ··· 500 494 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 501 495 } 502 496 503 503 - static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 504 504 - u32 opcode) 497 497 + static int sdhci_am654_do_tuning(struct sdhci_host *host, 498 498 + u32 opcode) 505 499 { 506 500 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 507 501 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 508 502 unsigned char timing = host->mmc->ios.timing; 509 503 struct window fail_window[ITAPDLY_LENGTH]; 504 504 + struct device *dev = mmc_dev(host->mmc); 510 505 u8 curr_pass, itap; 511 506 u8 fail_index = 0; 512 507 u8 prev_pass = 1; ··· 528 521 if (!curr_pass) { 529 522 fail_window[fail_index].end = itap; 530 523 fail_window[fail_index].length++; 524 524 + dev_dbg(dev, "Failed itapdly=%d\n", itap); 531 525 } 532 526 533 527 if (curr_pass && !prev_pass) ··· 540 532 if (fail_window[fail_index].length != 0) 541 533 fail_index++; 542 534 543 543 - itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 544 544 - sdhci_am654->dll_enable); 535 535 + return sdhci_am654_calculate_itap(host, fail_window, fail_index, 536 536 + sdhci_am654->dll_enable); 537 537 + } 545 538 546 546 - sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 539 539 + static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 540 540 + u32 opcode) 541 541 + { 542 542 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 543 543 + struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 544 544 + unsigned char timing = host->mmc->ios.timing; 545 545 + struct device *dev = mmc_dev(host->mmc); 546 546 + int itapdly; 547 547 548 548 + do { 549 549 + itapdly = sdhci_am654_do_tuning(host, opcode); 550 550 + if (itapdly >= 0) 551 551 + break; 552 552 + } while (++sdhci_am654->tuning_loop < RETRY_TUNING_MAX); 553 553 + 554 554 + if (itapdly < 0) { 555 555 + dev_err(dev, "Failed to find itapdly, fail tuning\n"); 556 556 + return -1; 557 557 + } 558 558 + 559 559 + dev_dbg(dev, "Passed tuning, final itapdly=%d\n", itapdly); 560 560 + sdhci_am654_write_itapdly(sdhci_am654, itapdly, sdhci_am654->itap_del_ena[timing]); 548 561 /* Save ITAPDLY */ 549 549 - sdhci_am654->itap_del_sel[timing] = itap; 562 562 + sdhci_am654->itap_del_sel[timing] = itapdly; 550 563 551 564 return 0; 552 565 } ··· 770 741 /* Enable tuning for SDR50 */ 771 742 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 772 743 TUNINGFORSDR50_MASK); 744 744 + 745 745 + /* Use to re-execute tuning */ 746 746 + sdhci_am654->tuning_loop = 0; 773 747 774 748 ret = sdhci_setup_host(host); 775 749 if (ret)

+3 -4

drivers/mmc/host/tmio_mmc_core.c

reviewed

··· 895 895 * It seems, VccQ should be switched on after Vcc, this is also what the 896 896 * omap_hsmmc.c driver does. 897 897 */ 898 898 - if (!IS_ERR(mmc->supply.vqmmc) && !ret) { 899 899 - ret = regulator_enable(mmc->supply.vqmmc); 898 898 + if (!ret) { 899 899 + ret = mmc_regulator_enable_vqmmc(mmc); 900 900 usleep_range(200, 300); 901 901 } 902 902 ··· 909 909 { 910 910 struct mmc_host *mmc = host->mmc; 911 911 912 912 - if (!IS_ERR(mmc->supply.vqmmc)) 913 913 - regulator_disable(mmc->supply.vqmmc); 912 912 + mmc_regulator_disable_vqmmc(mmc); 914 913 915 914 if (!IS_ERR(mmc->supply.vmmc)) 916 915 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);

+1

drivers/tee/optee/Kconfig

reviewed

··· 4 4 tristate "OP-TEE" 5 5 depends on HAVE_ARM_SMCCC 6 6 depends on MMU 7 7 + depends on RPMB || !RPMB 7 8 help 8 9 This implements the OP-TEE Trusted Execution Environment (TEE) 9 10 driver.

+95 -1

drivers/tee/optee/core.c

reviewed

··· 10 10 #include <linux/errno.h> 11 11 #include <linux/io.h> 12 12 #include <linux/module.h> 13 13 + #include <linux/rpmb.h> 13 14 #include <linux/slab.h> 14 15 #include <linux/string.h> 15 16 #include <linux/tee_core.h> 16 17 #include <linux/types.h> 17 18 #include "optee_private.h" 18 19 20 20 + struct blocking_notifier_head optee_rpmb_intf_added = 21 21 + BLOCKING_NOTIFIER_INIT(optee_rpmb_intf_added); 22 22 + 23 23 + static int rpmb_add_dev(struct device *dev) 24 24 + { 25 25 + blocking_notifier_call_chain(&optee_rpmb_intf_added, 0, 26 26 + to_rpmb_dev(dev)); 27 27 + 28 28 + return 0; 29 29 + } 30 30 + 31 31 + static struct class_interface rpmb_class_intf = { 32 32 + .add_dev = rpmb_add_dev, 33 33 + }; 34 34 + 35 35 + void optee_bus_scan_rpmb(struct work_struct *work) 36 36 + { 37 37 + struct optee *optee = container_of(work, struct optee, 38 38 + rpmb_scan_bus_work); 39 39 + int ret; 40 40 + 41 41 + if (!optee->rpmb_scan_bus_done) { 42 42 + ret = optee_enumerate_devices(PTA_CMD_GET_DEVICES_RPMB); 43 43 + optee->rpmb_scan_bus_done = !ret; 44 44 + if (ret && ret != -ENODEV) 45 45 + pr_info("Scanning for RPMB device: ret %d\n", ret); 46 46 + } 47 47 + } 48 48 + 49 49 + int optee_rpmb_intf_rdev(struct notifier_block *intf, unsigned long action, 50 50 + void *data) 51 51 + { 52 52 + struct optee *optee = container_of(intf, struct optee, rpmb_intf); 53 53 + 54 54 + schedule_work(&optee->rpmb_scan_bus_work); 55 55 + 56 56 + return 0; 57 57 + } 58 58 + 19 59 static void optee_bus_scan(struct work_struct *work) 20 60 { 21 61 WARN_ON(optee_enumerate_devices(PTA_CMD_GET_DEVICES_SUPP)); 62 62 + } 63 63 + 64 64 + static ssize_t rpmb_routing_model_show(struct device *dev, 65 65 + struct device_attribute *attr, char *buf) 66 66 + { 67 67 + struct optee *optee = dev_get_drvdata(dev); 68 68 + const char *s; 69 69 + 70 70 + if (optee->in_kernel_rpmb_routing) 71 71 + s = "kernel"; 72 72 + else 73 73 + s = "user"; 74 74 + 75 75 + return scnprintf(buf, PAGE_SIZE, "%s\n", s); 76 76 + } 77 77 + static DEVICE_ATTR_RO(rpmb_routing_model); 78 78 + 79 79 + static struct attribute *optee_dev_attrs[] = { 80 80 + &dev_attr_rpmb_routing_model.attr, 81 81 + NULL 82 82 + }; 83 83 + 84 84 + ATTRIBUTE_GROUPS(optee_dev); 85 85 + 86 86 + void optee_set_dev_group(struct optee *optee) 87 87 + { 88 88 + tee_device_set_dev_groups(optee->teedev, optee_dev_groups); 89 89 + tee_device_set_dev_groups(optee->supp_teedev, optee_dev_groups); 22 90 } 23 91 24 92 int optee_open(struct tee_context *ctx, bool cap_memref_null) ··· 165 97 166 98 void optee_remove_common(struct optee *optee) 167 99 { 100 100 + blocking_notifier_chain_unregister(&optee_rpmb_intf_added, 101 101 + &optee->rpmb_intf); 102 102 + cancel_work_sync(&optee->rpmb_scan_bus_work); 168 103 /* Unregister OP-TEE specific client devices on TEE bus */ 169 104 optee_unregister_devices(); 170 105 ··· 184 113 tee_shm_pool_free(optee->pool); 185 114 optee_supp_uninit(&optee->supp); 186 115 mutex_destroy(&optee->call_queue.mutex); 116 116 + rpmb_dev_put(optee->rpmb_dev); 117 117 + mutex_destroy(&optee->rpmb_dev_mutex); 187 118 } 188 119 189 120 static int smc_abi_rc; 190 121 static int ffa_abi_rc; 122 122 + static bool intf_is_regged; 191 123 192 124 static int __init optee_core_init(void) 193 125 { 126 126 + int rc; 127 127 + 194 128 /* 195 129 * The kernel may have crashed at the same time that all available 196 130 * secure world threads were suspended and we cannot reschedule the ··· 206 130 if (is_kdump_kernel()) 207 131 return -ENODEV; 208 132 133 133 + if (IS_REACHABLE(CONFIG_RPMB)) { 134 134 + rc = rpmb_interface_register(&rpmb_class_intf); 135 135 + if (rc) 136 136 + return rc; 137 137 + intf_is_regged = true; 138 138 + } 139 139 + 209 140 smc_abi_rc = optee_smc_abi_register(); 210 141 ffa_abi_rc = optee_ffa_abi_register(); 211 142 212 143 /* If both failed there's no point with this module */ 213 213 - if (smc_abi_rc && ffa_abi_rc) 144 144 + if (smc_abi_rc && ffa_abi_rc) { 145 145 + if (IS_REACHABLE(CONFIG_RPMB)) { 146 146 + rpmb_interface_unregister(&rpmb_class_intf); 147 147 + intf_is_regged = false; 148 148 + } 214 149 return smc_abi_rc; 150 150 + } 151 151 + 215 152 return 0; 216 153 } 217 154 module_init(optee_core_init); 218 155 219 156 static void __exit optee_core_exit(void) 220 157 { 158 158 + if (IS_REACHABLE(CONFIG_RPMB) && intf_is_regged) { 159 159 + rpmb_interface_unregister(&rpmb_class_intf); 160 160 + intf_is_regged = false; 161 161 + } 162 162 + 221 163 if (!smc_abi_rc) 222 164 optee_smc_abi_unregister(); 223 165 if (!ffa_abi_rc)

+7

drivers/tee/optee/device.c

reviewed

··· 43 43 ret = tee_client_invoke_func(ctx, &inv_arg, param); 44 44 if ((ret < 0) || ((inv_arg.ret != TEEC_SUCCESS) && 45 45 (inv_arg.ret != TEEC_ERROR_SHORT_BUFFER))) { 46 46 + /* 47 47 + * TEE_ERROR_STORAGE_NOT_AVAILABLE is returned when getting 48 48 + * the list of device TAs that depends on RPMB but a usable 49 49 + * RPMB device isn't found. 50 50 + */ 51 51 + if (inv_arg.ret == TEE_ERROR_STORAGE_NOT_AVAILABLE) 52 52 + return -ENODEV; 46 53 pr_err("PTA_CMD_GET_DEVICES invoke function err: %x\n", 47 54 inv_arg.ret); 48 55 return -EINVAL;

+14

drivers/tee/optee/ffa_abi.c

reviewed

··· 7 7 8 8 #include <linux/arm_ffa.h> 9 9 #include <linux/errno.h> 10 10 + #include <linux/rpmb.h> 10 11 #include <linux/scatterlist.h> 11 12 #include <linux/sched.h> 12 13 #include <linux/slab.h> ··· 910 909 optee->ffa.bottom_half_value = U32_MAX; 911 910 optee->rpc_param_count = rpc_param_count; 912 911 912 912 + if (IS_REACHABLE(CONFIG_RPMB) && 913 913 + (sec_caps & OPTEE_FFA_SEC_CAP_RPMB_PROBE)) 914 914 + optee->in_kernel_rpmb_routing = true; 915 915 + 913 916 teedev = tee_device_alloc(&optee_ffa_clnt_desc, NULL, optee->pool, 914 917 optee); 915 918 if (IS_ERR(teedev)) { ··· 930 925 } 931 926 optee->supp_teedev = teedev; 932 927 928 928 + optee_set_dev_group(optee); 929 929 + 933 930 rc = tee_device_register(optee->teedev); 934 931 if (rc) 935 932 goto err_unreg_supp_teedev; ··· 947 940 optee_cq_init(&optee->call_queue, 0); 948 941 optee_supp_init(&optee->supp); 949 942 optee_shm_arg_cache_init(optee, arg_cache_flags); 943 943 + mutex_init(&optee->rpmb_dev_mutex); 950 944 ffa_dev_set_drvdata(ffa_dev, optee); 951 945 ctx = teedev_open(optee->teedev); 952 946 if (IS_ERR(ctx)) { ··· 969 961 if (rc) 970 962 goto err_unregister_devices; 971 963 964 964 + INIT_WORK(&optee->rpmb_scan_bus_work, optee_bus_scan_rpmb); 965 965 + optee->rpmb_intf.notifier_call = optee_rpmb_intf_rdev; 966 966 + blocking_notifier_chain_register(&optee_rpmb_intf_added, 967 967 + &optee->rpmb_intf); 972 968 pr_info("initialized driver\n"); 973 969 return 0; 974 970 ··· 986 974 teedev_close_context(ctx); 987 975 err_rhashtable_free: 988 976 rhashtable_free_and_destroy(&optee->ffa.global_ids, rh_free_fn, NULL); 977 977 + rpmb_dev_put(optee->rpmb_dev); 978 978 + mutex_destroy(&optee->rpmb_dev_mutex); 989 979 optee_supp_uninit(&optee->supp); 990 980 mutex_destroy(&optee->call_queue.mutex); 991 981 mutex_destroy(&optee->ffa.mutex);

+2

drivers/tee/optee/optee_ffa.h

reviewed

··· 92 92 #define OPTEE_FFA_SEC_CAP_ARG_OFFSET BIT(0) 93 93 /* OP-TEE supports asynchronous notification via FF-A */ 94 94 #define OPTEE_FFA_SEC_CAP_ASYNC_NOTIF BIT(1) 95 95 + /* OP-TEE supports probing for RPMB device if needed */ 96 96 + #define OPTEE_FFA_SEC_CAP_RPMB_PROBE BIT(2) 95 97 96 98 #define OPTEE_FFA_EXCHANGE_CAPABILITIES OPTEE_FFA_BLOCKING_CALL(2) 97 99

+25 -1

drivers/tee/optee/optee_private.h

reviewed

··· 7 7 #define OPTEE_PRIVATE_H 8 8 9 9 #include <linux/arm-smccc.h> 10 10 + #include <linux/notifier.h> 10 11 #include <linux/rhashtable.h> 12 12 + #include <linux/rpmb.h> 11 13 #include <linux/semaphore.h> 12 14 #include <linux/tee_core.h> 13 15 #include <linux/types.h> ··· 22 20 /* Some Global Platform error codes used in this driver */ 23 21 #define TEEC_SUCCESS 0x00000000 24 22 #define TEEC_ERROR_BAD_PARAMETERS 0xFFFF0006 23 23 + #define TEEC_ERROR_ITEM_NOT_FOUND 0xFFFF0008 25 24 #define TEEC_ERROR_NOT_SUPPORTED 0xFFFF000A 26 25 #define TEEC_ERROR_COMMUNICATION 0xFFFF000E 27 26 #define TEEC_ERROR_OUT_OF_MEMORY 0xFFFF000C ··· 31 28 32 29 /* API Return Codes are from the GP TEE Internal Core API Specification */ 33 30 #define TEE_ERROR_TIMEOUT 0xFFFF3001 31 31 + #define TEE_ERROR_STORAGE_NOT_AVAILABLE 0xF0100003 34 32 35 33 #define TEEC_ORIGIN_COMMS 0x00000002 36 34 ··· 204 200 * @notif: notification synchronization struct 205 201 * @supp: supplicant synchronization struct for RPC to supplicant 206 202 * @pool: shared memory pool 203 203 + * @mutex: mutex protecting @rpmb_dev 204 204 + * @rpmb_dev: current RPMB device or NULL 205 205 + * @rpmb_scan_bus_done flag if device registation of RPMB dependent devices 206 206 + * was already done 207 207 + * @rpmb_scan_bus_work workq to for an RPMB device and to scan optee bus 208 208 + * and register RPMB dependent optee drivers 207 209 * @rpc_param_count: If > 0 number of RPC parameters to make room for 208 210 * @scan_bus_done flag if device registation was already done. 209 211 * @scan_bus_work workq to scan optee bus and register optee drivers ··· 228 218 struct optee_notif notif; 229 219 struct optee_supp supp; 230 220 struct tee_shm_pool *pool; 221 221 + /* Protects rpmb_dev pointer */ 222 222 + struct mutex rpmb_dev_mutex; 223 223 + struct rpmb_dev *rpmb_dev; 224 224 + struct notifier_block rpmb_intf; 231 225 unsigned int rpc_param_count; 232 232 - bool scan_bus_done; 226 226 + bool scan_bus_done; 227 227 + bool rpmb_scan_bus_done; 228 228 + bool in_kernel_rpmb_routing; 233 229 struct work_struct scan_bus_work; 230 230 + struct work_struct rpmb_scan_bus_work; 234 231 }; 235 232 236 233 struct optee_session { ··· 270 253 size_t num_entries; 271 254 }; 272 255 256 256 + extern struct blocking_notifier_head optee_rpmb_intf_added; 257 257 + 273 258 int optee_notif_init(struct optee *optee, u_int max_key); 274 259 void optee_notif_uninit(struct optee *optee); 275 260 int optee_notif_wait(struct optee *optee, u_int key, u32 timeout); ··· 302 283 303 284 #define PTA_CMD_GET_DEVICES 0x0 304 285 #define PTA_CMD_GET_DEVICES_SUPP 0x1 286 286 + #define PTA_CMD_GET_DEVICES_RPMB 0x2 305 287 int optee_enumerate_devices(u32 func); 306 288 void optee_unregister_devices(void); 289 289 + void optee_bus_scan_rpmb(struct work_struct *work); 290 290 + int optee_rpmb_intf_rdev(struct notifier_block *intf, unsigned long action, 291 291 + void *data); 307 292 293 293 + void optee_set_dev_group(struct optee *optee); 308 294 void optee_remove_common(struct optee *optee); 309 295 int optee_open(struct tee_context *ctx, bool cap_memref_null); 310 296 void optee_release(struct tee_context *ctx);

+35

drivers/tee/optee/optee_rpc_cmd.h

reviewed

··· 104 104 /* I2C master control flags */ 105 105 #define OPTEE_RPC_I2C_FLAGS_TEN_BIT BIT(0) 106 106 107 107 + /* 108 108 + * Reset RPMB probing 109 109 + * 110 110 + * Releases an eventually already used RPMB devices and starts over searching 111 111 + * for RPMB devices. Returns the kind of shared memory to use in subsequent 112 112 + * OPTEE_RPC_CMD_RPMB_PROBE_NEXT and OPTEE_RPC_CMD_RPMB calls. 113 113 + * 114 114 + * [out] value[0].a OPTEE_RPC_SHM_TYPE_*, the parameter for 115 115 + * OPTEE_RPC_CMD_SHM_ALLOC 116 116 + */ 117 117 + #define OPTEE_RPC_CMD_RPMB_PROBE_RESET 22 118 118 + 119 119 + /* 120 120 + * Probe next RPMB device 121 121 + * 122 122 + * [out] value[0].a Type of RPMB device, OPTEE_RPC_RPMB_* 123 123 + * [out] value[0].b EXT CSD-slice 168 "RPMB Size" 124 124 + * [out] value[0].c EXT CSD-slice 222 "Reliable Write Sector Count" 125 125 + * [out] memref[1] Buffer with the raw CID 126 126 + */ 127 127 + #define OPTEE_RPC_CMD_RPMB_PROBE_NEXT 23 128 128 + 129 129 + /* Type of RPMB device */ 130 130 + #define OPTEE_RPC_RPMB_EMMC 0 131 131 + #define OPTEE_RPC_RPMB_UFS 1 132 132 + #define OPTEE_RPC_RPMB_NVME 2 133 133 + 134 134 + /* 135 135 + * Replay Protected Memory Block access 136 136 + * 137 137 + * [in] memref[0] Frames to device 138 138 + * [out] memref[1] Frames from device 139 139 + */ 140 140 + #define OPTEE_RPC_CMD_RPMB_FRAMES 24 141 141 + 107 142 #endif /*__OPTEE_RPC_CMD_H*/

+2

drivers/tee/optee/optee_smc.h

reviewed

··· 278 278 #define OPTEE_SMC_SEC_CAP_ASYNC_NOTIF BIT(5) 279 279 /* Secure world supports pre-allocating RPC arg struct */ 280 280 #define OPTEE_SMC_SEC_CAP_RPC_ARG BIT(6) 281 281 + /* Secure world supports probing for RPMB device if needed */ 282 282 + #define OPTEE_SMC_SEC_CAP_RPMB_PROBE BIT(7) 281 283 282 284 #define OPTEE_SMC_FUNCID_EXCHANGE_CAPABILITIES 9 283 285 #define OPTEE_SMC_EXCHANGE_CAPABILITIES \

+177

drivers/tee/optee/rpc.c

reviewed

··· 7 7 8 8 #include <linux/delay.h> 9 9 #include <linux/i2c.h> 10 10 + #include <linux/rpmb.h> 10 11 #include <linux/slab.h> 11 12 #include <linux/tee_core.h> 12 13 #include "optee_private.h" ··· 262 261 optee_supp_thrd_req(ctx, OPTEE_RPC_CMD_SHM_FREE, 1, &param); 263 262 } 264 263 264 264 + static void handle_rpc_func_rpmb_probe_reset(struct tee_context *ctx, 265 265 + struct optee *optee, 266 266 + struct optee_msg_arg *arg) 267 267 + { 268 268 + struct tee_param params[1]; 269 269 + 270 270 + if (arg->num_params != ARRAY_SIZE(params) || 271 271 + optee->ops->from_msg_param(optee, params, arg->num_params, 272 272 + arg->params) || 273 273 + params[0].attr != TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT) { 274 274 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 275 275 + return; 276 276 + } 277 277 + 278 278 + params[0].u.value.a = OPTEE_RPC_SHM_TYPE_KERNEL; 279 279 + params[0].u.value.b = 0; 280 280 + params[0].u.value.c = 0; 281 281 + if (optee->ops->to_msg_param(optee, arg->params, 282 282 + arg->num_params, params)) { 283 283 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 284 284 + return; 285 285 + } 286 286 + 287 287 + mutex_lock(&optee->rpmb_dev_mutex); 288 288 + rpmb_dev_put(optee->rpmb_dev); 289 289 + optee->rpmb_dev = NULL; 290 290 + mutex_unlock(&optee->rpmb_dev_mutex); 291 291 + 292 292 + arg->ret = TEEC_SUCCESS; 293 293 + } 294 294 + 295 295 + static int rpmb_type_to_rpc_type(enum rpmb_type rtype) 296 296 + { 297 297 + switch (rtype) { 298 298 + case RPMB_TYPE_EMMC: 299 299 + return OPTEE_RPC_RPMB_EMMC; 300 300 + case RPMB_TYPE_UFS: 301 301 + return OPTEE_RPC_RPMB_UFS; 302 302 + case RPMB_TYPE_NVME: 303 303 + return OPTEE_RPC_RPMB_NVME; 304 304 + default: 305 305 + return -1; 306 306 + } 307 307 + } 308 308 + 309 309 + static int rpc_rpmb_match(struct device *dev, const void *data) 310 310 + { 311 311 + struct rpmb_dev *rdev = to_rpmb_dev(dev); 312 312 + 313 313 + return rpmb_type_to_rpc_type(rdev->descr.type) >= 0; 314 314 + } 315 315 + 316 316 + static void handle_rpc_func_rpmb_probe_next(struct tee_context *ctx, 317 317 + struct optee *optee, 318 318 + struct optee_msg_arg *arg) 319 319 + { 320 320 + struct rpmb_dev *rdev; 321 321 + struct tee_param params[2]; 322 322 + void *buf; 323 323 + 324 324 + if (arg->num_params != ARRAY_SIZE(params) || 325 325 + optee->ops->from_msg_param(optee, params, arg->num_params, 326 326 + arg->params) || 327 327 + params[0].attr != TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT || 328 328 + params[1].attr != TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT) { 329 329 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 330 330 + return; 331 331 + } 332 332 + buf = tee_shm_get_va(params[1].u.memref.shm, 333 333 + params[1].u.memref.shm_offs); 334 334 + if (IS_ERR(buf)) { 335 335 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 336 336 + return; 337 337 + } 338 338 + 339 339 + mutex_lock(&optee->rpmb_dev_mutex); 340 340 + rdev = rpmb_dev_find_device(NULL, optee->rpmb_dev, rpc_rpmb_match); 341 341 + rpmb_dev_put(optee->rpmb_dev); 342 342 + optee->rpmb_dev = rdev; 343 343 + mutex_unlock(&optee->rpmb_dev_mutex); 344 344 + 345 345 + if (!rdev) { 346 346 + arg->ret = TEEC_ERROR_ITEM_NOT_FOUND; 347 347 + return; 348 348 + } 349 349 + 350 350 + if (params[1].u.memref.size < rdev->descr.dev_id_len) { 351 351 + arg->ret = TEEC_ERROR_SHORT_BUFFER; 352 352 + return; 353 353 + } 354 354 + memcpy(buf, rdev->descr.dev_id, rdev->descr.dev_id_len); 355 355 + params[1].u.memref.size = rdev->descr.dev_id_len; 356 356 + params[0].u.value.a = rpmb_type_to_rpc_type(rdev->descr.type); 357 357 + params[0].u.value.b = rdev->descr.capacity; 358 358 + params[0].u.value.c = rdev->descr.reliable_wr_count; 359 359 + if (optee->ops->to_msg_param(optee, arg->params, 360 360 + arg->num_params, params)) { 361 361 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 362 362 + return; 363 363 + } 364 364 + 365 365 + arg->ret = TEEC_SUCCESS; 366 366 + } 367 367 + 368 368 + static void handle_rpc_func_rpmb_frames(struct tee_context *ctx, 369 369 + struct optee *optee, 370 370 + struct optee_msg_arg *arg) 371 371 + { 372 372 + struct tee_param params[2]; 373 373 + struct rpmb_dev *rdev; 374 374 + void *p0, *p1; 375 375 + 376 376 + mutex_lock(&optee->rpmb_dev_mutex); 377 377 + rdev = rpmb_dev_get(optee->rpmb_dev); 378 378 + mutex_unlock(&optee->rpmb_dev_mutex); 379 379 + if (!rdev) { 380 380 + arg->ret = TEEC_ERROR_ITEM_NOT_FOUND; 381 381 + return; 382 382 + } 383 383 + 384 384 + if (arg->num_params != ARRAY_SIZE(params) || 385 385 + optee->ops->from_msg_param(optee, params, arg->num_params, 386 386 + arg->params) || 387 387 + params[0].attr != TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT || 388 388 + params[1].attr != TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT) { 389 389 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 390 390 + goto out; 391 391 + } 392 392 + 393 393 + p0 = tee_shm_get_va(params[0].u.memref.shm, 394 394 + params[0].u.memref.shm_offs); 395 395 + p1 = tee_shm_get_va(params[1].u.memref.shm, 396 396 + params[1].u.memref.shm_offs); 397 397 + if (rpmb_route_frames(rdev, p0, params[0].u.memref.size, p1, 398 398 + params[1].u.memref.size)) { 399 399 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 400 400 + goto out; 401 401 + } 402 402 + if (optee->ops->to_msg_param(optee, arg->params, 403 403 + arg->num_params, params)) { 404 404 + arg->ret = TEEC_ERROR_BAD_PARAMETERS; 405 405 + goto out; 406 406 + } 407 407 + arg->ret = TEEC_SUCCESS; 408 408 + out: 409 409 + rpmb_dev_put(rdev); 410 410 + } 411 411 + 265 412 void optee_rpc_cmd(struct tee_context *ctx, struct optee *optee, 266 413 struct optee_msg_arg *arg) 267 414 { ··· 425 276 break; 426 277 case OPTEE_RPC_CMD_I2C_TRANSFER: 427 278 handle_rpc_func_cmd_i2c_transfer(ctx, arg); 279 279 + break; 280 280 + /* 281 281 + * optee->in_kernel_rpmb_routing true means that OP-TEE supports 282 282 + * in-kernel RPMB routing _and_ that the RPMB subsystem is 283 283 + * reachable. This is reported to user space with 284 284 + * rpmb_routing_model=kernel in sysfs. 285 285 + * 286 286 + * rpmb_routing_model=kernel is also a promise to user space that 287 287 + * RPMB access will not require supplicant support, hence the 288 288 + * checks below. 289 289 + */ 290 290 + case OPTEE_RPC_CMD_RPMB_PROBE_RESET: 291 291 + if (optee->in_kernel_rpmb_routing) 292 292 + handle_rpc_func_rpmb_probe_reset(ctx, optee, arg); 293 293 + else 294 294 + handle_rpc_supp_cmd(ctx, optee, arg); 295 295 + break; 296 296 + case OPTEE_RPC_CMD_RPMB_PROBE_NEXT: 297 297 + if (optee->in_kernel_rpmb_routing) 298 298 + handle_rpc_func_rpmb_probe_next(ctx, optee, arg); 299 299 + else 300 300 + handle_rpc_supp_cmd(ctx, optee, arg); 301 301 + break; 302 302 + case OPTEE_RPC_CMD_RPMB_FRAMES: 303 303 + if (optee->in_kernel_rpmb_routing) 304 304 + handle_rpc_func_rpmb_frames(ctx, optee, arg); 305 305 + else 306 306 + handle_rpc_supp_cmd(ctx, optee, arg); 428 307 break; 429 308 default: 430 309 handle_rpc_supp_cmd(ctx, optee, arg);

+14

drivers/tee/optee/smc_abi.c

reviewed

··· 20 20 #include <linux/of_irq.h> 21 21 #include <linux/of_platform.h> 22 22 #include <linux/platform_device.h> 23 23 + #include <linux/rpmb.h> 23 24 #include <linux/sched.h> 24 25 #include <linux/slab.h> 25 26 #include <linux/string.h> ··· 1686 1685 optee->smc.sec_caps = sec_caps; 1687 1686 optee->rpc_param_count = rpc_param_count; 1688 1687 1688 1688 + if (IS_REACHABLE(CONFIG_RPMB) && 1689 1689 + (sec_caps & OPTEE_SMC_SEC_CAP_RPMB_PROBE)) 1690 1690 + optee->in_kernel_rpmb_routing = true; 1691 1691 + 1689 1692 teedev = tee_device_alloc(&optee_clnt_desc, NULL, pool, optee); 1690 1693 if (IS_ERR(teedev)) { 1691 1694 rc = PTR_ERR(teedev); ··· 1704 1699 } 1705 1700 optee->supp_teedev = teedev; 1706 1701 1702 1702 + optee_set_dev_group(optee); 1703 1703 + 1707 1704 rc = tee_device_register(optee->teedev); 1708 1705 if (rc) 1709 1706 goto err_unreg_supp_teedev; ··· 1719 1712 optee->smc.memremaped_shm = memremaped_shm; 1720 1713 optee->pool = pool; 1721 1714 optee_shm_arg_cache_init(optee, arg_cache_flags); 1715 1715 + mutex_init(&optee->rpmb_dev_mutex); 1722 1716 1723 1717 platform_set_drvdata(pdev, optee); 1724 1718 ctx = teedev_open(optee->teedev); ··· 1774 1766 if (rc) 1775 1767 goto err_disable_shm_cache; 1776 1768 1769 1769 + INIT_WORK(&optee->rpmb_scan_bus_work, optee_bus_scan_rpmb); 1770 1770 + optee->rpmb_intf.notifier_call = optee_rpmb_intf_rdev; 1771 1771 + blocking_notifier_chain_register(&optee_rpmb_intf_added, 1772 1772 + &optee->rpmb_intf); 1777 1773 pr_info("initialized driver\n"); 1778 1774 return 0; 1779 1775 ··· 1791 1779 err_close_ctx: 1792 1780 teedev_close_context(ctx); 1793 1781 err_supp_uninit: 1782 1782 + rpmb_dev_put(optee->rpmb_dev); 1783 1783 + mutex_destroy(&optee->rpmb_dev_mutex); 1794 1784 optee_shm_arg_cache_uninit(optee); 1795 1785 optee_supp_uninit(&optee->supp); 1796 1786 mutex_destroy(&optee->call_queue.mutex);

+13 -6

drivers/tee/tee_core.c

reviewed

··· 40 40 static DECLARE_BITMAP(dev_mask, TEE_NUM_DEVICES); 41 41 static DEFINE_SPINLOCK(driver_lock); 42 42 43 43 - static const struct class tee_class = { 44 44 - .name = "tee", 45 45 - }; 46 46 - 43 43 + static const struct class tee_class; 47 44 static dev_t tee_devt; 48 45 49 46 struct tee_context *teedev_open(struct tee_device *teedev) ··· 962 965 } 963 966 EXPORT_SYMBOL_GPL(tee_device_alloc); 964 967 968 968 + void tee_device_set_dev_groups(struct tee_device *teedev, 969 969 + const struct attribute_group **dev_groups) 970 970 + { 971 971 + teedev->dev.groups = dev_groups; 972 972 + } 973 973 + EXPORT_SYMBOL_GPL(tee_device_set_dev_groups); 974 974 + 965 975 static ssize_t implementation_id_show(struct device *dev, 966 976 struct device_attribute *attr, char *buf) 967 977 { ··· 987 983 988 984 ATTRIBUTE_GROUPS(tee_dev); 989 985 986 986 + static const struct class tee_class = { 987 987 + .name = "tee", 988 988 + .dev_groups = tee_dev_groups, 989 989 + }; 990 990 + 990 991 /** 991 992 * tee_device_register() - Registers a TEE device 992 993 * @teedev: Device to register ··· 1009 1000 dev_err(&teedev->dev, "attempt to register twice\n"); 1010 1001 return -EINVAL; 1011 1002 } 1012 1012 - 1013 1013 - teedev->dev.groups = tee_dev_groups; 1014 1003 1015 1004 rc = cdev_device_add(&teedev->cdev, &teedev->dev); 1016 1005 if (rc) {

-12

include/linux/mmc/core.h

reviewed

··· 11 11 struct mmc_data; 12 12 struct mmc_request; 13 13 14 14 - enum mmc_blk_status { 15 15 - MMC_BLK_SUCCESS = 0, 16 16 - MMC_BLK_PARTIAL, 17 17 - MMC_BLK_CMD_ERR, 18 18 - MMC_BLK_RETRY, 19 19 - MMC_BLK_ABORT, 20 20 - MMC_BLK_DATA_ERR, 21 21 - MMC_BLK_ECC_ERR, 22 22 - MMC_BLK_NOMEDIUM, 23 23 - MMC_BLK_NEW_REQUEST, 24 24 - }; 25 25 - 26 14 struct mmc_command { 27 15 u32 opcode; 28 16 u32 arg;

+2 -25

include/linux/mmc/host.h

reviewed

··· 264 264 void (*cqe_recovery_finish)(struct mmc_host *host); 265 265 }; 266 266 267 267 - struct mmc_async_req { 268 268 - /* active mmc request */ 269 269 - struct mmc_request *mrq; 270 270 - /* 271 271 - * Check error status of completed mmc request. 272 272 - * Returns 0 if success otherwise non zero. 273 273 - */ 274 274 - enum mmc_blk_status (*err_check)(struct mmc_card *, struct mmc_async_req *); 275 275 - }; 276 276 - 277 267 /** 278 268 * struct mmc_slot - MMC slot functions 279 269 * ··· 279 289 int cd_irq; 280 290 bool cd_wake_enabled; 281 291 void *handler_priv; 282 282 - }; 283 283 - 284 284 - /** 285 285 - * mmc_context_info - synchronization details for mmc context 286 286 - * @is_done_rcv wake up reason was done request 287 287 - * @is_new_req wake up reason was new request 288 288 - * @is_waiting_last_req mmc context waiting for single running request 289 289 - * @wait wait queue 290 290 - */ 291 291 - struct mmc_context_info { 292 292 - bool is_done_rcv; 293 293 - bool is_new_req; 294 294 - bool is_waiting_last_req; 295 295 - wait_queue_head_t wait; 296 292 }; 297 293 298 294 struct regulator; ··· 648 672 host->err_stats[stat] += 1; 649 673 } 650 674 651 651 - int mmc_sd_switch(struct mmc_card *card, int mode, int group, u8 value, u8 *resp); 675 675 + int mmc_sd_switch(struct mmc_card *card, bool mode, int group, 676 676 + u8 value, u8 *resp); 652 677 int mmc_send_status(struct mmc_card *card, u32 *status); 653 678 int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); 654 679 int mmc_send_abort_tuning(struct mmc_host *host, u32 opcode);

+123

include/linux/rpmb.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Copyright (C) 2015-2019 Intel Corp. All rights reserved 4 4 + * Copyright (C) 2021-2022 Linaro Ltd 5 5 + */ 6 6 + #ifndef __RPMB_H__ 7 7 + #define __RPMB_H__ 8 8 + 9 9 + #include <linux/device.h> 10 10 + #include <linux/types.h> 11 11 + 12 12 + /** 13 13 + * enum rpmb_type - type of underlying storage technology 14 14 + * 15 15 + * @RPMB_TYPE_EMMC : emmc (JESD84-B50.1) 16 16 + * @RPMB_TYPE_UFS : UFS (JESD220) 17 17 + * @RPMB_TYPE_NVME : NVM Express 18 18 + */ 19 19 + enum rpmb_type { 20 20 + RPMB_TYPE_EMMC, 21 21 + RPMB_TYPE_UFS, 22 22 + RPMB_TYPE_NVME, 23 23 + }; 24 24 + 25 25 + /** 26 26 + * struct rpmb_descr - RPMB description provided by the underlying block device 27 27 + * 28 28 + * @type : block device type 29 29 + * @route_frames : routes frames to and from the RPMB device 30 30 + * @dev_id : unique device identifier read from the hardware 31 31 + * @dev_id_len : length of unique device identifier 32 32 + * @reliable_wr_count: number of sectors that can be written in one access 33 33 + * @capacity : capacity of the device in units of 128K 34 34 + * 35 35 + * @dev_id is intended to be used as input when deriving the authenticaion key. 36 36 + */ 37 37 + struct rpmb_descr { 38 38 + enum rpmb_type type; 39 39 + int (*route_frames)(struct device *dev, u8 *req, unsigned int req_len, 40 40 + u8 *resp, unsigned int resp_len); 41 41 + u8 *dev_id; 42 42 + size_t dev_id_len; 43 43 + u16 reliable_wr_count; 44 44 + u16 capacity; 45 45 + }; 46 46 + 47 47 + /** 48 48 + * struct rpmb_dev - device which can support RPMB partition 49 49 + * 50 50 + * @dev : device 51 51 + * @id : device_id 52 52 + * @list_node : linked list node 53 53 + * @descr : RPMB description 54 54 + */ 55 55 + struct rpmb_dev { 56 56 + struct device dev; 57 57 + int id; 58 58 + struct list_head list_node; 59 59 + struct rpmb_descr descr; 60 60 + }; 61 61 + 62 62 + #define to_rpmb_dev(x) container_of((x), struct rpmb_dev, dev) 63 63 + 64 64 + #if IS_ENABLED(CONFIG_RPMB) 65 65 + struct rpmb_dev *rpmb_dev_get(struct rpmb_dev *rdev); 66 66 + void rpmb_dev_put(struct rpmb_dev *rdev); 67 67 + struct rpmb_dev *rpmb_dev_find_device(const void *data, 68 68 + const struct rpmb_dev *start, 69 69 + int (*match)(struct device *dev, 70 70 + const void *data)); 71 71 + int rpmb_interface_register(struct class_interface *intf); 72 72 + void rpmb_interface_unregister(struct class_interface *intf); 73 73 + struct rpmb_dev *rpmb_dev_register(struct device *dev, 74 74 + struct rpmb_descr *descr); 75 75 + int rpmb_dev_unregister(struct rpmb_dev *rdev); 76 76 + 77 77 + int rpmb_route_frames(struct rpmb_dev *rdev, u8 *req, 78 78 + unsigned int req_len, u8 *resp, unsigned int resp_len); 79 79 + 80 80 + #else 81 81 + static inline struct rpmb_dev *rpmb_dev_get(struct rpmb_dev *rdev) 82 82 + { 83 83 + return NULL; 84 84 + } 85 85 + 86 86 + static inline void rpmb_dev_put(struct rpmb_dev *rdev) { } 87 87 + 88 88 + static inline struct rpmb_dev * 89 89 + rpmb_dev_find_device(const void *data, const struct rpmb_dev *start, 90 90 + int (*match)(struct device *dev, const void *data)) 91 91 + { 92 92 + return NULL; 93 93 + } 94 94 + 95 95 + static inline int rpmb_interface_register(struct class_interface *intf) 96 96 + { 97 97 + return -EOPNOTSUPP; 98 98 + } 99 99 + 100 100 + static inline void rpmb_interface_unregister(struct class_interface *intf) 101 101 + { 102 102 + } 103 103 + 104 104 + static inline struct rpmb_dev * 105 105 + rpmb_dev_register(struct device *dev, struct rpmb_descr *descr) 106 106 + { 107 107 + return NULL; 108 108 + } 109 109 + 110 110 + static inline int rpmb_dev_unregister(struct rpmb_dev *dev) 111 111 + { 112 112 + return 0; 113 113 + } 114 114 + 115 115 + static inline int rpmb_route_frames(struct rpmb_dev *rdev, u8 *req, 116 116 + unsigned int req_len, u8 *resp, 117 117 + unsigned int resp_len) 118 118 + { 119 119 + return -EOPNOTSUPP; 120 120 + } 121 121 + #endif /* CONFIG_RPMB */ 122 122 + 123 123 + #endif /* __RPMB_H__ */

+12

include/linux/tee_core.h

reviewed

··· 155 155 void tee_device_unregister(struct tee_device *teedev); 156 156 157 157 /** 158 158 + * tee_device_set_dev_groups() - Set device attribute groups 159 159 + * @teedev: Device to register 160 160 + * @dev_groups: Attribute groups 161 161 + * 162 162 + * Assigns the provided @dev_groups to the @teedev to be registered later 163 163 + * with tee_device_register(). Calling this function is optional, but if 164 164 + * it's called it must be called before tee_device_register(). 165 165 + */ 166 166 + void tee_device_set_dev_groups(struct tee_device *teedev, 167 167 + const struct attribute_group **dev_groups); 168 168 + 169 169 + /** 158 170 * tee_session_calc_client_uuid() - Calculates client UUID for session 159 171 * @uuid: Resulting UUID 160 172 * @connection_method: Connection method for session (TEE_IOCTL_LOGIN_*)